.NOLIST
.INCLUDE "m88def.inc"
.LIST
; ATmega88
; Verze pro komunikaci s ostatnima periferiema: 0.3 (melo by byt kompatibilni
  ; od pocatku verzovani gitem)

; PROGRAMOVANO PRO 20MHz krystal!!! Zvlast kriticke pro male casove zakladny!

; *-----------------------------------------*
; |              Promenne                   |
; *-----------------------------------------*
  ; Kody museji byt shodne pro buffer i pro main_uC

  ; Kody pro synchronizaci
.EQU sync_code_1 = $FA
.EQU sync_code_2 = $02
.EQU sync_code_3 = $DA

  ; Kody po resetu
.EQU reset_code_1 = $AA
.EQU reset_code_2 = $0D
.EQU reset_code_3 = $FC

  ; Kod, ktery se objevi na sbernici behem resetu
.EQU reset_in_progress = $2A	; Melo by byt mensi jak $3F, jinak je zapotrebi
  ; upravit kod manualne (v preruseni -> nastavi se pouze 6 LSB)



.EQU If_error_detected_stop = 1
  ; Touto promennou si nastavujeme chovani bufferu v pripade, ze nastane chyba.
  ; Napr. prijata casova zakladna neni v seznamu znamych. Jsou dve moznosti:
  ; budto to buffer bude ignorovat (0) a proste pouzije defaultni hodnoty, nebo
  ; se zastavi (1) a pomuze akorat reset

; *-----------------------------------------*
; |        POJMENOVANI REGISTRU             |
; *-----------------------------------------*

.DEF tmp = R16	; docasna data
.DEF number = R17	; vetsinou nejake cislo, ktere predstavuje napr.
  ; prevedene A/D cislo atd...
.DEF CNT = R18	; pro cykly
.DEF number_of_samples	= R24	; sem se bude ukladat informace o tom, kolik
  ; vzorku uzivatel vyzaduje a pokud to bude mozne, takovyto pocet vozrku
  ; se ulozi do SRAM (minimum je 100, maximum pak 255). Minimum si musi hlidat
  ; main uC!
.DEF number2 = R25

.DEF trigger_mode = R20		; sem se ulozi informace o tom ,zda se
  ; bude spoustet na vzestupnou, nebo sestupnou hranu atd....


  ; Promenne pro casove prodlevy
.DEF time1 = R21
.DEF time2 = R22
.DEF time3 = R23



; *-----------------------------------------*
; |   POJMENOVANI PORTU, PINU, RAM ADRESY   |
; *-----------------------------------------*

; *-----------------------------------------*
; |          DATOVY PORT PRO AD             |
; *-----------------------------------------*
.EQU data_port_AD = PortD
.EQU data_port_AD_IN = PinD
.EQU data_port_AD_IO = DDRD	; pro zjednoduseni vstupu a vystupu

; *-----------------------------------------*
; | DATOVY PORT PRO KOMUNIKACI S MAIN_uC    |
; *-----------------------------------------*
  ; Zde narazime na problem ohledne vstupu. Uz nam nezbyl zadny 8. bitovy. 
  ; takze si proste tento port "rozkouskujeme"
  ; Prvnich 6 nejnizsich bitu bude tady, zbytek na jinem portu

.EQU data_port_with_main = PortC		; tento port bude slouzit
  ; pro komunikaci mezi Bufferem a main_uC
.EQU data_port_with_main_IN = PinC	; nekdy bude vstupni a nekdy zase
  ; vysstupni
.EQU data_port_with_main_IO = DDRC	; pro zjednoduseni vstupu a vystupu


.EQU data_bit_0 = 0	; LSB
.EQU data_bit_1 = 1	; LSB+1
.EQU data_bit_2 = 2	; LSB+2
.EQU data_bit_3 = 3	; LSB+3
.EQU data_bit_4 = 4	; LSB+4
.EQU data_bit_5 = 5	; LSB+5

; *-----------------------------------------*
; |              OVLADACI PORT              |
; *-----------------------------------------*

.EQU control_port = PortB	; Tento port bude slouzit jako ovladaci
.EQU control_port_in = PinB	; a nektere vystupy budou vstupni
.EQU control_port_IO = DDRB	; pro zjednoduseni nastaveni vstupu a vystupu

.EQU main_ready = 0	; priznak pripravenosti ke cteni dat z bufferu
.EQU buffer_ready = 1	; priznak pripravenosti bufferu odeslat data
.EQU trigger_input = 2	; informace od spousteni

.EQU LED = 3	; LED pro debug

  ; A jeste sem musime "nahazet" zbyvajici bity co se "nevesli"
.EQU data_bit_6 = 4	; LSB+6
.EQU data_bit_7 = 5	; LSB+7 = MSB
; *-----------------------------------------*
; |            ADRESY V SRAM                |
; *-----------------------------------------*

; Nastaveni pojmenovani urcitych adres v SRAM
  ; ATmega88 ma pocatek SRAM pro obecne pouziti od adresy 0x0100 (narozdil
  ; od ATmega32 a ATmega8!!!)
.EQU TimeBaseSRAM = $0100	; adrese $0100 jsme priradili jmeno
  ; TimeBaseSRAM - sem se bude ukladat informace o zvolene casove zakladne

.EQU Samples_begin_SRAM = TimeBaseSRAM+1
  ; od teto adresy se budou ukladat jednotlive
  ; vzorky z A/D do SRAM

; *-----------------------------------------*
; |                PRERUSENI                |
; *-----------------------------------------*
.EQU RESET = $000
; .EQU Loop_for_WDT = $0020	; Tato hodnota je tu proto, aby se mohlo zvolit
;   ; jakekoli preruseni a nenastal omylem skok na tuto adresu.

.ORG RESET	; Po spusteni/resetu....
	RJMP Init	; Inicializace, nastaveni defaultnich hodnot
.ORG PCI0addr	; Pri zmene stavu na datove sbernici
	RJMP Software_reset	; Reset bufferu vynuceny od hlavni jednotky

; .ORG Loop_for_WDT
; Loop_WDT:	; Nekonecna smycka
; 	RJMP Loop_WDT


Software_reset:
	LDI tmp,(0<<PCINT1)

	STS PCMSK0,tmp	; Tim se vypne preruseni na pinu PCINT1

	LDI tmp,$FF
	OUT data_port_with_main_IO,tmp	; Nastaveni datoveho portu s main_uC na
  ; vystupni
	SBI control_port_IO,data_bit_6	; Tyto piny patri k tomuto dat. portu
	SBI control_port_IO,data_bit_7


	CBI control_port,data_bit_6	; Nastaveni vystupu na log. 0
	CBI control_port,data_bit_7	; Nastaveni vystupu na log. 0

	LDI tmp,reset_in_progress
	OUT data_port_with_main,tmp	; Dame vedet, ze se reset zdaril :)

; 	; Zapne watchdog
; 	LDI tmp,(0<<WDIE)|(1<<WDE)|(0<<WDP3)|(0<<WDP2)|(0<<WDP1)|(0<<WDP0)
; 	STS WDTCSR,tmp	; Zapisi se data do vhodneho registru
; 
; 	;hack, aby pri RETI nastal skok na mnou pozadovanou smycku
; 	LDI tmp,HIGH(RAMEND)
; 	OUT SPH,tmp
; 	LDI tmp,LOW(RAMEND)
; 	OUT SPL,tmp
; 
; 	LDI tmp,LOW(Loop_for_WDT)
; 	PUSH tmp
; 	LDI tmp,HIGH(Loop_for_WDT)
; 	PUSH tmp

  ; HACK
    ; Navratova hodnota ve stacku se preulozi na 
	LDI tmp,LOW(Init)
	PUSH tmp
	LDI tmp,HIGH(Init)
	PUSH tmp

	RETI	; Navrat na adresu, na kterou odkazuje Stack Poiner. Diky
  ; tomuto "hacku" bude nasledovat skok na "Loop_WDT"
; *-----------------------------------------*
; |              INICIALIZACE               |
; *-----------------------------------------*
Init:
; 	; Vypne watchdog
; 	WDR	; Resetuje pocitadlo u watchdogu. Pro vsechny pripady...
; 	CLI	; Vypne globalni preruseni - pri prvnim spusteni nema smysl,
;   ; ale pri restartu bufferu hlavni jednotkou to smysl ma. Je to proto, ze
;   ; pokud by se definovaly dalsi preruseni, pak by se mohly zavolat jeste
;   ; drive, nez by byla inicializace provedena (a vsechny promenne nastaveny
;   ; na defaultni hodnoty)
; 
; ;	IN tmp,MCUSR
; ;	ANDI tmp,($FF & (0<<WDRF))
; 	LDI tmp,(0<<WDRF)	; Nastavi registry "natvrdo", bez ohledu na to,
;   ; co zde bylo predtim. Koneckoncu chceme restart, ne? :)
; 	OUT MCUSR,tmp
; 
; ;	LDS tmp,WDTCSR
; ;	ORI tmp,(1<<WDCE)|(1<<WDE)
; 	LDI tmp,(1<<WDCE)|(1<<WDE)
; 	STS WDTCSR, tmp
; 
; 	LDI tmp,(0<<WDE)
; 	STS WDTCSR,tmp
; 
; 	; ted by mel byt Watchdog vyply


	LDI tmp,LOW(RAMEND)
	OUT SPL,tmp
	LDI tmp,HIGH(RAMEND)
	OUT SPH,tmp

	CLI	; Vypne globalni preruseni	; Poznamka: kvuli hacku nemuze
  ; byt po preruseni ihned prikaz CLI. Nevim proc, ale jink se mi to nerozjelo

; Nastaveni I/O
	LDI tmp,$00
	OUT data_port_AD_IO,tmp		; data_port_AD - cely vstupni

	CBI control_port,buffer_ready	; buffer_ready - 0 (vypne pull-up)
	CBI control_port,main_ready	; main_ready - 0 (vypne pull-up)
	CBI control_port,trigger_input	; Vypne Pull-up odpory

	CBI control_port_IO,buffer_ready	; buffer_ready - vstupni
  ; (pokud bude potreba, aby byl vstupni, pak se prenastavi)
	CBI control_port_IO,main_ready	; main_ready - vstupni

	CBI control_port_IO,trigger_input	; bude vstupni


	SBI control_port_IO,LED	; Pro debug. Nastavi LED jako vystupni
	CBI control_port_IO,LED	; Pro debug. Nastavi LED jako vyplou

  ; Nastaveni defaultnich hodnot
	LDI trigger_mode,0	; "0" -> spousteni na vzestupnou hranu
  ; "1"  by bylo spousteni na sestupnou hranu, 2 bez synchrnonizace
	LDI number_of_samples,200	; 200 vzorku se ulozi do pameti SRAM
  ; 200 je defaultni hodnota pro buffer, ale muze se prubezne menit :)




  ; Nastaveni preruseni
	LDI tmp,(1<<PCIE0)
	STS PCICR,tmp	; Tim se aktivuje preruseni na pinech PCINT1~14
   ; Preruseni od PCIE0 -> pin PCINT1
	LDI tmp,(1<<PCINT1)
	STS PCMSK0,tmp	; Tim se nastavi na preruseni pouze pin PCINT1

  ; Nyni zbyva uz jenom zapinat/vypinat preruseni PCINT1. Zapinat se bude
  ; pouze v casech, kdy se ceka na nastupnou/sestupnou hranu.

  ; Nyni je reset/inicializace u konce -> dame o tom vedet
	LDI number,reset_code_1
	RCALL send_number_to_main

	CALL wait_50us_minus_350ns

	LDI number,reset_code_2
	RCALL send_number_to_main

	CALL wait_50us_minus_350ns

	LDI number,reset_code_3
	RCALL send_number_to_main

	CALL wait_50us_minus_350ns

	SEI	; Zapne se globalni preruseni. Do teto doby neni mozne provest
  ; opetovny reset

;	RJMP Start
Start:
  ; number_of_samples - Pocet vzorku
	RCALL load_to_number
	MOV number_of_samples,number	; number_of_samples je registr
  ; proto neni potreba zapisovat do SRAM

  ; trigger_mode
	RCALL load_to_number
	MOV trigger_mode,number

  ; Time_base - casova zakladna
	RCALL load_to_number	; nahrajeme si casovou zakladnu do pameti
  ; vystupni data se ulozi do "number" -> ty pak pouziva load_data_to_SRAM

	RCALL load_data_to_SRAM	; Nahraje potrebna data do SRAM. Rozhoduje
  ; se podle dat ulozenych v "number"

  ; Pro kontrolu se odesila pocet vzorku (pro pripad, ze bychom je napr.
  ; v menu zmenili a pak by doslo k chybe
	MOV number,number_of_samples
	RCALL send_number_to_main

	RCALL send_data_to_main	; Odesle vzorky do main_uC


  ; Resetovaci kody - $FA, $02, $DA (jsou definovany na pocatku)
;	RCALL wait_1ms_minus_350ns	; cas na to, aby se main_uC pripravil
  ; a taky aby byl jasne oddeleny synchronizacni data od dat z A/D
	LDI number,sync_code_1
	RCALL send_number_to_main

	LDI number,sync_code_2
	RCALL send_number_to_main

	LDI number,sync_code_3
	RCALL send_number_to_main


;	RCALL Fill_SRAM	; DEBUG!!!!	; aby v SRAM aspon neco bylo
	RJMP Start



; *-----------------------------------------*
; Fill_SRAM:	; DEBUG!!!!!!
; 	LDI number,0
; 	LDI tmp,8
; 	CLR CNT
; 	LDI XH,HIGH(Samples_begin_SRAM)
; 	LDI XL,LOW(Samples_begin_SRAM)
; fill_2:
; 	ST X+,number
; 	ADD number,tmp
; 	INC cnt
; 	CPI cnt,250
; 	BRNE fill_2
; 	RET
; 
;   ; Hlavne pro DEBUG
 End:
 	nop
 	SBI control_port,LED
	RCALL wait_1ms_minus_350ns
	CBI control_port,LED
	RCALL wait_1ms_minus_350ns
 	RJMP End
; *-----------------------------------------*
; |                                         |
; *-----------------------------------------*
send_data_to_main:
  ; Odesleme "number_of_samples" vzorku do "main_uC"
	SET	; nastavime T bit na "1"

	CLR CNT		; vymazeme pocitadlo vzorku

  ; Nastavime pocatek, od ktereho se budou "tahat" data z SRAM
	LDI XH,HIGH(Samples_begin_SRAM)
	LDI XL,LOW(Samples_begin_SRAM)

  ; A nastavime komunikacni port s "main_uC" na vystupni
	LDI tmp,$FF
	OUT data_port_with_main_IO,tmp

	SBI control_port_IO,data_bit_6
	SBI control_port_IO,data_bit_7


still_send:
	RCALL set_data_port_with_main_to_OUT	; Nastavi se port na vystupni
  ; a postupne se bude rozhodovat, ktery vystup bude v "1" a ktery bude
  ; v "0"

	LD number,X+	; stahneme si hodnotu z SRAM do number
	COM number	; vytvorime jednotkovy doplnek, protoze na vstupu je
  ; invertor -> zase zinvertujeme a dostaneme puvodni hodnotu

  ; a tyto data nahrajeme na vystupy
	SBRC number,0	; pokud bude v "number" na pozici LSB
  ; ulozena "0", pak se nasledujici instrukce preskoci
	SBI data_port_with_main,data_bit_0	; pokud tam byla jednicka, pak
  ; se i vystup "data_bit_0" nastavi do jednicky

	SBRC number,1
	SBI data_port_with_main,data_bit_1	; to same, ale s dalsim bitem

	SBRC number,2
	SBI data_port_with_main,data_bit_2

	SBRC number,3
	SBI data_port_with_main,data_bit_3

	SBRC number,4
	SBI data_port_with_main,data_bit_4

	SBRC number,5
	SBI data_port_with_main,data_bit_5

	SBRC number,6
	SBI control_port,data_bit_6

	SBRC number,7
	SBI control_port,data_bit_7

	RCALL wait_for_main	; pockame, nez bude pripraveny main_uC

	RCALL wait_1us		; to by melo stacit na to, aby si main_uC
  ; stahl data do sve pameti
	MOV tmp,number_of_samples
	INC CNT		; zvysime cislo vzorku o 1
	CP CNT,tmp	; a porovname s hodnotou [number_of_samples]-1
	BRNE still_send	; pokud ne nebude rovnat, pak skok na still_send

  ; Pokud se dostaneme sem, pak bylo jiz "number_of_samples" vzorku poslano
	RCALL set_data_port_with_main_to_IN	; Komunikacni port se nastavi
  ; jako vstupni

	RET

; *-----------------------------------------*
; |                                         |
; *-----------------------------------------*
send_number_to_main:
	SET	; nastaveni T bitu
  ; A nastavime komunikacni port s "main_uC" na vystupni
	RCALL set_data_port_with_main_to_OUT
  ; a postupne se bude rozhodovat, ktery vystup bude v "1" a ktery bude
  ; v "0"
	SBRC number,0	; pokud bude v "number" na pozici LSB
  ; ulozena "0", pak se nasledujici instrukce preskoci
	SBI data_port_with_main,data_bit_0	; pokud tam byla jednicka, pak
  ; se i vystup "data_bit_0" nastavi do jednicky

	SBRC number,1
	SBI data_port_with_main,data_bit_1	; to same, ale s dalsim bitem

	SBRC number,2
	SBI data_port_with_main,data_bit_2

	SBRC number,3
	SBI data_port_with_main,data_bit_3

	SBRC number,4
	SBI data_port_with_main,data_bit_4

	SBRC number,5
	SBI data_port_with_main,data_bit_5

	SBRC number,6
	SBI control_port,data_bit_6

	SBRC number,7
	SBI control_port,data_bit_7


  ; Tak nyni jsou vystupy pripraveny a nastaveny
	RCALL wait_for_main	; pockame, nez bude pripraveny main_uC

	RCALL wait_1us		; to by melo stacit na to, aby si main_uC
  ; stahl data do sve pameti

	RCALL set_data_port_with_main_to_IN

	RET
; *-----------------------------------------*
; |                                         |
; *-----------------------------------------*

wait_for_main:
	LDI tmp,(0<<PCINT1)
	STS PCMSK0,tmp	; Tim se vypne preruseni na pinu PCINT1

	SBI control_port_IO,buffer_ready
	SBI control_port,buffer_ready	; a nastavime priznak pripravenosti
  ; bufferu

still_wait_for_main:
	SBIS control_port_in,main_ready	; kontrola, zda je na main_ready "1"
; ("1" -> preskoci nasledujici instrukci, "0" pokracuje na dalsi instrukci)
	RJMP still_wait_for_main	; pokud na main_ready je "0", znova
  ; skok na kontrolu



  ; Pokud se dostaneme sem, pak je i "main_uC" pripraven
	CBI control_port,buffer_ready	; nastavime priznak "pripraven" do "0"
    ; Preruseni od PCIE0 -> pin PCINT1
	CBI control_port_IO,buffer_ready
	LDI tmp,(1<<PCINT1)
	STS PCMSK0,tmp	; Tim se nastavi na preruseni pouze pin PCINT1


	RET


; *-----------------------------------------*
; |                                         |
; *-----------------------------------------*
  ; Nastavi komunikacni port s main_uc jako vystupni
set_data_port_with_main_to_OUT:
  ; Vystupy komunikujici s "main_uC" nastavime do "0"
	CLR tmp
	OUT data_port_with_main,tmp
	CBI control_port,data_bit_6
	CBI control_port,data_bit_7

	LDI tmp,$FF
	OUT data_port_with_main_IO,tmp
	SBI control_port_IO,data_bit_6
	SBI control_port_IO,data_bit_7
	RET

  ; Nastavi komunikacni port s main_uc jako vstupni
set_data_port_with_main_to_IN:
  ; Vstupy komunikujici s "main_uC" nastavime do "0" (vypnou se pripadne
  ; pull-up rezistory)
	CLR tmp
	OUT data_port_with_main,tmp
	CBI control_port,data_bit_6
	CBI control_port,data_bit_7

  ; Nastaveni portu jako vstupniho
	LDI tmp,$00	; do LDI nahrajeme 0b0000 0000
	OUT data_port_with_main_IO,tmp	; a to pak nahrajeme do data_port
  ; -> data_port_with_main_IO bude vstupni
	CBI control_port_IO,data_bit_6	; plus tyto dva budou take vstupni
	CBI control_port_IO,data_bit_7
	RET

; *-----------------------------------------*
; |                                         |
; *-----------------------------------------*
load_to_number:
	RCALL set_data_port_with_main_to_IN

	RCALL wait_for_main	; spustime podprogram, ktery pocka na main_uC
	SET	; nastavime T bit na "1" - pozdeji se tento bit bude kopirovat
  ; do "number"

	CLR number

	SBIC data_port_with_main_IN,data_bit_0	; pokud na "data_bit_0" je
  ; log. "0" -> nasledujici instrukce se preskoci
	BLD number,0	; pokud byla na vstupu "1" -> log. "1" se zkopiruje
  ; z bitu T do number na nejnizsi vahu (LSB)

	SBIC data_port_with_main_IN,data_bit_1
	BLD number,1	; pripadne na LSB+1
; ...atd
	SBIC data_port_with_main_IN,data_bit_2
	BLD number,2

	SBIC data_port_with_main_IN,data_bit_3
	BLD number,3

	SBIC data_port_with_main_IN,data_bit_4
	BLD number,4

	SBIC data_port_with_main_IN,data_bit_5
	BLD number,5
  ; POZOR! Dalsi bity jsou uz na jinem portu!!!!
	SBIC control_port_in,data_bit_6
	BLD number,6

	SBIC control_port_in,data_bit_7
	BLD number,7

	RET
; *-----------------------------------------*
; |                                         |
; *-----------------------------------------*

wait_for_trigger:
	CPI trigger_mode,0	; zjistime, jaky mod mame vlastne spustit
	BRNE trig_mode_test_1	; pokud nebude "0" v trigger_mode, pak skok
  ; na trig_mode_test_1

  ; Mod "0" -> vzestupna hrana (nejdriv musi byt na trigger "0" a pak "1"
trig_mode_is_0:	; pokud je trigger_mode "0", pak se dostaneme sem
	SBIC control_port_in,trigger_input	; kontrola, zda je na
  ; "trigger_input" 0
	RJMP trig_mode_is_0	; pokud neni na vstupu "0", skok na
  ; trig_mode_is_0
trig_mode_is_0_Now_wait_for_1:
  ; Na vstupu triggeru je tedy "0", musime pockat na "1"
	SBIS control_port_in,trigger_input	; "1" -> preskoci nasledujici
  ; prikaz	; "0" na trigger_input -> pokracuje na dalsi prikaz
	RJMP trig_mode_is_0_Now_wait_for_1

  ; Tak nyni je vse pripraveno
	RET


  ; Mod "1" -> sestupna hrana
trig_mode_test_1:
	CPI trigger_mode,1
	BRNE trig_mode_test_2
  ; tyto dva zakomentovane prikazy jsou zbytecne. Jine mody (zatim) nejsou
trig_mode_is_1:
	SBIS control_port_in,trigger_input
	RJMP trig_mode_is_1
trig_mode_is_1_Now_wait_for_0:
	SBIC control_port_in,trigger_input
	RJMP trig_mode_is_1_Now_wait_for_0

	RET

  ; Mod "2" -> stale vzorkuj a na nic necekej
trig_mode_test_2:
	CPI trigger_mode,2
	BRNE trig_mode_test_3

	RET

trig_mode_test_3:
	nop
  ; pripadne prikazy pro dalsi mod

trig_mode_test_error:
  ; Pokud neni zvolena ani jeden trigger, je neco spatne...
  ; Budto to buffer bude ignorovat a proste "zatriggeruje", nebo 

	LDI tmp,If_error_detected_stop	; Zjistime si nastaveni
  ; (zastavit/ignorovat)
	CPI tmp,0
	BRNE wait_for_trigger_error_stop	; Pokud nebude rovna 0 -> skok

	RET	; Pokud byla rovna nule -> Ignoruje se

wait_for_trigger_error_stop:
;///DEBUG
	SBI control_port,LED	; Pro debug - rozsviti LED
	RCALL wait_500ms_minus_350ns
	CBI control_port,LED
	RCALL wait_100ms_minus_350ns
;////DEBUG	


	RJMP wait_for_trigger_error_stop	; Pokud nebyla rovna nule ->
  ; -> nekonecna smycka

; *-----------------------------------------*
; |                                         |
; *-----------------------------------------*

  ; Musime zjistit, jaka je casova zakladna -> urci se mezery mezi
  ; jednotlivymi vzorky
load_data_to_SRAM:
  ; Nastavíme adresu, od které se má zapisovat do SRAM
	LDI XH,HIGH(Samples_begin_SRAM)
	LDI XL,LOW(Samples_begin_SRAM)

	CLR CNT		; sem se bude ukladat informace o poctu jiz hotovych
  ; vzorku
	RCALL wait_for_trigger	; take lze "hodit" sem. Rozhodovani o tom,
  ; jaka je casova zakladna pri stejne zvolene casove zakladne (napr. 220)
  ; bude pokazde trvat presne stejnou dobu

  ; Predchozi 4 prikazy jsou zde proto, abychom je pak nemuseli u kazde casove
  ; zakladne znovu a znovu definovat, kdyz jsou pokazde stejne
  ; Vysvetleni principu rozhodovani je na TB_211


	CPI number,0	; Nula je dafaultni nastaveni - je to pro pripad, ze
  ; se bude provadet reset, tak aby se buffer "nezasekl" (pokud bude nastaven
  ; debug mod na stop)
	BRNE TB_209	; Pokud neni rovno, pak se testuji dalsi moznosti

	RJMP Time_base_is_216	; V opacnem pripade se skoci sem


TB_209:			; 500ns/dilek -> 50ns/pixel - to odpovida jednomu
; cyklu -> zacina to byt opravdu slozite
	CPI number,209
	BRNE TB_210

	RJMP Time_base_is_209

TB_210:			; 1us/dilek -> 100ns/pixel - uz nutne pariodicke
  ; vzorkovani
	CPI number,210
	BRNE TB_211

	RJMP Time_base_is_210

TB_211:
	CPI number,211	; 2us/dilek -> 200ns/pixel
	BRNE TB_212	; pokud v "number" neni ulozeno 211, pak
  ; se pokracuje na "TB_212"
	RJMP Time_base_is_211	 ;pokud je v "number" ulozeno 211 -> skok na
  ; "Time_base_is_211" . Poznamka: tento program je dost dlouhy a nepotrbuje
  ; spoustet temer zadne zpozdeni. Pro prehlednost je na konci flash pameti.
  ; Zpusob nahrani vzorku do SRAM je popsan ale tam!
TB_212:
	CPI number,212	; 5us/dilek -> 500ns/pixel
	BRNE TB_213
	RJMP Time_base_is_212
TB_213:
	CPI number,213	; 10us
	BRNE TB_214
	RJMP Time_base_is_213
TB_214:
	CPI number,214	; 20us
	BRNE TB_215
	RJMP Time_base_is_214
TB_215:
	CPI number,215	; 50us
	BRNE TB_216
	RJMP Time_base_is_215
TB_216:
	CPI number,216	; 0.1ms
	BRNE TB_217
	RJMP Time_base_is_216
TB_217:
	CPI number,217	; 0.2ms
	BRNE TB_218
	RJMP Time_base_is_217
TB_218:
	CPI number,218	; 0.5ms
	BRNE  TB_219
	RJMP Time_base_is_218
TB_219:
	CPI number,219	; 1ms
	BRNE TB_220
	RJMP Time_base_is_219
TB_220:
	CPI number,220	; 2ms
	BRNE TB_221
	RJMP Time_base_is_220
TB_221:
	CPI number,221	; 5ms
	BRNE TB_222
	RJMP Time_base_is_221
TB_222:
	CPI number,222	; 10ms
	BRNE TB_223
	RJMP Time_base_is_222
TB_223:
	CPI number,223	; 20ms
	BRNE TB_224
	RJMP Time_base_is_223
TB_224:
	CPI number,224	; 50ms
	BRNE TB_225
	RJMP Time_base_is_224
TB_225:
	CPI number,225	; 0.1s
	BRNE TB_226
	RJMP Time_base_is_225
TB_226:
	CPI number,226	; 0.2s
	BRNE TB_227
	RJMP Time_base_is_226
TB_227:
	CPI number,227	; 0.5s
	BRNE TB_228
	RJMP Time_base_is_227
TB_228:
	CPI number,228	; 1s
	BRNE TB_229
	RJMP Time_base_is_228
TB_229:
	CPI number,229	; 2s
	BRNE TB_230
	RJMP Time_base_is_229
TB_230:
  ; 5s
	CPI number,230
	BRNE TB_error
	RJMP Time_base_is_230

TB_error:	; hlavne pro debug -> pokud se neco
  ; stane, potrebujeme abychom to nejak detekovali. Jsou dve moznosti: budto
  ; se chyba bude ignorovat a nastavi se vychozi hodnoty, nebo se program
  ; zacykli a pomuze akorat reset


	LDI tmp,If_error_detected_stop
	CPI tmp,0	; porovnani s nulou
	BRNE TB_error_stop	; Pokud nebude nula -> zacykleni

  ; V opacnem pripade se nastavi defaultni casovka
	RJMP Time_base_is_216

TB_error_stop:
;///DEBUG
	SBI control_port,LED	; Pro debug - rozsviti LED
	RCALL wait_50ms_minus_350ns
	CBI control_port,LED
	RCALL wait_500ms_minus_350ns
	RCALL wait_500ms_minus_350ns
;////DEBUG

	RJMP TB_error_stop

; *-----------------------------------------*

Time_base_is_212:	; 5us/dilek -> 500ns/pixel
	IN tmp,data_port_AD_IN	; 50ns
	ST X+,tmp	; 100ns
	INC CNT		; 50 ns
  ; ted jsme na 200ns
	nop	; 50ns
	nop	; 50ns
	nop	; 50ns
  ; 350ns
	CP CNT,number_of_samples	; 50ns
  ; 400ns
	BRNE Time_base_is_212	; pokud se "CNT" a "number_of_samples" nebudou
  ; rovnat, pak skok na "Time_base_is_212" -> to zabere 100ns -> takze mame
  ; 500ns
	RET

; *-----------------------------------------*

Time_base_is_213:	; 10us -> 1us/pixel
	IN tmp,data_port_AD_IN	; 50ns
	ST X+,tmp	; 100ns
	INC CNT		; 50ns
  ; Zpozdeni
	RCALL wait_1us_minus_350ns
	CP CNT,number_of_samples	; 50ns
	BRNE Time_base_is_213	; pokud skace na "Time_base_is_213" - 100ns
; Prikazy IN,ST,INC,CP a BRNE zabiraji v case dohromady 350ns. Takze zpozdeni
  ; musi byt o 350ns mensi!
	RET

; *-----------------------------------------*

Time_base_is_214:	; 20us -> 2us/pixel
	IN tmp,data_port_AD_IN
	ST X+,tmp
	INC CNT
	RCALL wait_2us_minus_350ns
	CP CNT,number_of_samples
	BRNE Time_base_is_214

	RET

; *-----------------------------------------*

Time_base_is_215:	; 50us -> 5us/pixel
	IN tmp,data_port_AD_IN
	ST X+,tmp
	INC CNT
	RCALL wait_5us_minus_350ns
	CP CNT,number_of_samples
	BRNE Time_base_is_215

	RET

; *-----------------------------------------*

Time_base_is_216:	; 0.1ms -> 10us/px
	IN tmp,data_port_AD_IN
	ST X+,tmp
	INC CNT
	RCALL wait_10us_minus_350ns
	CP CNT,number_of_samples
	BRNE Time_base_is_216

	RET

; *-----------------------------------------*

Time_base_is_217:	; 0.2ms -> 20us/px
	IN tmp,data_port_AD_IN
	ST X+,tmp
	INC CNT
	RCALL wait_20us_minus_350ns
	CP CNT,number_of_samples
	BRNE Time_base_is_217

	RET

; *-----------------------------------------*

Time_base_is_218:	; 0.5ms -> 50us/px
	IN tmp,data_port_AD_IN
	ST X+,tmp
	INC CNT
	RCALL wait_50us_minus_350ns
	CP CNT,number_of_samples
	BRNE Time_base_is_218

	RET

; *-----------------------------------------*

Time_base_is_219:	; 1ms -> 100us/px
	IN tmp,data_port_AD_IN
	ST X+,tmp
	INC CNT
	RCALL wait_100us_minus_350ns
	CP CNT,number_of_samples
	BRNE Time_base_is_219

	RET

; *-----------------------------------------*
Time_base_is_220:	; 2ms -> 200us/px

	IN tmp,data_port_AD_IN
        ST X+,tmp
	INC CNT
	RCALL wait_200us_minus_350ns
	CP CNT,number_of_samples
	BRNE Time_base_is_220
				
	RET

; *-----------------------------------------*
Time_base_is_221:	; 5ms -> 500us/px

	IN tmp,data_port_AD_IN
        ST X+,tmp
	INC CNT
	RCALL wait_500us_minus_350ns
	CP CNT,number_of_samples
	BRNE Time_base_is_221
				
	RET

; *-----------------------------------------*
Time_base_is_222:	; 10ms -> 1ms/px

	IN tmp,data_port_AD_IN
        ST X+,tmp
	INC CNT
	RCALL wait_1ms_minus_350ns
	CP CNT,number_of_samples
	BRNE Time_base_is_222
				
	RET
; *-----------------------------------------*
Time_base_is_223:	; 20ms -> 2ms/px

	IN tmp,data_port_AD_IN
        ST X+,tmp
	INC CNT
	RCALL wait_2ms_minus_350ns
	CP CNT,number_of_samples
	BRNE Time_base_is_223
				
	RET
; *-----------------------------------------*
Time_base_is_224:	; 50ms -> 5ms/px

	IN tmp,data_port_AD_IN
        ST X+,tmp
	INC CNT
	RCALL wait_5ms_minus_350ns
	CP CNT,number_of_samples
	BRNE Time_base_is_224
				
	RET
; *-----------------------------------------*
Time_base_is_225:	; 0.1s -> 10ms/px

	IN tmp,data_port_AD_IN
        ST X+,tmp
	INC CNT
	RCALL wait_10ms_minus_350ns
	CP CNT,number_of_samples
	BRNE Time_base_is_225
				
	RET
; *-----------------------------------------*
Time_base_is_226:	; 0.2s -> 20ms/px

	IN tmp,data_port_AD_IN
        ST X+,tmp
	INC CNT
	RCALL wait_20ms_minus_350ns
	CP CNT,number_of_samples
	BRNE Time_base_is_226
				
	RET
; *-----------------------------------------*
Time_base_is_227:	; 0.5s -> 50ms/px

	IN tmp,data_port_AD_IN
        ST X+,tmp
	INC CNT
	RCALL wait_50ms_minus_350ns
	CP CNT,number_of_samples
	BRNE Time_base_is_227
				
	RET
; *-----------------------------------------*
Time_base_is_228:	; 1s -> 100ms/px

	IN tmp,data_port_AD_IN
        ST X+,tmp
	INC CNT
	RCALL wait_100ms_minus_350ns
	CP CNT,number_of_samples
	BRNE Time_base_is_228
				
	RET
; *-----------------------------------------*
Time_base_is_229:	; 2s -> 200ms/px

	IN tmp,data_port_AD_IN
        ST X+,tmp
	INC CNT
	RCALL wait_200ms_minus_350ns
	CP CNT,number_of_samples
	BRNE Time_base_is_229
				
	RET
; *-----------------------------------------*
Time_base_is_230:	; 5s -> 500ms/px

	IN tmp,data_port_AD_IN
        ST X+,tmp
	INC CNT
	RCALL wait_500ms_minus_350ns
	CP CNT,number_of_samples
	BRNE Time_base_is_230
				
	RET
; *-----------------------------------------*

Time_base_is_211:	;2us/dilek -> 200ns/pixel
  ; V tomto pripade jde o kazdych 50ns (to je jeden takt pri 20Mhz)
  ; Proto nebude tento podprogram vyjimecne zalgoritmovan. Navic ma dany pevne
  ; pocet vzorku.
  ; Skoky zabiraji 2 takty a to uz je moc
	IN tmp,data_port_AD_IN	; nacteme prvni vzorek do registru "tmp"
  ; To trva 50ns pri 20Mhz krystalu
	ST X+,tmp	; a ulozime ho do SRAM na "Samples_begin_SRAM"
  ; To uz trva 100ns !!! (2 takty)
	nop	; 50ns - suma je tedy 200ns

	IN tmp,data_port_AD_IN	; dalsi vzorek
	ST X+,tmp	; a ulozi se do "Samples_begin_SRAM+1" (to plus
  ; znamena ze se adresa X vzdy zvysi o 1
	nop	; plus zpozdeni 50ns
  ; ATD....
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
  ; tak a 200 vzorku je v SRAM :D To byla ale drina
  ; Ted uz jen 55
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop

	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop

	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop

	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop

	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop

	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
	nop
  ; Aaaaa , 255 vzorku. No to je praseci kod

	RET
; *-----------------------------------------*
; |                                         |
; *-----------------------------------------*

.INCLUDE "wait_20Mhz.asm"	; zde jsou ulozeny podprogramy, ktere zarizuji
  ; presne zpozdeni

; *-----------------------------------------*
; |                                         |
; *-----------------------------------------*

Time_base_is_210:	; 1us/dilek, zase pevne dame 200 vzorku
	RCALL wait_for_trigger
	IN tmp,data_port_AD_IN	; trva 50ns -> takze musime i ostatni posunout
  ; o 50ns
	ST X+,tmp
  ; Prvni vzorek mame. Ted si pockame na trigger, az se znovu spusti, pockame
  ; 100ns a pak si zase ulozime dalsi vzorek do pameti
	RCALL wait_for_trigger
	nop	; 50ns	; je to tady za prikaz IN tmp,data_port_AD_IN
	nop	; 50ns
	IN tmp,data_port_AD_IN	; 50ns
	ST X+,tmp
  ; 2. sample	; 2x100ns = 200ns
	RCALL wait_for_trigger
  ; namisto 2x prikazu nop, pouzijeme instrukci, ktera trva 2 takty
	PUSH tmp
	POP tmp
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 3. sample ; 3x100ns = 300ns
	RCALL wait_for_trigger
	PUSH tmp

	POP tmp

	PUSH tmp
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 4. sample - 400ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 5. - 500ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	nop

	POP tmp
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 6. - 600ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	nop

	PUSH tmp

	POP tmp
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 700ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	nop

	PUSH tmp

	POP tmp

	PUSH tmp
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 800ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	RCALL wait_350ns
	POP tmp
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 900ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	RCALL wait_350ns
	PUSH tmp

	POP tmp
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 1us
	RCALL wait_for_trigger
	RCALL wait_350ns
	RCALL wait_350ns
	PUSH tmp

	CLR CNT		; tady je to k nicemu, ale pro nasledujici algoritmus
	LDI number,2	; Aspon usetrime nejake zlomky us :)

	POP tmp
	IN tmp,data_port_AD_IN
	ST X+,tmp

  ; 1.1us - tj. celkem dost casu si to uz nejak zalgoritmovat (22 prikazu)
  ; Takze ted to dame do smycek...
  ; pro zpozdeni 1.1us potrebujeme 22 cyklu, pro 1.2us 24 cyklu, pro 1.3us 26
  ; atd... takze se to da v urcite mire zalgoritmovat.
Time_base_is_210_loop:
	  RCALL wait_for_trigger
	  nop
	  ; 8 cyklu zpozdeni (jen zavolani)
	  RCALL wait_countdown

	  SBRS CNT,0	; rozhodujeme se podle LSB u CNT
  ; 1+2, nebo 3
	  RJMP Jump_there_I
	  ; 2 cykly INC
	  INC number	; number potrebujeme menit jenom jednou za "dve kola"
	  nop
	  nop
	  nop
Jump_back_I:
	  INC CNT
	  ; 1 cykl zapis

	  IN tmp,data_port_AD_IN
	  ST X+,tmp
	  CPI CNT,245	; aby bylo 255 vzorku
	  BRNE Time_base_is_210_loop

	RET

Jump_there_I:
	RJMP Jump_back_I
; *-----------------------------------------*
wait_countdown:	; 350ns + 50 (mov) - tj. 8 taktu
	MOV time1,number
wait_countdown_1:
	nop			; X
	DEC time1		; X
	BRNE wait_countdown_1	; 2*(X-1)+1
  ; vysledny vzorec: 2X+2(X-1)+1
  ; zkratka - pokud zvysime cislo number o 1, pak se zpozdeni zvysi o 4 cykly
	RET


; *-----------------------------------------*
; |               MACROS                    |
; *-----------------------------------------*
.MACRO w50ns
	nop
.ENDMACRO

.MACRO w100ns
	LDS tmp,$0101
.ENDMACRO

.MACRO w200ns 	
	LDS tmp,$0101
	LDS tmp,$0101
.ENDMACRO
; *-----------------------------------------*
; |                                         |
; *-----------------------------------------*

Time_base_is_209:
  ; 1.vzorek - 0ns zpozdeni
	RCALL wait_for_trigger
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 2. - 50ns
	RCALL wait_for_trigger
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 3 - 100ns
	RCALL wait_for_trigger
  ; namisto 2x prikazu nop, pouzijeme instrukci, ktera trva 2 takty
;	nop
;	nop
	w100ns
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 4 - 150ns
	RCALL wait_for_trigger
	w100ns
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 5 - 200ns
	RCALL wait_for_trigger
	w200ns
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 6 - 250ns
	RCALL wait_for_trigger
	w200ns
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 7 - 300ns
	RCALL wait_for_trigger
	w200ns
	w100ns
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 8 - 350ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 9 - 400ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	nop
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 10 - 450ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	w100ns
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 11 - 500ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	nop
	w100ns
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 12 - 550ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	w200ns
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 13 - 600ns
	RCALL wait_for_trigger
	RCALL wait_350ns
    ; Pro vetsi prehlednost jsem pouzil makra, tzn. ze dany kod se prida na
    ; dana mista, namisto toho, aby se provadely skoky, ktere jsou casove
    ; narocne
	w50ns
	w200ns
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 14 - 650ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	w200ns
	w100ns
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 15 - 700ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	RCALL wait_350ns
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 16 - 750ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	RCALL wait_350ns
	w50ns
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 17 - 800ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	RCALl wait_350ns
	w100ns
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 18 - 850ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	RCALL wait_350ns
	w100ns
	w50ns
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 19 - 900ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	RCALL wait_350ns
	w200ns
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 20 - 950ns
	RCALL wait_for_trigger
	RCALL wait_350ns
	RCALL wait_350ns
	w200ns
	w50ns
	IN tmp,data_port_AD_IN
	ST X+,tmp

  ; 21 - 1000ns = 1us
	RCALL wait_for_trigger
	RCALL wait_1us
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 22 - 1050ns
	RCALL wait_for_trigger
	RCALL wait_1us
	w50ns
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 23 - 1100ns
	RCALL wait_for_trigger
	RCALL wait_1us
	w100ns
	IN tmp,data_port_AD_IN
	ST X+,tmp
  ; 24 - 1150ns
	RCALL wait_for_trigger
	RCALL wait_1us
	w100ns
	w50ns
	IN tmp,data_port_AD_IN
	ST X+,tmp




 ; 25 1200ns - 24cyklu -  to uz snad pujde nejak zalgoritmovat
	CLR CNT
	LDI number,1

Time_base_is_209_loop:
	RCALL wait_for_trigger
	RCALL wait_countdown	; 8 taktu plus zpozdeni
  ; number=1 -> 3 takty
	SBRS CNT,1
	RJMP Time_base_is_209_CNT_1
	w200ns
Jump_back_II:
	SBRS CNT,0
	RJMP Time_base_is_209_CNT_0

	w200ns	; 4 takty -> RJMP a RJMP
  ; toto zpozdeni se provede jen tehdy, kdyz bude CNT,1 a CNT,0 v nule ->
  ; -> musi se dohnat zpozdeni, ktere maji prikazy RJMP
Jump_back_III:
	INC CNT			; 1
	IN tmp,data_port_AD_IN	; 1
	ST X+,tmp
	SBRS CNT,0	; pokud je CNT,0 a CNT,1 v "1", tak number zvysime o 1
	RJMP Time_base_is_209_loop_no_change
	SBRC CNT,1
	INC number	; takze jednou za 4 doby zvysime number o "1"

Time_base_is_209_loop_no_change:
	CPI CNT,231
	BRNE Time_base_is_209_loop

	RET

Time_base_is_209_CNT_1:
;	nop
	nop
	RJMP Jump_back_II

Time_base_is_209_CNT_0:
;	nop
	RJMP Jump_back_III