fir3 Project Status (05/20/2011 - 02:44:42)
Project File: | fir3.ise | Implementation State: | Translated
Module Name: | fir3 | Errors: | No Errors
Target Device: | xc3s50an-4tqg144 | Warnings: | 333 Warnings
Product Version: | ISE 11.1 | Routing Results: |
Design Goal: | Balanced | Timing Constraints: |
Design Strategy: | Xilinx Default (unlocked) | Final Timing Score: |

Device Utilization Summary (estimated values) | [-]
Logic Utilization | Used | Available | Utilization
Number of Slices | 755 | 704 | 107%
Number of Slice Flip Flops | 262 | 1408 | 18%
Number of 4 input LUTs | 1375 | 1408 | 97%
Number of bonded IOBs | 17 | 108 | 15%
Number of MULT18X18SIOs | 3 | 3 | 100%
Number of GCLKs | 1 | 24 | 4%

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Fri 20. May 02:44:35 2011 | 0 | 333 Warnings | 19 Infos
Translation Report | Current | Fri 20. May 02:44:41 2011 | 0 | 0 | 0
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated

Date Generated: 05/20/2011 - 09:40:11