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-- Company: 
-- Engineer:
--
-- Create Date:   00:58:10 05/15/2013
-- Design Name:   
-- Module Name:   C:/School/bb2m/vhdl/cube_controller/disp2_test.vhd
-- Project Name:  cube_controller
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: display2
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;

use work.MEMORY.all;
 
ENTITY disp2_test IS
END disp2_test;
 
ARCHITECTURE behavior OF disp2_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT display2
    PORT(
         clk : IN  std_logic;
         animation: in unsigned (1 downto 0);
         srclk0 : OUT  std_logic;
         srclk1 : OUT  std_logic;
         srclk2 : OUT  std_logic;
         rclk0 : OUT  std_logic;
         rclk1 : OUT  std_logic;
         rclk2 : OUT  std_logic;
         clk_out0 : OUT  std_logic;
         clk_out1 : OUT  std_logic;
         clk_out2 : OUT  std_logic;
         ser_row0 : OUT  std_logic;
         ser_row1 : OUT  std_logic;
         ser_row2 : OUT  std_logic;
         ser_row3 : OUT  std_logic;
         ser_row4 : OUT  std_logic;
         ser_row5 : OUT  std_logic;
         ser_row6 : OUT  std_logic;
         ser_row7 : OUT  std_logic;
         srclk_level : OUT  std_logic;
         rclk_level : OUT  std_logic;
         ser_level : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal animation: unsigned (1 downto 0) := (others => '0');

 	--Outputs
   signal srclk0 : std_logic;
   signal srclk1 : std_logic;
   signal srclk2 : std_logic;
   signal rclk0 : std_logic;
   signal rclk1 : std_logic;
   signal rclk2 : std_logic;
   signal clk_out0 : std_logic;
   signal clk_out1 : std_logic;
   signal clk_out2 : std_logic;
   signal ser_row0 : std_logic;
   signal ser_row1 : std_logic;
   signal ser_row2 : std_logic;
   signal ser_row3 : std_logic;
   signal ser_row4 : std_logic;
   signal ser_row5 : std_logic;
   signal ser_row6 : std_logic;
   signal ser_row7 : std_logic;
   signal srclk_level : std_logic;
   signal rclk_level : std_logic;
   signal ser_level : std_logic;

   -- Clock period definitions
   constant clk_period : time := 20 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: display2 PORT MAP (
          clk => clk,
          animation => animation,
          srclk0 => srclk0,
          srclk1 => srclk1,
          srclk2 => srclk2,
          rclk0 => rclk0,
          rclk1 => rclk1,
          rclk2 => rclk2,
          clk_out0 => clk_out0,
          clk_out1 => clk_out1,
          clk_out2 => clk_out2,
          ser_row0 => ser_row0,
          ser_row1 => ser_row1,
          ser_row2 => ser_row2,
          ser_row3 => ser_row3,
          ser_row4 => ser_row4,
          ser_row5 => ser_row5,
          ser_row6 => ser_row6,
          ser_row7 => ser_row7,
          srclk_level => srclk_level,
          rclk_level => rclk_level,
          ser_level => ser_level
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 1 ns;	

      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;
