main Project Status (06/05/2013 - 18:01:45)
Project File: | cube_controller.xise | Parser Errors: | No Errors
Module Name: | main | Implementation State: | Programming File Generated
Target Device: | xc3s200-4ft256 | Errors: | No Errors
Product Version: | ISE 14.3 | Warnings: | 54 Warnings (24 new)
Design Goal: | Balanced | Routing Results: | All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: | All Constraints Met
Environment: | System Settings | Final Timing Score: | 0 (Timing Report)

Device Utilization Summary | [-]
Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Flip Flops | 325 | 3,840 | 8% |
Number of 4 input LUTs | 2,289 | 3,840 | 59% |
Number of occupied Slices | 1,309 | 1,920 | 68% |
Number of Slices containing only related logic | 1,309 | 1,309 | 100% |
Number of Slices containing unrelated logic | 0 | 1,309 | 0% |
Total Number of 4 input LUTs | 2,508 | 3,840 | 65% |
Number used as logic | 2,006 |  |  |
Number used as a route-thru | 219 |  |  |
Number used for Dual Port RAMs | 256 |  |  |
Number used as Shift registers | 27 |  |  |
Number of bonded IOBs | 28 | 173 | 16% |
Number of BUFGMUXs | 1 | 8 | 12% |
Average Fanout of Non-Clock Nets | 4.51 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | st 5. VI 18:00:03 2013 | 0 | 49 Warnings (24 new) | 3 Infos (0 new)
Translation Report | Current | st 5. VI 18:00:20 2013 | 0 | 0 | 0
Map Report | Current | st 5. VI 18:00:34 2013 | 0 | 5 Warnings (0 new) | 4 Infos (0 new)
Place and Route Report | Current | st 5. VI 18:01:20 2013 | 0 | 0 | 2 Infos (0 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | st 5. VI 18:01:27 2013 | 0 | 0 | 6 Infos (0 new)
Bitgen Report | Current | st 5. VI 18:01:41 2013 | 0 | 0 | 1 Info (0 new)

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Out of Date | po 20. V 01:54:59 2013
WebTalk Report | Current | st 5. VI 18:01:43 2013
WebTalk Log File | Current | st 5. VI 18:01:45 2013

Date Generated: 06/05/2013 - 18:01:45