System Settings

Environment Settings
Environment Variable | xst | ngdbuild | map | par
PATHEXT | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH
Path | C:\Xilinx\14.3\ISE_DS\ISE\\lib\nt; C:\Xilinx\14.3\ISE_DS\ISE\\bin\nt; C:\Xilinx\Vivado_HLS\2012.3\bin; C:\Xilinx\14.3\ISE_DS\ISE\bin\nt; C:\Xilinx\14.3\ISE_DS\ISE\lib\nt; C:\Xilinx\14.3\ISE_DS\ISE\..\..\..\DocNav; C:\Xilinx\Vivado\2012.3\bin; C:\Xilinx\14.3\ISE_DS\PlanAhead\bin; C:\Xilinx\14.3\ISE_DS\EDK\bin\nt; C:\Xilinx\14.3\ISE_DS\EDK\lib\nt; C:\Xilinx\14.3\ISE_DS\EDK\gnu\microblaze\nt\bin; C:\Xilinx\14.3\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin; C:\Xilinx\14.3\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\14.3\ISE_DS\EDK\gnu\arm\nt\bin; C:\Xilinx\14.3\ISE_DS\common\bin\nt; C:\Xilinx\14.3\ISE_DS\common\lib\nt; C:\Program Files\Parallels\Parallels Tools\Applications; C:\Program Files\Borland\Delphi7\Bin; C:\Program Files\Borland\Delphi7\Projects\Bpl\; C:\WINDOWS\system32; C:\WINDOWS; C:\WINDOWS\System32\Wbem; C:\Program Files\Microsoft SQL Server\90\Tools\binn\; C:\OrCAD\OrCAD_16.5_Lite\tools\PSpice; C:\OrCAD\OrCAD_16.5_Lite\tools\PSpice\Library; C:\OrCAD\OrCAD_16.5_Lite\tools\Capture; C:\OrCAD\OrCAD_16.5_Lite\tools\bin; C:\OrCAD\OrCAD_16.5_Lite\OpenAccess\bin\win32\opt; C:\OrCAD\OrCAD_16.5_Lite\tools\fet\bin; C:\OrCAD\OrCAD_16.5_Lite\tools\pcb\bin; C:\Program Files\MATLAB\R2010a\runtime\win32; C:\Program Files\MATLAB\R2010a\bin; C:\Program Files\Microchip\MPLAB C30\bin | C:\Xilinx\14.3\ISE_DS\ISE\\lib\nt; C:\Xilinx\14.3\ISE_DS\ISE\\bin\nt; C:\Xilinx\Vivado_HLS\2012.3\bin; C:\Xilinx\14.3\ISE_DS\ISE\bin\nt; C:\Xilinx\14.3\ISE_DS\ISE\lib\nt; C:\Xilinx\14.3\ISE_DS\ISE\..\..\..\DocNav; C:\Xilinx\Vivado\2012.3\bin; C:\Xilinx\14.3\ISE_DS\PlanAhead\bin; C:\Xilinx\14.3\ISE_DS\EDK\bin\nt; C:\Xilinx\14.3\ISE_DS\EDK\lib\nt; C:\Xilinx\14.3\ISE_DS\EDK\gnu\microblaze\nt\bin; C:\Xilinx\14.3\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin; C:\Xilinx\14.3\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\14.3\ISE_DS\EDK\gnu\arm\nt\bin; C:\Xilinx\14.3\ISE_DS\common\bin\nt; C:\Xilinx\14.3\ISE_DS\common\lib\nt; C:\Program Files\Parallels\Parallels Tools\Applications; C:\Program Files\Borland\Delphi7\Bin; C:\Program Files\Borland\Delphi7\Projects\Bpl\; C:\WINDOWS\system32; C:\WINDOWS; C:\WINDOWS\System32\Wbem; C:\Program Files\Microsoft SQL Server\90\Tools\binn\; C:\OrCAD\OrCAD_16.5_Lite\tools\PSpice; C:\OrCAD\OrCAD_16.5_Lite\tools\PSpice\Library; C:\OrCAD\OrCAD_16.5_Lite\tools\Capture; C:\OrCAD\OrCAD_16.5_Lite\tools\bin; C:\OrCAD\OrCAD_16.5_Lite\OpenAccess\bin\win32\opt; C:\OrCAD\OrCAD_16.5_Lite\tools\fet\bin; C:\OrCAD\OrCAD_16.5_Lite\tools\pcb\bin; C:\Program Files\MATLAB\R2010a\runtime\win32; C:\Program Files\MATLAB\R2010a\bin; C:\Program Files\Microchip\MPLAB C30\bin | C:\Xilinx\14.3\ISE_DS\ISE\\lib\nt; C:\Xilinx\14.3\ISE_DS\ISE\\bin\nt; C:\Xilinx\Vivado_HLS\2012.3\bin; C:\Xilinx\14.3\ISE_DS\ISE\bin\nt; C:\Xilinx\14.3\ISE_DS\ISE\lib\nt; C:\Xilinx\14.3\ISE_DS\ISE\..\..\..\DocNav; C:\Xilinx\Vivado\2012.3\bin; C:\Xilinx\14.3\ISE_DS\PlanAhead\bin; C:\Xilinx\14.3\ISE_DS\EDK\bin\nt; C:\Xilinx\14.3\ISE_DS\EDK\lib\nt; C:\Xilinx\14.3\ISE_DS\EDK\gnu\microblaze\nt\bin; C:\Xilinx\14.3\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin; C:\Xilinx\14.3\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\14.3\ISE_DS\EDK\gnu\arm\nt\bin; C:\Xilinx\14.3\ISE_DS\common\bin\nt; C:\Xilinx\14.3\ISE_DS\common\lib\nt; C:\Program Files\Parallels\Parallels Tools\Applications; C:\Program Files\Borland\Delphi7\Bin; C:\Program Files\Borland\Delphi7\Projects\Bpl\; C:\WINDOWS\system32; C:\WINDOWS; C:\WINDOWS\System32\Wbem; C:\Program Files\Microsoft SQL Server\90\Tools\binn\; C:\OrCAD\OrCAD_16.5_Lite\tools\PSpice; C:\OrCAD\OrCAD_16.5_Lite\tools\PSpice\Library; C:\OrCAD\OrCAD_16.5_Lite\tools\Capture; C:\OrCAD\OrCAD_16.5_Lite\tools\bin; C:\OrCAD\OrCAD_16.5_Lite\OpenAccess\bin\win32\opt; C:\OrCAD\OrCAD_16.5_Lite\tools\fet\bin; C:\OrCAD\OrCAD_16.5_Lite\tools\pcb\bin; C:\Program Files\MATLAB\R2010a\runtime\win32; C:\Program Files\MATLAB\R2010a\bin; C:\Program Files\Microchip\MPLAB C30\bin | C:\Xilinx\14.3\ISE_DS\ISE\\lib\nt; C:\Xilinx\14.3\ISE_DS\ISE\\bin\nt; C:\Xilinx\Vivado_HLS\2012.3\bin; C:\Xilinx\14.3\ISE_DS\ISE\bin\nt; C:\Xilinx\14.3\ISE_DS\ISE\lib\nt; C:\Xilinx\14.3\ISE_DS\ISE\..\..\..\DocNav; C:\Xilinx\Vivado\2012.3\bin; C:\Xilinx\14.3\ISE_DS\PlanAhead\bin; C:\Xilinx\14.3\ISE_DS\EDK\bin\nt; C:\Xilinx\14.3\ISE_DS\EDK\lib\nt; C:\Xilinx\14.3\ISE_DS\EDK\gnu\microblaze\nt\bin; C:\Xilinx\14.3\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin; C:\Xilinx\14.3\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\14.3\ISE_DS\EDK\gnu\arm\nt\bin; C:\Xilinx\14.3\ISE_DS\common\bin\nt; C:\Xilinx\14.3\ISE_DS\common\lib\nt; C:\Program Files\Parallels\Parallels Tools\Applications; C:\Program Files\Borland\Delphi7\Bin; C:\Program Files\Borland\Delphi7\Projects\Bpl\; C:\WINDOWS\system32; C:\WINDOWS; C:\WINDOWS\System32\Wbem; C:\Program Files\Microsoft SQL Server\90\Tools\binn\; C:\OrCAD\OrCAD_16.5_Lite\tools\PSpice; C:\OrCAD\OrCAD_16.5_Lite\tools\PSpice\Library; C:\OrCAD\OrCAD_16.5_Lite\tools\Capture; C:\OrCAD\OrCAD_16.5_Lite\tools\bin; C:\OrCAD\OrCAD_16.5_Lite\OpenAccess\bin\win32\opt; C:\OrCAD\OrCAD_16.5_Lite\tools\fet\bin; C:\OrCAD\OrCAD_16.5_Lite\tools\pcb\bin; C:\Program Files\MATLAB\R2010a\runtime\win32; C:\Program Files\MATLAB\R2010a\bin; C:\Program Files\Microchip\MPLAB C30\bin
XILINX | C:\Xilinx\14.3\ISE_DS\ISE\ | C:\Xilinx\14.3\ISE_DS\ISE\ | C:\Xilinx\14.3\ISE_DS\ISE\ | C:\Xilinx\14.3\ISE_DS\ISE\
XILINX_DSP | C:\Xilinx\14.3\ISE_DS\ISE | C:\Xilinx\14.3\ISE_DS\ISE | C:\Xilinx\14.3\ISE_DS\ISE | C:\Xilinx\14.3\ISE_DS\ISE
XILINX_EDK | C:\Xilinx\14.3\ISE_DS\EDK | C:\Xilinx\14.3\ISE_DS\EDK | C:\Xilinx\14.3\ISE_DS\EDK | C:\Xilinx\14.3\ISE_DS\EDK
XILINX_PLANAHEAD | C:\Xilinx\14.3\ISE_DS\PlanAhead | C:\Xilinx\14.3\ISE_DS\PlanAhead | C:\Xilinx\14.3\ISE_DS\PlanAhead | C:\Xilinx\14.3\ISE_DS\PlanAhead
XILINX_VIVADO | C:\Xilinx\Vivado\2012.3 | C:\Xilinx\Vivado\2012.3 | C:\Xilinx\Vivado\2012.3 | C:\Xilinx\Vivado\2012.3

Synthesis Property Settings
Switch Name | Property Name | Value | Default Value
-ifn |  | main.prj |
-ifmt |  | mixed | MIXED
-ofn |  | main |
-ofmt |  | NGC | NGC
-p |  | xc3s200-4-ft256 |
-top |  | main |
-opt_mode | Optimization Goal | Speed | SPEED
-opt_level | Optimization Effort | 1 | 1
-iuc | Use synthesis Constraints File | NO | NO
-keep_hierarchy | Keep Hierarchy | No | NO
-netlist_hierarchy | Netlist Hierarchy | As_Optimized | as_optimized
-rtlview | Generate RTL Schematic | Yes | NO
-glob_opt | Global Optimization Goal | AllClockNets | ALLCLOCKNETS
-read_cores | Read Cores | YES | YES
-write_timing_constraints | Write Timing Constraints | NO | NO
-cross_clock_analysis | Cross Clock Analysis | NO | NO
-bus_delimiter | Bus Delimiter | <> | <>
-slice_utilization_ratio | Slice Utilization Ratio | 100 | 100%
-bram_utilization_ratio | BRAM Utilization Ratio | 100 | 100%
-verilog2001 | Verilog 2001 | YES | YES
-fsm_extract |  | YES | YES
-fsm_encoding |  | Auto | AUTO
-safe_implementation |  | No | NO
-fsm_style |  | LUT | LUT
-ram_extract |  | Yes | YES
-ram_style |  | Auto | AUTO
-rom_extract |  | Yes | YES
-shreg_extract |  | YES | YES
-rom_style |  | Auto | AUTO
-auto_bram_packing |  | NO | NO
-resource_sharing |  | YES | YES
-async_to_sync |  | NO | NO
-mult_style |  | Auto | AUTO
-iobuf |  | YES | YES
-max_fanout |  | 100000 | 500
-bufg |  | 8 | 8
-register_duplication |  | YES | YES
-register_balancing |  | No | NO
-optimize_primitives |  | NO | NO
-use_clock_enable |  | Yes | YES
-use_sync_set |  | Yes | YES
-use_sync_reset |  | Yes | YES
-iob |  | Auto | AUTO
-equivalent_register_removal |  | YES | YES
-slice_utilization_ratio_maxmargin |  | 5 | 0%

Translation Property Settings
Switch Name | Property Name | Value | Default Value
-intstyle |  | ise | None
-dd |  | _ngo | None
-p |  | xc3s200-ft256-4 | None
-uc |  | main.ucf | None

Map Property Settings
Switch Name | Property Name | Value | Default Value
-ir | Use RLOC Constraints | OFF | OFF
-cm | Optimization Strategy (Cover Mode) | area | area
-intstyle |  | ise | None
-o |  | main_map.ncd | None
-pr | Pack I/O Registers/Latches into IOBs | off | off
-p |  | xc3s200-ft256-4 | None

Place and Route Property Settings
Switch Name | Property Name | Value | Default Value
-t |  | 1 | 1
-intstyle |  | ise |
-ol | Place & Route Effort Level (Overall) | high | std
-w |  | true | false

Operating System Information
Operating System Information | xst | ngdbuild | map | par
CPU Architecture/Speed | Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz/2389 MHz | Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz/2389 MHz | Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz/2389 MHz | Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz/2389 MHz
Host | mimo0abe | mimo0abe | mimo0abe | mimo0abe
OS Name | Microsoft Windows XP Professional | Microsoft Windows XP Professional | Microsoft Windows XP Professional | Microsoft Windows XP Professional
OS Release | Service Pack 2 (build 2600) | Service Pack 2 (build 2600) | Service Pack 2 (build 2600) | Service Pack 2 (build 2600)