/*
 * ENC424J600_SPI_Instructions.h
 *
 *  Created on: Nov 14, 2011
 *      Author: RomanM
 */

#ifndef ENC424J600_SPI_INSTRUCTIONS_H_
#define ENC424J600_SPI_INSTRUCTIONS_H_

/*******************************************************************************
 * ENC424J600 SPI Instruction Set
 ******************************************************************************/

#define	B0SEL		0xc0	// Bank 0 Select
#define	B1SEL		0xc2	// Bank 1 Select
#define	B2SEL		0xc4	// Bank 2 Select
#define	B3SEL		0xc6	// Bank 3 Select
#define	SETETHRST	0xca	// System Reset
#define	FCDISABLE	0xe0	// Flow Control Disable
#define	FCSINGLE	0xe2	// Flow Control Single
#define	FCMULTIPLE	0xe4	// Flow Control Multiple
#define	FCCLEAR		0xe6	// Flow Control Clear
#define SETPKTDEC	0xcc	// Decrement Packet Counter
#define	DMASTOP		0xd2	// DMA Stop
#define	DMACKSUM	0xd8	// DMA Start Checksum
#define	DMACKSUMS	0xda	// DMA Start Checksum with Seed
#define	DMACOPY		0xdc	// DMA Start Copy
#define	DMACOPYS	0xde	// DMA Start Copy and Checksum with Seed
#define	SETTXRTS	0xd4	// Request Packet Transmission
#define	ENABLERX	0xe8	// Enable RX
#define	DISABLERX	0xea	// Disable RX
#define	SETEIE		0xec	// Enable Interrupts
#define	CLREIE		0xee	// Disable Interrupts
#define	RBSEL		0xc8	// Read Bank Select
#define	WGPRDPT		0x60	// Write EGPRDPT
#define	RGPRDPT		0x62	// Read EGPRDPT
#define	WRXRDPT		0x64	// Write ERXRDPT
#define	RRXRDPT		0x66	// Read ERXRDPT
#define	WUDARDPT	0x68	// Write EUDARDPT
#define	RUDARDPT	0x6a	// Read EUDARDPT
#define	WGPWRPT		0x6c	// Write EGPWRPT
#define	RGPWRPT		0x6e	// Read EGPWRPT
#define	WRXWRPT		0x70	// Write ERXWRPT
#define	RRXWRPT		0x72	// Read ERXWRPT
#define	WUDAWRPT	0x74	// Write EUDAWRPT
#define	RUDAWRPT	0x76	// Read EUDAWRPT
#define	RCR			0x00	// Read Control Register
#define	WCR			0x40	// Write Control Register
#define	RCRU		0x20	// Read Control Register Unbanked
#define	WCRU		0x22	// Write Control Register Unbanked
#define	BFS			0x80	// Bit Field Set
#define	BFC			0xa0	// Bit Field Clear
#define	BFSU		0x24	// Bit Field Set Unbanked
#define	BFCU		0x26	// Bit Field Clear Unbanked
#define	RGPDATA		0x28	// Read EGPDATA
#define	WGPDATA		0x2a	// Write EGPDATA
#define	RRXDATA		0x2c	// Read ERXDATA
#define	WRXDATA		0x2e	// Write ERXDATA
#define	RUDADATA	0x30	// Read EUDADATA
#define	WUDADATA	0x32	// Write EUDADATA

#endif /* ENC424J600_SPI_INSTRUCTIONS_H_ */
