/*
 * MFRC530_Registers.h
 *
 *  Created on: Nov 11, 2011
 *      Author: RomanM
 */

#ifndef MFRC530_REGISTERS_H_
#define MFRC530_REGISTERS_H_

#define MFRC530_RegPage(address)		(0x80 | ((address) >> 3))

// Page 0: Command and status
#define	Page				0x00
#define	Command				0x01
#define	FIFOData			0x02
#define	PrimaryStatus		0x03
#define	FIFOLength			0x04
#define	SecondaryStatus		0x05
#define	InterruptEn			0x06
#define	InterruptRq			0x07

// Page 1: Control and status
#define	Control				0x09
#define	ErrorFlag			0x0A
#define	CollPos				0x0B
#define	TimerValue			0x0C
#define	CRCResultLSB		0x0D
#define	CRCResultMSB		0x0E
#define	BitFraming			0x0F

// Page 2: Transmitter and coder control
#define	TxControl			0x11
#define	CwConductance		0x12
#define	CoderControl		0x14
#define	ModWidth			0x15

// Page 3: Receiver and decoder control
#define	RxControl1			0x19
#define	DecoderControl		0x1A
#define	BitPhase			0x1B
#define	RxThreshold			0x1C
#define	BPSKDemControl		0x1D
#define	RxControl2			0x1E
#define	ClockQControl		0x1F

// Page 4: RF Timing and channel redundancy
#define	RxWait				0x21
#define	ChannelRedundancy	0x22
#define	CRCPresetLSB		0x23
#define	CRCPresetMSB		0x24
#define	MfOutSelect			0x26

// Page 5: FIFO, timer and IRQ pin configuration
#define	FIFOLevel			0x29
#define	TimerClock			0x2A
#define	TimerControl		0x2B
#define	TimerReload			0x2C
#define	IRqPinConfig		0x2D

// Page 7: Test control
#define	TestAnaSelect		0x3A
#define	TestDigiSelect		0x3D

/*
 * Register bits
 */

// Page register
#define	UsePageSelect					(1<<7)

// Command register
#define	IFDetectBusy					(1<<7)

// PrimaryStatus register
#define	ModemState						0x70
#define	ModemState_Idle					0x00
#define	ModemState_TxSOF				0x10
#define	ModemState_TxData				0x20
#define	ModemState_TxEOF				0x30
#define	ModemState_GoToRx				0x40
#define	ModemState_PrepareRx			0x50
#define	ModemState_AwaitingRx			0x60
#define	ModemState_Receiving			0x70
#define	IRq								(1<<3)
#define	Err								(1<<2)
#define	HiAlert							(1<<1)
#define	LoAlert							(1<<0)

// SecondaryStatus register
#define	TRunning						(1<<7)
#define	E2Ready							(1<<6)
#define	CRCReady						(1<<5)
#define	RxLastBits						0x70

// InterruptEn register
#define	SetIEn							(1<<7)
#define	TimerIEn						(1<<5)
#define	TxIEn							(1<<4)
#define	RxIEn							(1<<3)
#define	IdleIEn							(1<<2)
#define	HiAlertIEn						(1<<1)
#define	LoAlertIEn						(1<<0)

// InterruptRq register
#define	SetIRq							(1<<7)
#define	TimerIRq						(1<<5)
#define	TxIRq							(1<<4)
#define	RxIRq							(1<<3)
#define	IdleIRq							(1<<2)
#define	HiAlertIRq						(1<<1)
#define	LoAlertIRq						(1<<0)

// Control register
#define	StandBy							(1<<5)
#define	PowerDown						(1<<4)
#define	Crypto1On						(1<<3)
#define	TStopNow						(1<<2)
#define	TStartNow						(1<<1)
#define	FlushFIFO						(1<<0)

// ErrorFlag register
#define	KeyErr							(1<<6)
#define	AccessErr						(1<<5)
#define	FIFOOvfl						(1<<4)
#define	CRCErr							(1<<3)
#define	FramingErr						(1<<2)
#define	ParityErr						(1<<1)
#define	CollErr							(1<<0)

// TxControl register
#define	ModulatorSource					0x60
#define	ModulatorSource_LOW				0x00
#define	ModulatorSource_HIGH			0x20
#define	ModulatorSource_Internal		0x40
#define	ModulatorSource_MFIN			0x60
#define	TX2Inv							(1<<3)
#define	TX2Cw							(1<<2)
#define	TX2RFEn							(1<<1)
#define	TX1RFEn							(1<<0)

// RxControl1 register
#define	SubCPulses						0xE0
#define	SubCPulses_1					0x00
#define	SubCPulses_2					0x20
#define	SubCPulses_4					0x40
#define	SubCPulses_8					0x60
#define	SubCPulses_16					0x80
#define	LPOff							(1<<2)
#define	Gain							0x03
#define	Gain_20dB						0x00
#define	Gain_24dB						0x01
#define	Gain_31dB						0x02
#define	Gain_35dB						0x03

// DecoderControl register
#define	RxMultiple						(1<<6)
#define	ZeroAfterColl					(1<<5)
#define	RxCoding						(1<<0)

// RxControl2 ragister
#define	RcvClkSelI						(1<<7)
#define	RxAutoPD						(1<<6)
#define	DecoderSource_LOW				0x00
#define	DecoderSource_Internal			0x01
#define DecoderSource_SubMFIN			0x02
#define	DecoderSource_BaseMFIN			0x03

// ClockQControl register
#define	ClkQ180Deg						(1<<7)
#define	ClkQCalib						(1<<6)

// ChannelRedundancy register
#define	CRC3309							(1<<5)
#define	CRC8							(1<<4)
#define	RxCRCEn							(1<<3)
#define	TxCRCEn							(1<<2)
#define	ParityOdd						(1<<1)
#define	ParityEn						(1<<0)

// TimerClock register
#define	TAutoRestart					(1<<5)

// TimerControl register
#define TStopRxEnd						(1<<3)
#define	TStopRxBegin					(1<<2)
#define	TStartTxEnd						(1<<1)
#define	TStartTxBegin					(1<<0)

// IRQPinConfig
#define	IRQInv							(1<<1)
#define IRQPushPull						(1<<0)

#endif /* MFRC530_REGISTERS_H_ */
