/*
 * ENC424J600_Registers.h
 *
 *  Created on: Nov 14, 2011
 *      Author: RomanM
 */

#ifndef ENC424J600_REGISTERS_H_
#define ENC424J600_REGISTERS_H_

/*******************************************************************************
 * ENC424J600 Registers
 ******************************************************************************/

// SPI Bank 0 registers
#define	ETXST		0x00
#define	ETXSTL		0x00
#define	ETXSTH		0x01

#define	ETXLEN		0x02
#define	ETXLENL		0x02
#define	ETXLENH		0x03

#define	ERXST		0x04
#define	ERXSTL		0x04
#define	ERXSTH		0x05

#define	ERXTAIL		0x06
#define	ERXTAILL	0x06
#define	ERXTAILH	0x07

#define	ERXHEAD		0x08
#define	ERXHEADL	0x08
#define	ERXHEADH	0x09

#define	EDMAST		0x0a
#define	EDMASTL		0x0a
#define	EDMASTH		0x0b

#define	EDMALEN		0x0c
#define	EDMALENL	0x0c
#define	EDMALENH	0x0d

#define	EDMADST		0x0e
#define	EDMADSTL	0x0e
#define	EDMADSTH	0x0f

#define	EDMACS		0x10
#define	EDMACSL		0x10
#define	EDMACSH		0x11

#define	ETXSTAT		0x12
#define	ETXSTATL	0x12
#define	ETXSTATH	0x13

#define	ETXWIRE		0x14
#define	ETXWIREL	0x14
#define	ETXWIREH	0x15

#define	EUDAST		0x16
#define	EUDASTL		0x16
#define	EUDASTH		0x17

#define	EUDAND		0x18
#define	EUDANDL		0x18
#define	EUDANDH		0x19

#define	ESTAT		0x1a
#define	ESTATL		0x1a
#define	ESTATH		0x1b

#define	EIR			0x1c
#define	EIRL		0x1c
#define	EIRH		0x1d

#define	ECON1		0x1e
#define	ECON1L		0x1e
#define	ECON1H		0x1f

// SPI Bank 1 registers
#define	EHT1		0x20
#define	EHT1L		0x20
#define	EHT1H		0x21
#define	EHT2		0x22
#define	EHT2L		0x22
#define	EHT2H		0x23
#define	EHT3		0x24
#define	EHT3L		0x24
#define	EHT3H		0x25
#define	EHT4		0x26
#define	EHT4L		0x26
#define	EHT4H		0x27
#define	EPMM1		0x28
#define	EPMM1L		0x28
#define	EPMM1H		0x29
#define	EPMM2		0x2a
#define	EPMM2L		0x2a
#define	EPMM2H		0x2b
#define	EPMM3		0x2c
#define	EPMM3L		0x2c
#define	EPMM3H		0x2d
#define	EPMM4		0x2e
#define	EPMM4L		0x2e
#define	EPMM4H		0x2f
#define	EPMCS		0x30
#define	EPMCSL		0x30
#define	EPMCSH		0x31
#define	EPMO		0x32
#define	EPMOL		0x32
#define	EPMOH		0x33
#define	ERXFCON		0x34
#define	ERXFCONL	0x34
#define	ERXFCONH	0x35

// SPI Bank 2 registers
#define	MACON1		0x40
#define	MACON1L		0x40
#define	MACON1H		0x41
#define	MACON2		0x42
#define	MACON2L		0x42
#define	MACON2H		0x43
#define	MABBIPG		0x44
#define	MABBIPGL	0x44
#define	MABBIPGH	0x45
#define	MAIPG		0x46
#define	MAIPGL		0x46
#define	MAIPGH		0x47
#define	MACLCON		0x48
#define	MACLCONL	0x48
#define	MACLCONH	0x49
#define	MAMXFL		0x4a
#define	MAMXFLL		0x4a
#define	MAMXFLH		0x4b
#define	MICMD		0x52
#define	MICMDL		0x52
#define	MICMDH		0x53
#define	MIREGADR	0x54
#define	MIREGADRL	0x54
#define	MIREGADRH	0x55

// SPI Bank 3 registers
#define	MAADR3		0x60
#define	MAADR3L		0x60
#define	MAADR3H		0x61
#define	MAADR2		0x62
#define	MAADR2L		0x62
#define	MAADR2H		0x63
#define	MAADR1		0x64
#define	MAADR1L		0x64
#define	MAADR1H		0x65
#define	MIWR		0x66
#define	MIWRL		0x66
#define	MIWRH		0x67
#define	MIRD		0x68
#define	MIRDL		0x68
#define	MIRDH		0x69
#define	MISTAT		0x6a
#define	MISTATL		0x6a
#define	MISTATH		0x6b
#define	EPAUS		0x6c
#define	EPAUSL		0x6c
#define	EPAUSH		0x6d
#define	ECON2		0x6e
#define	ECON2L		0x6e
#define	ECON2H		0x6f
#define	ERXWM		0x70
#define	ERXWML		0x70
#define	ERXWMH		0x71
#define	EIE			0x72
#define	EIEL		0x72
#define	EIEH		0x73
#define	EIDLED		0x74
#define	EIDLEDL		0x74
#define	EIDLEDH		0x75

// SPI unbanked registers
#define	EGPDATA		0x80
#define	ERXDATA		0x82
#define	EUDADATA	0x84
#define	EGPRDPT		0x86
#define	EGPRDPTL	0x86
#define	EGPRDPTH	0x87
#define	EGPWRPT		0x88
#define	EGPWRPTL	0x88
#define	EGPWRPTH	0x89
#define	ERXRDPT		0x8a
#define	ERXRDPTL	0x8a
#define	ERXRDPTH	0x8b
#define	ERXWRPT		0x8c
#define	ERXWRPTL	0x8c
#define	ERXWRPTH	0x8d
#define	EUDARDPT	0x8e
#define	EUDARDPTL	0x8e
#define	EUDARDPTH	0x8f
#define	EUDAWRPT	0x90
#define	EUDAWRPTL	0x90
#define	EUDAWRPTH	0x91

// PHY registers
#define	PHCON1		0x00
#define	PHSTAT1		0x01
#define	PHANA		0x04
#define	PHANLPA		0x05
#define	PHANE		0x06
#define	PHCON2		0x11
#define	PHSTAT2		0x1b
#define	PHSTAT3		0x1f


/*******************************************************************************
 * ENC424J600 Registers Bits
 ******************************************************************************/

// ECON1 - Ethernet control 1
#define	RXEN		(1<<0)
#define	TXRTS		(1<<1)
#define	DMANOCS		(1<<2)
#define	DMACSSD		(1<<3)
#define	DMACPY		(1<<4)
#define	DMAST		(1<<5)
#define	FCOP0		(1<<6)
#define	FCOP1		(1<<7)
#define	PKTDEC		(1<<8)
#define	AESOP0		(1<<9)
#define	AESOP1		(1<<10)
#define	AESST		(1<<11)
#define	HASHLST		(1<<12)
#define	HASHOP		(1<<13)
#define	HASHEN		(1<<14)
#define	MODEXST		(1<<15)

// ECON2 - Ethernet control 2
#define	AESLEN0		(1<<0)
#define	AESLEN1		(1<<1)
#define	MODLEN0		(1<<2)
#define	MODLEN1		(1<<3)
#define	ETHRST		(1<<4)
#define	RXRST		(1<<5)
#define	TXRST		(1<<6)
#define	AUTOFC		(1<<7)
#define	COCON0		(1<<8)
#define	COCON1		(1<<9)
#define	COCON2		(1<<10)
#define	COCON3		(1<<11)
#define	SHA1MD5		(1<<12)
#define	TXMAC		(1<<13)
#define	STRCH		(1<<14)
#define	ETHEN		(1<<15)

// EIDLED - Ethernet ID status/LED control
#define	REVID0		(1<<0)
#define	REVID1		(1<<1)
#define	REVID2		(1<<2)
#define	REVID3		(1<<3)
#define	REVID4		(1<<4)
#define	DEVID0		(1<<5)
#define	DEVID1		(1<<6)
#define	DEVID2		(1<<7)
#define	LBCFG0		(1<<8)
#define	LBCFG1		(1<<9)
#define	LBCFG2		(1<<10)
#define	LBCFG3		(1<<11)
#define	LACFG0		(1<<12)
#define	LACFG1		(1<<13)
#define	LACFG2		(1<<14)
#define	LACFG3		(1<<15)

// EIE - Ethernet interrupt enable register
#define	PCFULIE		(1<<0)
#define	RXABTIE		(1<<1)
#define	TXABTIE		(1<<2)
#define	TXIE		(1<<3)
#define	DMAIE		(1<<5)
#define	PKTIE		(1<<6)
#define	LINKIE		(1<<11)
#define	AESIE		(1<<12)
#define	HASHIE		(1<<13)
#define	MODEXIE		(1<<14)
#define	INTIE		(1<<15)

// EIR - Ethernet interrupt flag
#define	PCFULIF		(1<<0)
#define	RXABTIF		(1<<1)
#define	TXABTIF		(1<<2)
#define	TXIF		(1<<3)
#define	DMAIF		(1<<5)
#define	PKTIF		(1<<6)
#define	LINKIF		(1<11)
#define	AESIF		(1<<12)
#define	HASHIF		(1<<13)
#define	MODEXIF		(1<<14)
#define	CRYPTEN		(1<<15)

// ERXFCON - Ethernet RX filter control
#define	BCEN		(1<<0)
#define	MCEN		(1<<1)
#define	NOTMEEN		(1<<2)
#define	UCEN		(1<<3)
#define	RUNTEN		(1<<4)
#define	RUNTEEN		(1<<5)
#define	CRCEN		(1<<6)
#define	CRCEEN		(1<<7)
#define	PMEN0		(1<<8)
#define	PMEN1		(1<<9)
#define	PMEN2		(1<<10)
#define	PMEN3		(1<<11)
#define	NOTPM		(1<<12)
#define	MPEN		(1<<14)
#define	HTEN		(1<<15)

// ESTAT - Ethernet status register
#define	PKTCNT		(0x00ff)
#define	PKTCNT0		(1<<0)
#define	PKTCNT1		(1<<1)
#define	PKTCNT2		(1<<2)
#define	PKTCNT3		(1<<3)
#define	PKTCNT4		(1<<4)
#define	PKTCNT5		(1<<5)
#define	PKTCNT6		(1<<6)
#define	PKTCNT7		(1<<7)
#define	PHYLNK		(1<<8)
#define	PHYDPX		(1<<10)
#define	CLKRDY		(1<<12)
#define	RXBUSY		(1<<13)
#define	FCIDLE		(1<<14)
#define	INT			(1<<15)

// ETXSTAT - Ethernet transmit status
#define	COLCNT0		(1<<0)
#define	COLCNT1		(1<<1)
#define	COLCNT2		(1<<2)
#define	COLCNT3		(1<<3)
#define	CRCBAD		(1<<4)
#define	DEFER_ETXSTAT	(1<<7)
#define	EXDEFER		(1<<8)
#define	MAXCOL		(1<<9)
#define	LATECOL		(1<<10)

// MACON1 - MAC control 1
#define	PASSALL		(1<<1)
#define	RXPAUS		(1<<2)
#define	LOOPBK		(1<<4)

// MACON2 - MAC control 2
#define	FULDPX		(1<<0)
#define	HFRMEN		(1<<2)
#define	PHDREN		(1<<3)
#define	TXCRCEN		(1<<4)
#define	PADCFG0		(1<<5)
#define	PADCFG1		(1<<6)
#define	PADCFG2		(1<<7)
#define	NOBKOFF		(1<<12)
#define	BPEN		(1<<13)
#define	DEFER_MACON2	(1<<14)

// MICMD - MII management command
#define	MIIRD		(1<<0)
#define	MIISCAN		(1<<1)

// MISTAT - MII management status
#define	BUSY		(1<<0)
#define	SCAN		(1<<1)
#define	NVALID		(1<<2)

// PHANA - PHY auto-negotiation advertisement
#define	ADIEEE0		(1<<0)
#define	ADIEEE1		(1<<1)
#define	ADIEEE2		(1<<2)
#define	ADIEEE3		(1<<3)
#define	ADIEEE4		(1<<4)
#define	AD10		(1<<5)
#define	AD10FD		(1<<6)
#define	AD100		(1<<7)
#define	AD100FD		(1<<8)
#define	ADPAUS0		(1<<10)
#define	ADPAUS1		(1<<11)
#define	ADFAULT		(1<<13)
#define	ADNP		(1<<15)

// PHANE - PHY auto-negotiation expansion
#define	LPANABL		(1<<0)
#define	LPARCD		(1<<1)
#define	PDFLT		(1<<4)

// PHANLPA - PHY auto-negotiation link partner ability
#define	LPIEEE0		(1<<0)
#define	LPIEEE1		(1<<1)
#define	LPIEEE2		(1<<2)
#define	LPIEEE3		(1<<3)
#define	LPIEEE4		(1<<4)
#define	LP10		(1<<5)
#define	LP10FD		(1<<6)
#define	LP100		(1<<7)
#define	LP100FD		(1<<8)
#define	LP100T4		(1<<9)
#define	LPPAUS0		(1<<10)
#define	LPPAUS1		(1<<11)
#define	LPFAULT		(1<<13)
#define	LPACK		(1<<14)
#define	LPNP		(1<<15)

// PHCON1 - PHY control 1
#define	PFULDPX		(1<<8)
#define	RENEG		(1<<9)
#define	PSLEEP		(1<<11)
#define	ANEN		(1<<12)
#define	SPD100		(1<<13)
#define	PLOOPBK		(1<<14)
#define	PRST		(1<<15)

// PHCON2 - PHY control 2
#define	EDSTAT		(1<<1)
#define	FRCLNK		(1<<2)
#define	EDTHRES		(1<<11)
#define	EDPWRDN		(1<<13)

// PHSTAT1 - PHY status 1
#define	EXTREGS		(1<<0)
#define	LLSTAT		(1<<2)
#define	ANABLE		(1<<3)
#define	LRFAULT		(1<<4)
#define	ANDONE		(1<<5)
#define	HALF10		(1<<11)
#define	FULL10		(1<<12)
#define	HALF100		(1<<13)
#define	FULL100		(1<<14)

// PHSTAT2 - PHY status 2
#define	PLRITY		(1<<4)

// PHSTAT3 - PHY status 3
#define	SPDDPX0		(1<<2)
#define	SPDDPX1		(1<<3)
#define	SPDDPX2		(1<<4)

#endif /* ENC424J600_REGISTERS_H_ */
