library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
	Generic ( 	Clk_divMax : integer := 13);

	Port (  output_mot :  		out STD_LOGIC_VECTOR (3 downto 0):="0000";
			  clk,sensor_en : in std_logic;
			  rx_out : out std_logic_vector(7 downto 0);
			  rx_data : in  STD_LOGIC;
			  digit4: out std_logic_vector(3 downto 0);
			  seg4: out std_logic_vector(7 downto 0)
		 );
end main;			  
architecture Behavioral of main is
	
component rf 
	Port (  rx_out : out std_logic_vector(7 downto 0);
			  data_ready : out  STD_LOGIC;
           rx_data,rx_16clk : in  STD_LOGIC);
end component ;

component rotator 
	 Port ( output_mot :  		out STD_LOGIC_VECTOR (3 downto 0):="0000";	--neaktivní uroven
			  clk : 		  			in  STD_LOGIC;
			  position :			in  STD_LOGIC_VECTOR (7 downto 0); -- pozice 0-199
			  position_en :      in  STD_LOGIC; 						  -- hranou spousti toceni na pozici
			  sensor_en :			in  STD_LOGIC);						  -- imp ze senzoru polohy, senzor je umisten v poloze Sensor_position v modulu rotator
end component ;

component DspDr
    Port( clk:       in std_logic;
          bcdint:    in std_logic_vector(11 downto 0);
          dp3,dp2,dp1,dp0: in std_logic;
          digit:     out std_logic_vector(3 downto 0);
		    seg:       out std_logic_vector(7 downto 0));
end component ;

component Bin9_BCD
		PORT(Bin: IN std_logic_vector(8 DOWNTO 0);
			  BCD: OUT std_logic_vector(11 DOWNTO 0));
end component;

	signal rx_16clk,rot_clk,data_ready,clk32k : STD_LOGIC ;	
	signal clk_div :STD_LOGIC_VECTOR (Clk_divMax downto 0):= (OTHERS => '0');
	signal position :STD_LOGIC_VECTOR (7 downto 0);
	signal bcdint: std_logic_vector(11 downto 0) := x"000";
	signal cnt_32k: std_logic_vector(10 downto 0);
	signal bin_deg: std_logic_vector(8 downto 0);

begin
u1 : rf PORT MAP (
   	rx_out => position,
		data_ready => data_ready,
		rx_data => rx_data,
		rx_16clk => rx_16clk
	);
	
u2 : rotator PORT MAP (
   	output_mot => output_mot,
	  	clk => rot_clk,
		position => position,
   	position_en => data_ready,
		sensor_en => sensor_en
	);	

u3 : DspDr PORT MAP (
		 clk=>clk,
		 bcdint=>bcdint,
       dp3=>'1',
		 dp2=>'1',
		 dp1=>'1',
		 dp0=>'1',
       digit=>digit4,
		 seg=>seg4
	);	
	
u4 : Bin9_BCD PORT MAP (
		 Bin=>bin_deg, 
		 BCD=>bcdint
	);	
	
process (clk)
begin	
if clk='1' AND clk'event then				
	clk_div <= clk_div  + 1;
	cnt_32k <= cnt_32k + 1;

	if cnt_32k <= X"1D" then				-- frekvence 2KHz z 1,8432MHz cita do 1CC log 1, pak do 398 log 0 
		clk32k <= '1';							
	else											-- pro 32 khz / 16 / 2 = 2khz    1D		3A
		if cnt_32k =X"3A" then
			cnt_32k <= (others=> '0');
			clk32k <= '0';
		end if;
	end if;	
end if;
end process;

Bin_Deg <= std_logic_vector( to_unsigned( to_integer(unsigned('0'& position) * 231/128), 9 ));
	-- Jeden krok ma 1,804 stupne = 231/128	
	-- Převod na stupne v rozsahu 0-360,prijatelná presnost +-1
	
rx_out <= position;
-- Kmitočty hodinových signálů	
rx_16clk<=clk32k;		
rot_clk <= clk_div(clk_divMax);		--1,8432M / 2na(13+1)=112,5 Hz

end Behavioral;
