    cpldfit:  version K.31                              Xilinx Inc.
                                      Fitter Report
    Design Name: main                                Date:  5-11-2009,  4:42PM
    Device Used: XC2C256-7-TQ144
    Fitting Status: Successful

    *************************  Mapped Resource Summary  **************************

    Macrocells     Product Terms    Function Block   Registers      Pins
    Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot
    220/256 ( 86%) 627 /896  ( 70%) 398 /640  ( 62%) 136/256 ( 53%) 27 /118 ( 23%)

    ** Function Block Resources **

    Function Mcells   FB Inps  Pterms   IO       CTC      CTR      CTS      CTE
    Block    Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
    FB1      16/16*    14/40    17/56     3/ 6    0/1      0/1      0/1      0/1
    FB2      16/16*    33/40    24/56     0/ 8    1/1*     0/1      0/1      0/1
    FB3      16/16*    17/40    28/56     3/ 6    1/1*     0/1      0/1      0/1
    FB4      16/16*    26/40    56/56*    4/ 8    0/1      0/1      0/1      0/1
    FB5      16/16*    22/40    28/56     2/ 5    1/1*     0/1      0/1      0/1
    FB6      16/16*    18/40    20/56     3/ 8    1/1*     0/1      0/1      0/1
    FB7      16/16*    21/40    26/56     3/ 8    1/1*     0/1      0/1      0/1
    FB8      16/16*    37/40    54/56     4/ 8    1/1*     1/1*     1/1*     0/1
    FB9       8/16     33/40    56/56*    0/ 8    0/1      0/1      0/1      0/1
    FB10     13/16     30/40    56/56*    0/ 9    1/1*     1/1*     0/1      0/1
    FB11     12/16     38/40*   29/56     2/ 8    0/1      0/1      0/1      0/1
    FB12      7/16     23/40    56/56*    0/ 6    0/1      0/1      0/1      0/1
    FB13     12/16     23/40    56/56*    0/ 8    0/1      0/1      0/1      0/1
    FB14     16/16*    27/40    56/56*    0/ 8    0/1      0/1      0/1      0/1
    FB15     16/16*    19/40    33/56     0/ 7    1/1*     0/1      0/1      0/1
    FB16      8/16     17/40    32/56     0/ 7    1/1*     0/1      0/1      0/1
             -----    -------  -------   -----    ---      ---      ---      ---
    Total   220/256   398/640  627/896   24/118   9/16     2/16     1/16     0/16

    CTC - Control Term Clock
    CTR - Control Term Reset
    CTS - Control Term Set
    CTE - Control Term Output Enable

    * - Resource is exhausted

    ** Global Control Resources **

    GCK         GSR         GTS
    Used/Tot    Used/Tot    Used/Tot
    1/3         0/1         0/4

    Signal 'clk' mapped onto global clock net GCK2.

    ** Pin Resources **

    Signal Type    Required     Mapped  |  Pin Type            Used    Total
    ------------------------------------|------------------------------------
    Input         :    2           2    |  I/O              :    22    108
    Output        :   24          24    |  GCK/IO           :     3      3
    Bidirectional :    0           0    |  GTS/IO           :     0      4
    GCK           :    1           1    |  GSR/IO           :     0      1
    GTS           :    0           0    |  CDR/IO           :     1      1
    GSR           :    0           0    |  DGE/IO           :     1      1
                     ----        ----
            Total     27          27

    End of Mapped Resource Summary
    **************************  Errors and Warnings  ***************************

    INFO:Cpld - Inferring BUFG constraint for signal 'clk' based upon the LOC
       constraint 'P38'. It is recommended that you declare this BUFG explicitedly
       in your design. Note that for certain device families the output of a BUFG
       constraint can not drive a gated clock, and the BUFG constraint will be
       ignored.
    WARNING:Cpld:945 - The component 'u4/XLXI_40' has no outputs and will be
       deleted.
    *************************  Summary of Mapped Logic  ************************

    ** 24 Outputs **

    Signal                                        Total Total Loc     Pin   Pin       Pin     I/O      I/O       Slew Reg     Reg Init
    Name                                          Pts   Inps          No.   Type      Use     STD      Style     Rate Use     State
    seg4<7>                                       2     4     FB1_4   142   I/O       O       LVCMOS33           FAST DFF     RESET
    seg4<6>                                       2     4     FB1_12  139   I/O       O       LVCMOS33           FAST DFF     RESET
    seg4<5>                                       3     4     FB1_14  137   I/O       O       LVCMOS33           FAST DFF     RESET
    seg4<4>                                       4     4     FB3_2   135   I/O       O       LVCMOS33           FAST DFF     RESET
    seg4<3>                                       2     4     FB3_5   133   I/O       O       LVCMOS33           FAST DFF     RESET
    seg4<2>                                       3     4     FB3_16  131   I/O       O       LVCMOS33           FAST DFF     RESET
    digit4<0>                                     1     2     FB4_5   15    I/O       O       LVCMOS33           FAST DFF     RESET
    digit4<1>                                     1     2     FB4_6   16    I/O       O       LVCMOS33           FAST DFF     RESET
    digit4<2>                                     1     2     FB4_12  17    I/O       O       LVCMOS33           FAST DFF     RESET
    digit4<3>                                     1     2     FB4_14  18    I/O       O       LVCMOS33           FAST DFF     RESET
    rx_out<4>                                     3     3     FB5_4   32    GCK/I/O   O       LVCMOS33           FAST DEFF    RESET
    rx_out<5>                                     3     3     FB5_6   30    GCK/I/O   O       LVCMOS33           FAST DEFF    RESET
    rx_out<3>                                     3     3     FB6_2   35    CDR/I/O   O       LVCMOS33           FAST DEFF    RESET
    rx_out<1>                                     3     3     FB6_12  39    DGE/I/O   O       LVCMOS33           FAST DEFF    RESET
    rx_out<0>                                     3     3     FB6_15  42    I/O       O       LVCMOS33           FAST DEFF    RESET
    rx_out<6>                                     3     3     FB7_5   26    I/O       O       LVCMOS33           FAST DEFF    RESET
    rx_out<7>                                     3     3     FB7_11  24    I/O       O       LVCMOS33           FAST DEFF    RESET
    rx_out<2>                                     3     3     FB7_12  23    I/O       O       LVCMOS33           FAST DEFF    RESET
    output_mot<0>                                 2     4     FB8_2   45    I/O       O       LVCMOS33           FAST
    output_mot<1>                                 2     4     FB8_5   48    I/O       O       LVCMOS33           FAST
    output_mot<2>                                 2     4     FB8_11  50    I/O       O       LVCMOS33           FAST
    output_mot<3>                                 2     4     FB8_13  52    I/O       O       LVCMOS33           FAST
    seg4<0>                                       1     1     FB11_13 126   I/O       O       LVCMOS33           FAST DFF     RESET
    seg4<1>                                       2     4     FB11_15 129   I/O       O       LVCMOS33           FAST DFF     RESET

    ** 196 Buried Nodes **

    Signal                                        Total Total Loc     Reg     Reg Init
    Name                                          Pts   Inps          Use     State
    clk_div<7>                                    1     7     FB1_1   TFF     RESET
    clk_div<6>                                    1     6     FB1_2   TFF     RESET
    clk_div<10>                                   1     10    FB1_3   TFF     RESET
    clk_div<5>                                    1     5     FB1_5   TFF     RESET
    clk_div<9>                                    1     9     FB1_6   TFF     RESET
    clk_div<4>                                    1     4     FB1_7   TFF     RESET
    clk_div<3>                                    1     3     FB1_8   TFF     RESET
    clk_div<2>                                    1     2     FB1_9   TFF     RESET
    clk_div<1>                                    1     1     FB1_10  TFF     RESET
    u3/mhertz_count                               0     0     FB1_11  TFF     RESET
    clk_div<8>                                    1     8     FB1_13  TFF     RESET
    u3/dp                                         0     0     FB1_15  DFF     RESET
    clk_div<0>                                    0     0     FB1_16  TFF     RESET
    u1/regrx<30>                                  2     2     FB2_1   DFF     RESET
    u1/regrx<17>                                  2     2     FB2_2   DFF     RESET
    u1/regrx<2>                                   2     2     FB2_3   DFF     RESET
    u1/regrx<28>                                  2     2     FB2_4   DFF     RESET
    u1/regrx<27>                                  2     2     FB2_5   DFF     RESET
    u1/regrx<16>                                  2     2     FB2_6   DFF     RESET
    u1/regrx<10>                                  2     2     FB2_7   DFF     RESET
    u1/regrx<0>                                   2     2     FB2_8   DFF     RESET
    u3/mhertz_en                                  1     1     FB2_9   DFF     RESET
    u3/cd<1>                                      1     2     FB2_10  TFF     RESET
    u3/cd<0>                                      1     1     FB2_11  TFF     RESET
    u1/regrx<26>                                  2     2     FB2_12  DFF     RESET
    u1/regrx<20>                                  2     2     FB2_13  DFF     RESET
    u1/regrx<1>                                   2     2     FB2_14  DFF     RESET
    u1/regrx<18>                                  2     2     FB2_15  DFF     RESET
    N_PZ_750                                      8     29    FB2_16
    u1/rxd1                                       2     2     FB3_1   DFF     RESET
    clk32k                                        5     12    FB3_3   TFF     RESET
    cnt_32k<5>                                    2     11    FB3_4   TFF     RESET
    cnt_32k<4>                                    2     11    FB3_6   TFF     RESET
    cnt_32k<3>                                    2     11    FB3_7   TFF     RESET
    cnt_32k<0>                                    1     11    FB3_8   TFF     RESET
    cnt_32k<10>                                   1     10    FB3_9   TFF     RESET
    cnt_32k<9>                                    1     9     FB3_10  TFF     RESET
    cnt_32k<8>                                    1     8     FB3_11  TFF     RESET
    cnt_32k<7>                                    1     7     FB3_12  TFF     RESET
    cnt_32k<6>                                    1     6     FB3_13  TFF     RESET

    Signal                                        Total Total Loc     Reg     Reg Init
    Name                                          Pts   Inps          Use     State
    cnt_32k<1>                                    2     11    FB3_14  TFF     RESET
    cnt_32k<2>                                    1     2     FB3_15  TFF     RESET
    N_PZ_929                                      2     3     FB4_1
    N_PZ_1022                                     2     4     FB4_2
    Mmult_bin_deg_mult0000__or0028                5     6     FB4_3
    u4/XLXN_37                                    2     5     FB4_4
    u4/XLXI_47/S0_or000011                        1     5     FB4_7
    u4/XLXN_36                                    2     8     FB4_8
    u4/XLXI_22/S1_or00006                         1     7     FB4_9
    u4/XLXN_38                                    5     10    FB4_10
    u3/curr<0>                                    14    16    FB4_11  DFF     RESET
    u3/curr<1>                                    9     16    FB4_13  DFF     RESET
    u3/curr<2>                                    8     15    FB4_15  DFF     RESET
    u3/curr<3>                                    5     10    FB4_16  DFF     RESET
    u1/regrx<13>                                  2     2     FB5_1   DFF     RESET
    u1/regrx<23>                                  2     2     FB5_2   DFF     RESET
    u1/regrx<12>                                  2     2     FB5_3   DFF     RESET
    u1/regrx<22>                                  2     2     FB5_5   DFF     RESET
    u1/regrx<11>                                  2     2     FB5_7   DFF     RESET
    N_PZ_970                                      1     2     FB5_8
    u1/regrx<9>                                   2     2     FB5_9   DFF     RESET
    u1/regrx<29>                                  2     2     FB5_10  DFF     RESET
    u1/regrx<19>                                  2     2     FB5_11  DFF     RESET
    u1/rx_out_or000044                            8     12    FB5_12
    u1/rx_out_or000047                            8     14    FB5_13
    u1/regrx<21>                                  2     2     FB5_14  DFF     RESET
    u1/regrx<15>                                  2     2     FB5_15  DFF     RESET
    u1/regrx<14>                                  2     2     FB5_16  DFF     RESET
    u1/regrx<4>                                   2     2     FB6_1   DFF     RESET
    u1/regrx<35>                                  2     2     FB6_3   DFF     RESET
    u1/regrx<3>                                   2     2     FB6_4   DFF     RESET
    u1/regrx<34>                                  2     2     FB6_5   DFF     RESET
    u1/regrx<33>                                  2     2     FB6_6   DFF     RESET
    u1/regrx<32>                                  2     2     FB6_7   DFF     RESET
    u1/regrx<31>                                  2     2     FB6_8   DFF     RESET
    u1/regrx<25>                                  2     2     FB6_9   DFF     RESET
    u1/regrx<24>                                  2     2     FB6_10  DFF     RESET
    N_PZ_1032                                     1     2     FB6_11
    u1/regrx<38>                                  2     2     FB6_13  DFF     RESET
    u1/regrx<37>                                  2     2     FB6_14  DFF     RESET

    Signal                                        Total Total Loc     Reg     Reg Init
    Name                                          Pts   Inps          Use     State
    u1/regrx<36>                                  2     2     FB6_16  DFF     RESET
    u3/khertz_en                                  1     11    FB7_1   DFF     RESET
    u3/khertz_count<4>                            1     5     FB7_2   TFF     RESET
    u3/khertz_count<2>                            1     3     FB7_3   TFF     RESET
    u3/khertz_count<1>                            1     2     FB7_4   TFF     RESET
    u3/khertz_count<7>                            7     12    FB7_6   DFF     RESET
    u1/regrx<8>                                   2     2     FB7_7   DFF     RESET
    u1/regrx<7>                                   2     2     FB7_8   DFF     RESET
    u1/regrx<6>                                   2     2     FB7_9   DFF     RESET
    u1/regrx<5>                                   2     2     FB7_10  DFF     RESET
    u3/khertz_count<9>                            2     12    FB7_13  TFF     RESET
    u3/khertz_count<8>                            2     12    FB7_14  TFF     RESET
    u3/khertz_count<0>                            2     11    FB7_15  TFF     RESET
    u3/khertz_count<3>                            2     11    FB7_16  TFF     RESET
    u2/forward_backward                           17    27    FB8_1   DFF/S   SET
    N_PZ_977                                      1     5     FB8_3
    u2/sensor_set                                 3     5     FB8_4   TFF/S   SET
    N_PZ_1003                                     1     5     FB8_6
    u2/cnt_reg<0>                                 3     5     FB8_7   TFF     RESET
    u2/cnt_reg<1>                                 4     7     FB8_8   TFF     RESET
    u2/run                                        3     5     FB8_9   DFF     RESET
    u2/now_ST_FFd4                                7     7     FB8_10  DFF     RESET
    N_PZ_967                                      2     4     FB8_12
    u2/now_ST_FFd3                                6     7     FB8_14  DFF     RESET
    u2/now_ST_FFd2                                5     7     FB8_15  TFF     RESET
    u2/now_ST_FFd1                                4     7     FB8_16  DFF     RESET
    Mmult_bin_deg_mult0000__or0017                4     10    FB9_3
    u2/cnt_catch_cmp_le0000                       2     5     FB9_5
    Mmult_bin_deg_mult0000_Mxor__index0016        7     8     FB9_7
    Mmult_bin_deg_mult0000_Mxor__index0015        12    14    FB9_8
    N_PZ_642                                      3     4     FB9_9
    N_PZ_695                                      2     4     FB9_10
    N_PZ_762                                      7     11    FB9_11
    u2/Mcompar_forward_backward_cmp_lt0000_ALB20  21    16    FB9_16
    u2/SF17                                       1     2     FB10_4
    N_PZ_789                                      2     4     FB10_5
    u2/_sub0000<6>                                6     7     FB10_6
    u2/cnt_reg<5>                                 6     11    FB10_7  TFF     RESET
    u2/cnt_reg<3>                                 6     11    FB10_8  TFF     RESET
    u2/cnt_reg<7>                                 5     11    FB10_9  TFF     RESET

    Signal                                        Total Total Loc     Reg     Reg Init
    Name                                          Pts   Inps          Use     State
    u2/cnt_reg<6>                                 5     11    FB10_10 TFF     RESET
    u2/cnt_reg<4>                                 5     11    FB10_11 TFF     RESET
    u2/Msub__sub0000__or0006                      3     7     FB10_12
    u2/_mux0000                                   5     8     FB10_13
    u2/forward_backward_mux000876                 4     10    FB10_14
    u2/sensor_set_cmp_ne0000                      16    16    FB10_15
    u2/cnt_reg<2>                                 3     5     FB10_16 TFF     RESET
    N_PZ_619                                      2     3     FB11_1
    N_PZ_621                                      1     2     FB11_2
    N_PZ_936                                      1     4     FB11_3
    u3/khertz_count<6>                            6     12    FB11_4  DFF     RESET
    u3/khertz_count<5>                            5     12    FB11_7  DFF     RESET
    clk_div<13>                                   1     13    FB11_8  TFF     RESET
    clk_div<12>                                   1     12    FB11_9  TFF     RESET
    clk_div<11>                                   1     11    FB11_10 TFF     RESET
    N_PZ_911                                      1     2     FB11_14
    N_PZ_689                                      7     7     FB11_16
    N_PZ_653                                      1     4     FB12_5
    Mmult_bin_deg_mult0000_Mxor__index0021        8     6     FB12_6
    Mmult_bin_deg_mult0000_Mxor__index0031        4     5     FB12_7
    bin_deg<1>                                    6     7     FB12_8
    Mmult_bin_deg_mult0000__or00213               6     9     FB12_9
    Mmult_bin_deg_mult0000__or0014                15    10    FB12_10
    Mmult_bin_deg_mult0000_Mxor__index0014        16    11    FB12_16
    N_PZ_615                                      2     3     FB13_4
    Mmult_bin_deg_mult0000__or0031                3     7     FB13_6
    N_PZ_604                                      3     3     FB13_7
    N_PZ_624                                      2     5     FB13_8
    u4/XLXN_81                                    9     9     FB13_9
    u4/XLXI_46/S1_or00007                         6     8     FB13_10
    u4/XLXN_83                                    3     8     FB13_11
    u4/XLXN_27                                    4     5     FB13_12
    N_PZ_666                                      3     4     FB13_13
    N_PZ_632                                      3     3     FB13_14
    Mmult_bin_deg_mult0000_Mxor__index0033        8     8     FB13_15
    Mmult_bin_deg_mult0000_Mxor__index0032        12    10    FB13_16
    u2/Msub__sub0000__or0003                      2     4     FB14_1
    u2/_sub0000<3>                                3     3     FB14_2
    N_PZ_643                                      2     4     FB14_3
    N_PZ_680                                      3     3     FB14_4

    Signal                                        Total Total Loc     Reg     Reg Init
    Name                                          Pts   Inps          Use     State
    N_PZ_904                                      2     2     FB14_5
    N_PZ_971                                      3     4     FB14_6
    N_PZ_761                                      2     4     FB14_7
    N_PZ_606                                      3     3     FB14_8
    Mmult_bin_deg_mult0000_Mxor__index0029        3     3     FB14_9
    Mmult_bin_deg_mult0000__or0023                3     7     FB14_10
    Mmult_bin_deg_mult0000_Mxor__index0030        8     6     FB14_11
    Mmult_bin_deg_mult0000_Mxor__index0020        3     3     FB14_12
    bin_deg<4>                                    8     6     FB14_13
    bin_deg<3>                                    3     3     FB14_14
    Mmult_bin_deg_mult0000_Mxor__index0022        6     8     FB14_15
    u4/XLXN_33                                    2     2     FB14_16
    N_PZ_907                                      2     2     FB15_1
    u1/rxd2                                       2     2     FB15_2  DFF     RESET
    u2/cnt_catch<7>                               3     3     FB15_3  DEFF    RESET
    u2/cnt_catch<6>                               3     3     FB15_4  DEFF    RESET
    u2/cnt_catch<5>                               3     3     FB15_5  DEFF    RESET
    u2/cnt_catch<4>                               3     3     FB15_6  DEFF    RESET
    u2/cnt_catch<3>                               3     3     FB15_7  DEFF    RESET
    u2/cnt_catch<2>                               3     3     FB15_8  DEFF    RESET
    u2/cnt_catch<1>                               3     3     FB15_9  DEFF    RESET
    u2/cnt_catch<0>                               3     3     FB15_10 DEFF    RESET
    u1/clkdiv<0>                                  2     3     FB15_11 DFF/S   SET
    u1/clkdiv<1>                                  3     4     FB15_12 DFF/S   SET
    u1/clkdiv<2>                                  3     5     FB15_13 TFF/S   SET
    u1/regrx<39>                                  1     1     FB15_14 DFF     RESET
    data_ready                                    3     6     FB15_15 TFF     RESET
    u2/_sub0000<5>                                3     3     FB15_16
    u1/edge                                       3     3     FB16_2  DFF     RESET
    u4/XLXN_34                                    4     7     FB16_3
    N_PZ_641                                      4     7     FB16_4
    u4/XLXN_35                                    4     5     FB16_7
    u4/XLXN_41                                    3     4     FB16_8
    u4/XLXN_29                                    4     7     FB16_9
    u4/XLXN_94                                    5     7     FB16_10
    u4/XLXN_28                                    6     7     FB16_14

    ** 3 Inputs **

    Signal                                        Loc     Pin   Pin       Pin     I/O      I/O
    Name                                                  No.   Type      Use     STD      Style
    clk                                           FB6_4   38    GCK/I/O   GCK     LVCMOS33 KPR
    sensor_en                                     FB11_12 125   I/O       I       LVCMOS33 KPR
    rx_data                                       FB15_14 88    I/O       I       LVCMOS33

    Legend:
    Pin No.   - ~     - User Assigned
    I/O Style - OD    - OpenDrain
              - PU    - Pullup
              - KPR   - Keeper
              - S     - SchmittTrigger
              - DG    - DataGate
    Reg Use   - LATCH - Transparent latch
              - DFF   - D-flip-flop
              - DEFF  - D-flip-flop with clock enable
              - TFF   - T-flip-flop
              - TDFF  - Dual-edge-triggered T-flip-flop
              - DDFF  - Dual-edge-triggered flip-flop
              - DDEFF - Dual-edge-triggered flip-flop with clock enable
              /S (after any above flop/latch type) indicates initial state is Set
    **************************  Function Block Details  ************************
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
                  VRF - Vref
    Pin No.      - ~  - User Assigned
    *********************************** FB1  ***********************************
    This function block is part of I/O Bank number:               2
    Number of function block inputs used/remaining:               14/26
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   17/39
    Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
    Name                          Pt            No.  Type    Use
    clk_div<7>                    1     FB1_1        (b)     (b)
    clk_div<6>                    1     FB1_2        (b)     (b)
    clk_div<10>                   1     FB1_3   143  GSR/I/O (b)
    seg4<7>                       2     FB1_4   142  I/O     O
    clk_div<5>                    1     FB1_5        (b)     (b)
    clk_div<9>                    1     FB1_6   140  I/O     (b)
    clk_div<4>                    1     FB1_7        (b)     (b)
    clk_div<3>                    1     FB1_8        (b)     (b)
    clk_div<2>                    1     FB1_9        (b)     (b)
    clk_div<1>                    1     FB1_10       (b)     (b)
    u3/mhertz_count               0     FB1_11       (b)     (b)
    seg4<6>                       2     FB1_12  139  I/O     O
    clk_div<8>                    1     FB1_13  138  I/O     (b)
    seg4<5>                       3     FB1_14  137  I/O     O
    u3/dp                         0     FB1_15       (b)     (b)
    clk_div<0>                    0     FB1_16       (b)     (b)

    Signals Used by Logic in Function Block
      1: clk_div<0>         6: clk_div<5>        11: u3/curr<0>
      2: clk_div<1>         7: clk_div<6>        12: u3/curr<1>
      3: clk_div<2>         8: clk_div<7>        13: u3/curr<2>
      4: clk_div<3>         9: clk_div<8>        14: u3/curr<3>
      5: clk_div<4>        10: clk_div<9>

    Signal                     1         2         3         4 FB
    Name             0----+----0----+----0----+----0----+----0 Inputs
    clk_div<7>        XXXXXXX................................. 7
    clk_div<6>        XXXXXX.................................. 6
    clk_div<10>       XXXXXXXXXX.............................. 10
    seg4<7>           ..........XXXX.......................... 4
    clk_div<5>        XXXXX................................... 5
    clk_div<9>        XXXXXXXXX............................... 9
    clk_div<4>        XXXX.................................... 4
    clk_div<3>        XXX..................................... 3
    clk_div<2>        XX...................................... 2
    clk_div<1>        X....................................... 1
    u3/mhertz_count   ........................................ 0
    seg4<6>           ..........XXXX.......................... 4
    clk_div<8>        XXXXXXXX................................ 8
    seg4<5>           ..........XXXX.......................... 4
    u3/dp             ........................................ 0
    clk_div<0>        ........................................ 0
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    *********************************** FB2  ***********************************
    This function block is part of I/O Bank number:               2
    Number of function block inputs used/remaining:               33/7
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   24/32
    Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
    Name                          Pt            No.  Type    Use
    u1/regrx<30>                  2     FB2_1   2    GTS/I/O (b)    +
    u1/regrx<17>                  2     FB2_2        (b)     (b)    +
    u1/regrx<2>                   2     FB2_3   3    GTS/I/O (b)    +
    u1/regrx<28>                  2     FB2_4   4    I/O     (b)    +
    u1/regrx<27>                  2     FB2_5   5    GTS/I/O (b)    +
    u1/regrx<16>                  2     FB2_6        (b)     (b)    +
    u1/regrx<10>                  2     FB2_7        (b)     (b)    +
    u1/regrx<0>                   2     FB2_8        (b)     (b)    +
    u3/mhertz_en                  1     FB2_9        (b)     (b)
    u3/cd<1>                      1     FB2_10       (b)     (b)
    u3/cd<0>                      1     FB2_11       (b)     (b)
    u1/regrx<26>                  2     FB2_12  6    GTS/I/O (b)    +
    u1/regrx<20>                  2     FB2_13  7    I/O     (b)    +
    u1/regrx<1>                   2     FB2_14  9    I/O     (b)    +
    u1/regrx<18>                  2     FB2_15  10   I/O     (b)    +
    N_PZ_750                      8     FB2_16       (b)     (b)

    Signals Used by Logic in Function Block
      1: N_PZ_970          12: u1/regrx<2>       23: u1/regrx<4>
      2: data_ready        13: u1/regrx<31>      24: u1/regrx<5>
      3: u1/regrx<11>      14: u1/regrx<32>      25: u1/regrx<6>
      4: u1/regrx<17>      15: u1/regrx<33>      26: u1/regrx<7>
      5: u1/regrx<18>      16: u1/regrx<34>      27: u1/regrx<8>
      6: u1/regrx<19>      17: u1/regrx<35>      28: u1/regrx<9>
      7: u1/regrx<1>       18: u1/regrx<36>      29: u1/rx_out_or000044
      8: u1/regrx<21>      19: u1/regrx<37>      30: u1/rx_out_or000047
      9: u1/regrx<27>      20: u1/regrx<38>      31: u3/cd<0>
     10: u1/regrx<28>      21: u1/regrx<39>      32: u3/khertz_en
     11: u1/regrx<29>      22: u1/regrx<3>       33: u3/mhertz_count

    Signal                     1         2         3         4 FB
    Name             0----+----0----+----0----+----0----+----0 Inputs
    u1/regrx<30>      .X..........X........................... 2
    u1/regrx<17>      .X..X................................... 2
    u1/regrx<2>       .X...................X.................. 2
    u1/regrx<28>      .X........X............................. 2
    u1/regrx<27>      .X.......X.............................. 2
    u1/regrx<16>      .X.X.................................... 2
    u1/regrx<10>      .XX..................................... 2
    u1/regrx<0>       .X....X................................. 2
    u3/mhertz_en      ................................X....... 1
    u3/cd<1>          ..............................XX........ 2
    u3/cd<0>          ...............................X........ 1
    u1/regrx<26>      .X......X............................... 2
    u1/regrx<20>      .X.....X................................ 2
    u1/regrx<1>       .X.........X............................ 2
    u1/regrx<18>      .X...X.................................. 2
    N_PZ_750          X.XXXXXXXXXXXXXXXXXXXXXXXXXXXX.......... 29
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    *********************************** FB3  ***********************************
    This function block is part of I/O Bank number:               2
    Number of function block inputs used/remaining:               17/23
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   28/28
    Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
    Name                          Pt            No.  Type    Use
    u1/rxd1                       2     FB3_1   136  I/O     (b)    +
    seg4<4>                       4     FB3_2   135  I/O     O
    clk32k                        5     FB3_3   134  I/O     (b)
    cnt_32k<5>                    2     FB3_4        (b)     (b)
    seg4<3>                       2     FB3_5   133  I/O     O
    cnt_32k<4>                    2     FB3_6        (b)     (b)
    cnt_32k<3>                    2     FB3_7        (b)     (b)
    cnt_32k<0>                    1     FB3_8        (b)     (b)
    cnt_32k<10>                   1     FB3_9        (b)     (b)
    cnt_32k<9>                    1     FB3_10       (b)     (b)
    cnt_32k<8>                    1     FB3_11       (b)     (b)
    cnt_32k<7>                    1     FB3_12       (b)     (b)
    cnt_32k<6>                    1     FB3_13       (b)     (b)
    cnt_32k<1>                    2     FB3_14  132  I/O     (b)
    cnt_32k<2>                    1     FB3_15       (b)     (b)
    seg4<2>                       3     FB3_16  131  I/O     O

    Signals Used by Logic in Function Block
      1: clk32k             7: cnt_32k<4>        13: rx_data
      2: cnt_32k<0>         8: cnt_32k<5>        14: u3/curr<0>
      3: cnt_32k<10>        9: cnt_32k<6>        15: u3/curr<1>
      4: cnt_32k<1>        10: cnt_32k<7>        16: u3/curr<2>
      5: cnt_32k<2>        11: cnt_32k<8>        17: u3/curr<3>
      6: cnt_32k<3>        12: cnt_32k<9>

    Signal                     1         2         3         4 FB
    Name             0----+----0----+----0----+----0----+----0 Inputs
    u1/rxd1           X...........X........................... 2
    seg4<4>           .............XXXX....................... 4
    clk32k            XXXXXXXXXXXX............................ 12
    cnt_32k<5>        .XXXXXXXXXXX............................ 11
    seg4<3>           .............XXXX....................... 4
    cnt_32k<4>        .XXXXXXXXXXX............................ 11
    cnt_32k<3>        .XXXXXXXXXXX............................ 11
    cnt_32k<0>        .XXXXXXXXXXX............................ 11
    cnt_32k<10>       .X.XXXXXXXXX............................ 10
    cnt_32k<9>        .X.XXXXXXXX............................. 9
    cnt_32k<8>        .X.XXXXXXX.............................. 8
    cnt_32k<7>        .X.XXXXXX............................... 7
    cnt_32k<6>        .X.XXXXX................................ 6
    cnt_32k<1>        .XXXXXXXXXXX............................ 11
    cnt_32k<2>        .X.X.................................... 2
    seg4<2>           .............XXXX....................... 4
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    *********************************** FB4  ***********************************
    This function block is part of I/O Bank number:               2
    Number of function block inputs used/remaining:               26/14
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   56/0
    Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
    Name                          Pt            No.  Type    Use
    N_PZ_929                      2     FB4_1   11   I/O     (b)
    N_PZ_1022                     2     FB4_2   12   I/O     (b)
    Mmult_bin_deg_mult0000__or0028
                                  5     FB4_3   13   I/O     (b)
    u4/XLXN_37                    2     FB4_4   14   I/O     (b)
    digit4<0>                     1     FB4_5   15   I/O     O
    digit4<1>                     1     FB4_6   16   I/O     O
    u4/XLXI_47/S0_or000011        1     FB4_7        (b)     (b)
    u4/XLXN_36                    2     FB4_8        (b)     (b)
    u4/XLXI_22/S1_or00006         1     FB4_9        (b)     (b)
    u4/XLXN_38                    5     FB4_10       (b)     (b)
    u3/curr<0>                    14    FB4_11       (b)     (b)
    digit4<2>                     1     FB4_12  17   I/O     O
    u3/curr<1>                    9     FB4_13       (b)     (b)
    digit4<3>                     1     FB4_14  18   I/O     O
    u3/curr<2>                    8     FB4_15       (b)     (b)
    u3/curr<3>                    5     FB4_16       (b)     (b)

    Signals Used by Logic in Function Block
      1: Mmult_bin_deg_mult0000_Mxor__index0020  10: bin_deg<1>              19: u4/XLXN_34
      2: Mmult_bin_deg_mult0000_Mxor__index0029  11: rx_out<0>               20: u4/XLXN_35
      3: Mmult_bin_deg_mult0000__or00213         12: rx_out<1>               21: u4/XLXN_36
      4: N_PZ_1022                               13: rx_out<7>               22: u4/XLXN_37
      5: N_PZ_624                                14: u3/cd<0>                23: u4/XLXN_38
      6: N_PZ_641                                15: u3/cd<1>                24: u4/XLXN_41
      7: N_PZ_666                                16: u4/XLXI_22/S1_or00006   25: u4/XLXN_83
      8: N_PZ_689                                17: u4/XLXI_47/S0_or000011  26: u4/XLXN_94
      9: N_PZ_929                                18: u4/XLXN_33

    Signal                     1         2         3         4 FB
    Name             0----+----0----+----0----+----0----+----0 Inputs
    N_PZ_929          X.X........X............................ 3
    N_PZ_1022         ....X.......X...........XX.............. 4
    Mmult_bin_deg_mult0000__or0028
                      XXX....X..XX............................ 6
    u4/XLXN_37        ...X..X........XX......X................ 5
    digit4<0>         .............XX......................... 2
    digit4<1>         .............XX......................... 2
    u4/XLXI_47/S0_or000011
                      ....X.X.....X...........XX.............. 5
    u4/XLXN_36        ...XX.X.....X...X......XXX.............. 8
    u4/XLXI_22/S1_or00006
                      ....X.X.....X...X......XXX.............. 7
    u4/XLXN_38        ....X.X.....X..XX...XX.XXX.............. 10
    u3/curr<0>        X.X..X.XXXXX.XX..XXXXXX................. 16
    digit4<2>         .............XX......................... 2
    u3/curr<1>        ....XXX..X..XXX.XXXXXXX.XX.............. 16
    digit4<3>         .............XX......................... 2
    u3/curr<2>        ....XXX..X..XXX..XXXXXX.XX.............. 15
    u3/curr<3>        .....X...X...XX..XXXXXX................. 10
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    *********************************** FB5  ***********************************
    This function block is part of I/O Bank number:               1
    Number of function block inputs used/remaining:               22/18
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   28/28
    Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
    Name                          Pt            No.  Type    Use
    u1/regrx<13>                  2     FB5_1        (b)     (b)    +
    u1/regrx<23>                  2     FB5_2   33   I/O     (b)    +
    u1/regrx<12>                  2     FB5_3        (b)     (b)    +
    rx_out<4>                     3     FB5_4   32   GCK/I/O O      +
    u1/regrx<22>                  2     FB5_5   31   I/O     (b)    +
    rx_out<5>                     3     FB5_6   30   GCK/I/O O      +
    u1/regrx<11>                  2     FB5_7        (b)     (b)    +
    N_PZ_970                      1     FB5_8        (b)     (b)
    u1/regrx<9>                   2     FB5_9        (b)     (b)    +
    u1/regrx<29>                  2     FB5_10       (b)     (b)    +
    u1/regrx<19>                  2     FB5_11       (b)     (b)    +
    u1/rx_out_or000044            8     FB5_12       (b)     (b)
    u1/rx_out_or000047            8     FB5_13       (b)     (b)
    u1/regrx<21>                  2     FB5_14  28   I/O     (b)    +
    u1/regrx<15>                  2     FB5_15       (b)     (b)    +
    u1/regrx<14>                  2     FB5_16       (b)     (b)    +

    Signals Used by Logic in Function Block
      1: N_PZ_750           9: u1/regrx<15>      16: u1/regrx<23>
      2: data_ready        10: u1/regrx<16>      17: u1/regrx<24>
      3: u1/regrx<0>       11: u1/regrx<17>      18: u1/regrx<25>
      4: u1/regrx<10>      12: u1/regrx<18>      19: u1/regrx<26>
      5: u1/regrx<11>      13: u1/regrx<20>      20: u1/regrx<27>
      6: u1/regrx<12>      14: u1/regrx<21>      21: u1/regrx<28>
      7: u1/regrx<13>      15: u1/regrx<22>      22: u1/regrx<30>
      8: u1/regrx<14>

    Signal                     1         2         3         4 FB
    Name             0----+----0----+----0----+----0----+----0 Inputs
    u1/regrx<13>      .X.....X................................ 2
    u1/regrx<23>      .X..............X....................... 2
    u1/regrx<12>      .X....X................................. 2
    rx_out<4>         XX......X............................... 3
    u1/regrx<22>      .X.............X........................ 2
    rx_out<5>         XX.......X.............................. 3
    u1/regrx<11>      .X...X.................................. 2
    N_PZ_970          .........X........X..................... 2
    u1/regrx<9>       .X.X.................................... 2
    u1/regrx<29>      .X...................X.................. 2
    u1/regrx<19>      .X..........X........................... 2
    u1/rx_out_or000044
                      ..XXXXXX....XXXXX....X.................. 12
    u1/rx_out_or000047
                      .....XXXXXXX..XXXXXXX................... 14
    u1/regrx<21>      .X............X......................... 2
    u1/regrx<15>      .X.......X.............................. 2
    u1/regrx<14>      .X......X............................... 2
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    *********************************** FB6  ***********************************
    This function block is part of I/O Bank number:               1
    Number of function block inputs used/remaining:               18/22
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   20/36
    Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
    Name                          Pt            No.  Type    Use
    u1/regrx<4>                   2     FB6_1   34   I/O     (b)    +
    rx_out<3>                     3     FB6_2   35   CDR/I/O O      +
    u1/regrx<35>                  2     FB6_3        (b)     (b)    +
    u1/regrx<3>                   2     FB6_4   38   GCK/I/O GCK    +
    u1/regrx<34>                  2     FB6_5        (b)     (b)    +
    u1/regrx<33>                  2     FB6_6        (b)     (b)    +
    u1/regrx<32>                  2     FB6_7        (b)     (b)    +
    u1/regrx<31>                  2     FB6_8        (b)     (b)    +
    u1/regrx<25>                  2     FB6_9        (b)     (b)    +
    u1/regrx<24>                  2     FB6_10       (b)     (b)    +
    N_PZ_1032                     1     FB6_11       (b)     (b)
    rx_out<1>                     3     FB6_12  39   DGE/I/O O      +
    u1/regrx<38>                  2     FB6_13  40   I/O     (b)    +
    u1/regrx<37>                  2     FB6_14  41   I/O     (b)    +
    rx_out<0>                     3     FB6_15  42   I/O     O      +
    u1/regrx<36>                  2     FB6_16  43   I/O     (b)    +

    Signals Used by Logic in Function Block
      1: N_PZ_750           7: u1/regrx<26>      13: u1/regrx<37>
      2: data_ready         8: u1/regrx<32>      14: u1/regrx<38>
      3: u1/regrx<11>       9: u1/regrx<33>      15: u1/regrx<39>
      4: u1/regrx<12>      10: u1/regrx<34>      16: u1/regrx<4>
      5: u1/regrx<14>      11: u1/regrx<35>      17: u1/regrx<5>
      6: u1/regrx<25>      12: u1/regrx<36>      18: u2/run

    Signal                     1         2         3         4 FB
    Name             0----+----0----+----0----+----0----+----0 Inputs
    u1/regrx<4>       .X..............X....................... 2
    rx_out<3>         XX..X................................... 3
    u1/regrx<35>      .X.........X............................ 2
    u1/regrx<3>       .X.............X........................ 2
    u1/regrx<34>      .X........X............................. 2
    u1/regrx<33>      .X.......X.............................. 2
    u1/regrx<32>      .X......X............................... 2
    u1/regrx<31>      .X.....X................................ 2
    u1/regrx<25>      .X....X................................. 2
    u1/regrx<24>      .X...X.................................. 2
    N_PZ_1032         .X...............X...................... 2
    rx_out<1>         XX.X.................................... 3
    u1/regrx<38>      .X............X......................... 2
    u1/regrx<37>      .X...........X.......................... 2
    rx_out<0>         XXX..................................... 3
    u1/regrx<36>      .X..........X........................... 2
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    *********************************** FB7  ***********************************
    This function block is part of I/O Bank number:               1
    Number of function block inputs used/remaining:               21/19
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   26/30
    Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
    Name                          Pt            No.  Type    Use
    u3/khertz_en                  1     FB7_1        (b)     (b)
    u3/khertz_count<4>            1     FB7_2        (b)     (b)
    u3/khertz_count<2>            1     FB7_3        (b)     (b)
    u3/khertz_count<1>            1     FB7_4        (b)     (b)
    rx_out<6>                     3     FB7_5   26   I/O     O      +
    u3/khertz_count<7>            7     FB7_6   25   I/O     (b)
    u1/regrx<8>                   2     FB7_7        (b)     (b)    +
    u1/regrx<7>                   2     FB7_8        (b)     (b)    +
    u1/regrx<6>                   2     FB7_9        (b)     (b)    +
    u1/regrx<5>                   2     FB7_10       (b)     (b)    +
    rx_out<7>                     3     FB7_11  24   I/O     O      +
    rx_out<2>                     3     FB7_12  23   I/O     O      +
    u3/khertz_count<9>            2     FB7_13  22   I/O     (b)
    u3/khertz_count<8>            2     FB7_14  21   I/O     (b)
    u3/khertz_count<0>            2     FB7_15  20   I/O     (b)
    u3/khertz_count<3>            2     FB7_16  19   I/O     (b)

    Signals Used by Logic in Function Block
      1: N_PZ_750           8: u1/regrx<7>         15: u3/khertz_count<4>
      2: N_PZ_936           9: u1/regrx<8>         16: u3/khertz_count<5>
      3: data_ready        10: u1/regrx<9>         17: u3/khertz_count<6>
      4: u1/regrx<13>      11: u3/khertz_count<0>  18: u3/khertz_count<7>
      5: u1/regrx<17>      12: u3/khertz_count<1>  19: u3/khertz_count<8>
      6: u1/regrx<18>      13: u3/khertz_count<2>  20: u3/khertz_count<9>
      7: u1/regrx<6>       14: u3/khertz_count<3>  21: u3/mhertz_en

    Signal                     1         2         3         4 FB
    Name             0----+----0----+----0----+----0----+----0 Inputs
    u3/khertz_en      ..........XXXXXXXXXXX................... 11
    u3/khertz_count<4>
                      ..........XXXX......X................... 5
    u3/khertz_count<2>
                      ..........XX........X................... 3
    u3/khertz_count<1>
                      ..........X.........X................... 2
    rx_out<6>         X.X.X................................... 3
    u3/khertz_count<7>
                      .X........XXXXXXXXXXX................... 12
    u1/regrx<8>       ..X......X.............................. 2
    u1/regrx<7>       ..X.....X............................... 2
    u1/regrx<6>       ..X....X................................ 2
    u1/regrx<5>       ..X...X................................. 2
    rx_out<7>         X.X..X.................................. 3
    rx_out<2>         X.XX.................................... 3
    u3/khertz_count<9>
                      .X........XXXXXXXXXXX................... 12
    u3/khertz_count<8>
                      .X........XXXXXXXXXXX................... 12
    u3/khertz_count<0>
                      ..........XXXXXXXXXXX................... 11
    u3/khertz_count<3>
                      ..........XXXXXXXXXXX................... 11
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    *********************************** FB8  ***********************************
    This function block is part of I/O Bank number:               1
    Number of function block inputs used/remaining:               37/3
    Number of function block control terms used/remaining:        3/1
    Number of PLA product terms used/remaining:                   54/2
    Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
    Name                          Pt            No.  Type    Use
    u2/forward_backward           17    FB8_1   44   I/O     (b)            +
    output_mot<0>                 2     FB8_2   45   I/O     O
    N_PZ_977                      1     FB8_3   46   I/O     (b)
    u2/sensor_set                 3     FB8_4        (b)     (b)    +   +
    output_mot<1>                 2     FB8_5   48   I/O     O
    N_PZ_1003                     1     FB8_6   49   I/O     (b)
    u2/cnt_reg<0>                 3     FB8_7        (b)     (b)    +   +
    u2/cnt_reg<1>                 4     FB8_8        (b)     (b)    +   +
    u2/run                        3     FB8_9        (b)     (b)    +
    u2/now_ST_FFd4                7     FB8_10       (b)     (b)    +
    output_mot<2>                 2     FB8_11  50   I/O     O
    N_PZ_967                      2     FB8_12  51   I/O     (b)
    output_mot<3>                 2     FB8_13  52   I/O     O
    u2/now_ST_FFd3                6     FB8_14       (b)     (b)    +
    u2/now_ST_FFd2                5     FB8_15       (b)     (b)    +
    u2/now_ST_FFd1                4     FB8_16       (b)     (b)    +

    Signals Used by Logic in Function Block
      1: N_PZ_1032         14: rx_out<5>                26: u2/cnt_reg<5>
      2: N_PZ_762          15: rx_out<6>                27: u2/cnt_reg<6>
      3: N_PZ_789          16: rx_out<7>                28: u2/cnt_reg<7>
      4: N_PZ_904          17: sensor_en                29: u2/forward_backward
      5: N_PZ_967          18: u2/SF17                  30: u2/forward_backward_mux000876
      6: N_PZ_971          19: u2/_mux0000              31: u2/now_ST_FFd1
      7: clk_div<13>       20: u2/cnt_catch_cmp_le0000  32: u2/now_ST_FFd2
      8: data_ready        21: u2/cnt_reg<0>            33: u2/now_ST_FFd3
      9: rx_out<0>         22: u2/cnt_reg<1>            34: u2/now_ST_FFd4
     10: rx_out<1>         23: u2/cnt_reg<2>            35: u2/run
     11: rx_out<2>         24: u2/cnt_reg<3>            36: u2/sensor_set
     12: rx_out<3>         25: u2/cnt_reg<4>            37: u2/sensor_set_cmp_ne0000
     13: rx_out<4>

    Signal                     1         2         3         4 FB
    Name             0----+----0----+----0----+----0----+----0 Inputs
    u2/forward_backward
                      .XXX.X.XXXXXXXXXXXXXXXXXXXXXXX.......... 27
    output_mot<0>     ..............................XXX.X..... 4
    N_PZ_977          X...................XX......X.......X... 5
    u2/sensor_set     X.....X.........X..................XX... 5
    output_mot<1>     ..............................XXX.X..... 4
    N_PZ_1003         X...................XX......X.......X... 5
    u2/cnt_reg<0>     X.....X.........X..................XX... 5
    u2/cnt_reg<1>     X.....X.........X...X.......X......XX... 7
    u2/run            ....X.X.........X.................XX.... 5
    u2/now_ST_FFd4    ....X.X.....................X.XXXX...... 7
    output_mot<2>     ...............................XXXX..... 4
    N_PZ_967          X...............X..................XX... 4
    output_mot<3>     ...............................XXXX..... 4
    u2/now_ST_FFd3    ....X.X.....................X.XXXX...... 7
    u2/now_ST_FFd2    ....X.X.....................X.XXXX...... 7
    u2/now_ST_FFd1    ....X.X.....................X.XXXX...... 7
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    *********************************** FB9  ***********************************
    This function block is part of I/O Bank number:               2
    Number of function block inputs used/remaining:               33/7
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   56/0
    Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
    Name                          Pt            No.  Type    Use
    (unused)                      0     FB9_1   112  I/O
    (unused)                      0     FB9_2   113  I/O
    Mmult_bin_deg_mult0000__or0017
                                  4     FB9_3        (b)     (b)
    (unused)                      0     FB9_4   114  I/O
    u2/cnt_catch_cmp_le0000       2     FB9_5        (b)     (b)
    (unused)                      0     FB9_6   115  I/O
    Mmult_bin_deg_mult0000_Mxor__index0016
                                  7     FB9_7        (b)     (b)
    Mmult_bin_deg_mult0000_Mxor__index0015
                                  12    FB9_8        (b)     (b)
    N_PZ_642                      3     FB9_9        (b)     (b)
    N_PZ_695                      2     FB9_10       (b)     (b)
    N_PZ_762                      7     FB9_11       (b)     (b)
    (unused)                      0     FB9_12  116  I/O
    (unused)                      0     FB9_13  117  I/O
    (unused)                      0     FB9_14  118  I/O
    (unused)                      0     FB9_15  119  I/O
    u2/Mcompar_forward_backward_cmp_lt0000_ALB20
                                  21    FB9_16       (b)     (b)

    Signals Used by Logic in Function Block
      1: Mmult_bin_deg_mult0000_Mxor__index0014  12: N_PZ_689          23: rx_out<7>
      2: Mmult_bin_deg_mult0000_Mxor__index0015  13: N_PZ_695          24: u2/Mcompar_forward_backward_cmp_lt0000_ALB20
      3: Mmult_bin_deg_mult0000_Mxor__index0016  14: N_PZ_904          25: u2/Msub__sub0000__or0006
      4: Mmult_bin_deg_mult0000_Mxor__index0020  15: N_PZ_907          26: u2/SF17
      5: Mmult_bin_deg_mult0000_Mxor__index0021  16: rx_out<0>         27: u2/_sub0000<3>
      6: Mmult_bin_deg_mult0000_Mxor__index0022  17: rx_out<1>         28: u2/_sub0000<5>
      7: Mmult_bin_deg_mult0000__or0014          18: rx_out<2>         29: u2/_sub0000<6>
      8: N_PZ_619                                19: rx_out<3>         30: u2/cnt_reg<0>
      9: N_PZ_621                                20: rx_out<4>         31: u2/cnt_reg<1>
     10: N_PZ_642                                21: rx_out<5>         32: u2/cnt_reg<2>
     11: N_PZ_680                                22: rx_out<6>         33: u2/cnt_reg<7>

    Signal                     1         2         3         4 FB
    Name             0----+----0----+----0----+----0----+----0 Inputs
    Mmult_bin_deg_mult0000__or0017
                      XXXXXXX..........XXX.................... 10
    u2/cnt_catch_cmp_le0000
                      ..................XXXXX................. 5
    Mmult_bin_deg_mult0000_Mxor__index0016
                      X...............XXXXXXX................. 8
    Mmult_bin_deg_mult0000_Mxor__index0015
                      X.X....XX..X..XXXXXXXXX................. 14
    N_PZ_642          ...............XX............XX......... 4
    N_PZ_695          .........X...X...X.............X........ 4
    N_PZ_762          .........XX..X........XXXXXXX...X....... 11
    u2/Mcompar_forward_backward_cmp_lt0000_ALB20
                      .........XX.X..XXX....X.XXXXXXXXX....... 16
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    *********************************** FB10 ***********************************
    This function block is part of I/O Bank number:               2
    Number of function block inputs used/remaining:               30/10
    Number of function block control terms used/remaining:        2/2
    Number of PLA product terms used/remaining:                   56/0
    Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
    Name                          Pt            No.  Type    Use
    (unused)                      0     FB10_1  111  I/O
    (unused)                      0     FB10_2  110  I/O
    (unused)                      0     FB10_3  107  I/O
    u2/SF17                       1     FB10_4  106  I/O     (b)
    N_PZ_789                      2     FB10_5  105  I/O     (b)
    u2/_sub0000<6>                6     FB10_6  104  I/O     (b)
    u2/cnt_reg<5>                 6     FB10_7       (b)     (b)    +   +
    u2/cnt_reg<3>                 6     FB10_8       (b)     (b)    +   +
    u2/cnt_reg<7>                 5     FB10_9       (b)     (b)    +   +
    u2/cnt_reg<6>                 5     FB10_10      (b)     (b)    +   +
    u2/cnt_reg<4>                 5     FB10_11      (b)     (b)    +   +
    u2/Msub__sub0000__or0006      3     FB10_12 103  I/O     (b)
    u2/_mux0000                   5     FB10_13      (b)     (b)
    u2/forward_backward_mux000876 4     FB10_14 102  I/O     (b)
    u2/sensor_set_cmp_ne0000      16    FB10_15      (b)     (b)
    u2/cnt_reg<2>                 3     FB10_16 101  I/O     (b)    +   +

    Signals Used by Logic in Function Block
      1: N_PZ_1003         11: u2/Msub__sub0000__or0006  21: u2/cnt_catch<7>
      2: N_PZ_643          12: u2/SF17                   22: u2/cnt_reg<0>
      3: N_PZ_762          13: u2/_sub0000<5>            23: u2/cnt_reg<1>
      4: N_PZ_789          14: u2/cnt_catch<0>           24: u2/cnt_reg<2>
      5: N_PZ_977          15: u2/cnt_catch<1>           25: u2/cnt_reg<3>
      6: clk_div<13>       16: u2/cnt_catch<2>           26: u2/cnt_reg<4>
      7: rx_out<5>         17: u2/cnt_catch<3>           27: u2/cnt_reg<5>
      8: rx_out<6>         18: u2/cnt_catch<4>           28: u2/cnt_reg<6>
      9: rx_out<7>         19: u2/cnt_catch<5>           29: u2/cnt_reg<7>
     10: sensor_en         20: u2/cnt_catch<6>           30: u2/sensor_set

    Signal                     1         2         3         4 FB
    Name             0----+----0----+----0----+----0----+----0 Inputs
    u2/SF17           ........X...................X........... 2
    N_PZ_789          ......XX..................XX............ 4
    u2/_sub0000<6>    .X....XX..X.X.............XX............ 7
    u2/cnt_reg<5>     X...XX...X.............XXXXXXX.......... 11
    u2/cnt_reg<3>     X...XX...X.............XXXXXXX.......... 11
    u2/cnt_reg<7>     X...XX...X.............XXXXXXX.......... 11
    u2/cnt_reg<6>     X...XX...X.............XXXXXXX.......... 11
    u2/cnt_reg<4>     X...XX...X.............XXXXXXX.......... 11
    u2/Msub__sub0000__or0006
                      .X.X..XX....X.............XX............ 7
    u2/_mux0000       .............XXXXXXXX................... 8
    u2/forward_backward_mux000876
                      .XXX..XXX..X..............XXX........... 10
    u2/sensor_set_cmp_ne0000
                      .............XXXXXXXXXXXXXXXX........... 16
    u2/cnt_reg<2>     X...XX...X...................X.......... 5
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    *********************************** FB11 ***********************************
    This function block is part of I/O Bank number:               2
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   29/27
    Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
    Name                          Pt            No.  Type    Use
    N_PZ_619                      2     FB11_1       (b)     (b)
    N_PZ_621                      1     FB11_2       (b)     (b)
    N_PZ_936                      1     FB11_3       (b)     (b)
    u3/khertz_count<6>            6     FB11_4       (b)     (b)
    (unused)                      0     FB11_5  120  I/O
    (unused)                      0     FB11_6  121  I/O
    u3/khertz_count<5>            5     FB11_7       (b)     (b)
    clk_div<13>                   1     FB11_8       (b)     (b)
    clk_div<12>                   1     FB11_9       (b)     (b)
    clk_div<11>                   1     FB11_10      (b)     (b)
    (unused)                      0     FB11_11 124  I/O
    (unused)                      0     FB11_12 125  I/O     I
    seg4<0>                       1     FB11_13 126  I/O     O
    N_PZ_911                      1     FB11_14 128  I/O     (b)
    seg4<1>                       2     FB11_15 129  I/O     O
    N_PZ_689                      7     FB11_16 130  I/O     (b)

    Signals Used by Logic in Function Block
      1: Mmult_bin_deg_mult0000_Mxor__index0031  14: clk_div<6>        27: u3/dp
      2: N_PZ_619                                15: clk_div<7>        28: u3/khertz_count<0>
      3: N_PZ_621                                16: clk_div<8>        29: u3/khertz_count<1>
      4: N_PZ_936                                17: clk_div<9>        30: u3/khertz_count<2>
      5: clk_div<0>                              18: rx_out<2>         31: u3/khertz_count<3>
      6: clk_div<10>                             19: rx_out<3>         32: u3/khertz_count<4>
      7: clk_div<11>                             20: rx_out<4>         33: u3/khertz_count<5>
      8: clk_div<12>                             21: rx_out<5>         34: u3/khertz_count<6>
      9: clk_div<1>                              22: rx_out<6>         35: u3/khertz_count<7>
     10: clk_div<2>                              23: u3/curr<0>        36: u3/khertz_count<8>
     11: clk_div<3>                              24: u3/curr<1>        37: u3/khertz_count<9>
     12: clk_div<4>                              25: u3/curr<2>        38: u3/mhertz_en
     13: clk_div<5>                              26: u3/curr<3>

    Signal                     1         2         3         4 FB
    Name             0----+----0----+----0----+----0----+----0 Inputs
    N_PZ_619          .................X..XX.................. 3
    N_PZ_621          .................X..X................... 2
    N_PZ_936          ...........................XXX.X........ 4
    u3/khertz_count<6>
                      ...X.......................XXXXXXXXXXX.. 12
    u3/khertz_count<5>
                      ...X.......................XXXXXXXXXXX.. 12
    clk_div<13>       ....XXXXXXXXXXXXX....................... 13
    clk_div<12>       ....XXX.XXXXXXXXX....................... 12
    clk_div<11>       ....XX..XXXXXXXXX....................... 11
    seg4<0>           ..........................X............. 1
    N_PZ_911          X..................X.................... 2
    seg4<1>           ......................XXXX.............. 4
    N_PZ_689          .XX..............XXXXX.................. 7
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    *********************************** FB12 ***********************************
    This function block is part of I/O Bank number:               2
    Number of function block inputs used/remaining:               23/17
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   56/0
    Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
    Name                          Pt            No.  Type    Use
    (unused)                      0     FB12_1       (b)
    (unused)                      0     FB12_2  100  I/O
    (unused)                      0     FB12_3       (b)
    (unused)                      0     FB12_4       (b)
    N_PZ_653                      1     FB12_5       (b)     (b)
    Mmult_bin_deg_mult0000_Mxor__index0021
                                  8     FB12_6       (b)     (b)
    Mmult_bin_deg_mult0000_Mxor__index0031
                                  4     FB12_7       (b)     (b)
    bin_deg<1>                    6     FB12_8       (b)     (b)
    Mmult_bin_deg_mult0000__or00213
                                  6     FB12_9       (b)     (b)
    Mmult_bin_deg_mult0000__or0014
                                  15    FB12_10      (b)     (b)
    (unused)                      0     FB12_11 98   I/O
    (unused)                      0     FB12_12 97   I/O
    (unused)                      0     FB12_13 96   I/O
    (unused)                      0     FB12_14 95   I/O
    (unused)                      0     FB12_15 94   I/O
    Mmult_bin_deg_mult0000_Mxor__index0014
                                  16    FB12_16      (b)     (b)

    Signals Used by Logic in Function Block
      1: Mmult_bin_deg_mult0000_Mxor__index0014   9: Mmult_bin_deg_mult0000__or0028  17: rx_out<2>
      2: Mmult_bin_deg_mult0000_Mxor__index0015  10: N_PZ_619                        18: rx_out<3>
      3: Mmult_bin_deg_mult0000_Mxor__index0020  11: N_PZ_621                        19: rx_out<4>
      4: Mmult_bin_deg_mult0000_Mxor__index0029  12: N_PZ_632                        20: rx_out<5>
      5: Mmult_bin_deg_mult0000__or0014          13: N_PZ_689                        21: rx_out<6>
      6: Mmult_bin_deg_mult0000__or0017          14: N_PZ_911                        22: rx_out<7>
      7: Mmult_bin_deg_mult0000__or00213         15: rx_out<0>                       23: u2/cnt_catch_cmp_le0000
      8: Mmult_bin_deg_mult0000__or0023          16: rx_out<1>

    Signal                     1         2         3         4 FB
    Name             0----+----0----+----0----+----0----+----0 Inputs
    N_PZ_653          X....X.X.....X.......................... 4
    Mmult_bin_deg_mult0000_Mxor__index0021
                      XXX.X...........XX...................... 6
    Mmult_bin_deg_mult0000_Mxor__index0031
                      X..........X.......XXX.................. 5
    bin_deg<1>        ..XX..X.X...X.XX........................ 7
    Mmult_bin_deg_mult0000__or00213
                      ..X......XX.X.XX.XX.X................... 9
    Mmult_bin_deg_mult0000__or0014
                      .........XX.X.XXXXXXX................... 10
    Mmult_bin_deg_mult0000_Mxor__index0014
                      .........XX.X.XX.XXXXXX................. 11
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    *********************************** FB13 ***********************************
    This function block is part of I/O Bank number:               1
    Number of function block inputs used/remaining:               23/17
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   56/0
    Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
    Name                          Pt            No.  Type    Use
    (unused)                      0     FB13_1  75   I/O
    (unused)                      0     FB13_2  76   I/O
    (unused)                      0     FB13_3  77   I/O
    N_PZ_615                      2     FB13_4       (b)     (b)
    (unused)                      0     FB13_5  78   I/O
    Mmult_bin_deg_mult0000__or0031
                                  3     FB13_6  79   I/O     (b)
    N_PZ_604                      3     FB13_7       (b)     (b)
    N_PZ_624                      2     FB13_8       (b)     (b)
    u4/XLXN_81                    9     FB13_9       (b)     (b)
    u4/XLXI_46/S1_or00007         6     FB13_10      (b)     (b)
    u4/XLXN_83                    3     FB13_11      (b)     (b)
    u4/XLXN_27                    4     FB13_12 80   I/O     (b)
    N_PZ_666                      3     FB13_13 81   I/O     (b)
    N_PZ_632                      3     FB13_14 82   I/O     (b)
    Mmult_bin_deg_mult0000_Mxor__index0033
                                  8     FB13_15      (b)     (b)
    Mmult_bin_deg_mult0000_Mxor__index0032
                                  12    FB13_16      (b)     (b)

    Signals Used by Logic in Function Block
      1: Mmult_bin_deg_mult0000_Mxor__index0014   9: N_PZ_615          17: rx_out<4>
      2: Mmult_bin_deg_mult0000_Mxor__index0031  10: N_PZ_624          18: rx_out<5>
      3: Mmult_bin_deg_mult0000_Mxor__index0032  11: N_PZ_653          19: rx_out<6>
      4: Mmult_bin_deg_mult0000_Mxor__index0033  12: N_PZ_761          20: rx_out<7>
      5: Mmult_bin_deg_mult0000__or0017          13: N_PZ_911          21: u4/XLXI_46/S1_or00007
      6: Mmult_bin_deg_mult0000__or0023          14: bin_deg<3>        22: u4/XLXN_81
      7: Mmult_bin_deg_mult0000__or0031          15: bin_deg<4>        23: u4/XLXN_83
      8: N_PZ_604                                16: rx_out<3>

    Signal                     1         2         3         4 FB
    Name             0----+----0----+----0----+----0----+----0 Inputs
    N_PZ_615          ....XX......X........................... 3
    Mmult_bin_deg_mult0000__or0031
                      .XX........X.XXXX....................... 7
    N_PZ_604          ...X..X..........X...................... 3
    N_PZ_624          ...X..X...X......XX..................... 5
    u4/XLXN_81        ...X..XXXX.......XXXX................... 9
    u4/XLXI_46/S1_or00007
                      ...X..XXXX.......XXX.................... 8
    u4/XLXN_83        ...X..XX.XX......XXX.................... 8
    u4/XLXN_27        .......X......X.....XXX................. 5
    N_PZ_666          .......X............XXX................. 4
    N_PZ_632          ....XX..........X....................... 3
    Mmult_bin_deg_mult0000_Mxor__index0033
                      ....XX..X.X.X....XXX.................... 8
    Mmult_bin_deg_mult0000_Mxor__index0032
                      X..XXX..X.X.X....XXX.................... 10
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    *********************************** FB14 ***********************************
    This function block is part of I/O Bank number:               1
    Number of function block inputs used/remaining:               27/13
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   56/0
    Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
    Name                          Pt            No.  Type    Use
    u2/Msub__sub0000__or0003      2     FB14_1  74   I/O     (b)
    u2/_sub0000<3>                3     FB14_2  71   I/O     (b)
    N_PZ_643                      2     FB14_3  70   I/O     (b)
    N_PZ_680                      3     FB14_4  69   I/O     (b)
    N_PZ_904                      2     FB14_5       (b)     (b)
    N_PZ_971                      3     FB14_6  68   I/O     (b)
    N_PZ_761                      2     FB14_7       (b)     (b)
    N_PZ_606                      3     FB14_8       (b)     (b)
    Mmult_bin_deg_mult0000_Mxor__index0029
                                  3     FB14_9       (b)     (b)
    Mmult_bin_deg_mult0000__or0023
                                  3     FB14_10      (b)     (b)
    Mmult_bin_deg_mult0000_Mxor__index0030
                                  8     FB14_11      (b)     (b)
    Mmult_bin_deg_mult0000_Mxor__index0020
                                  3     FB14_12      (b)     (b)
    bin_deg<4>                    8     FB14_13 66   I/O     (b)
    bin_deg<3>                    3     FB14_14 64   I/O     (b)
    Mmult_bin_deg_mult0000_Mxor__index0022
                                  6     FB14_15      (b)     (b)
    u4/XLXN_33                    2     FB14_16 61   I/O     (b)

    Signals Used by Logic in Function Block
      1: Mmult_bin_deg_mult0000_Mxor__index0014  10: Mmult_bin_deg_mult0000__or0014  19: bin_deg<3>
      2: Mmult_bin_deg_mult0000_Mxor__index0015  11: Mmult_bin_deg_mult0000__or0028  20: rx_out<2>
      3: Mmult_bin_deg_mult0000_Mxor__index0020  12: N_PZ_606                        21: rx_out<3>
      4: Mmult_bin_deg_mult0000_Mxor__index0021  13: N_PZ_641                        22: rx_out<4>
      5: Mmult_bin_deg_mult0000_Mxor__index0022  14: N_PZ_680                        23: u2/Msub__sub0000__or0003
      6: Mmult_bin_deg_mult0000_Mxor__index0029  15: N_PZ_695                        24: u2/_sub0000<3>
      7: Mmult_bin_deg_mult0000_Mxor__index0030  16: N_PZ_761                        25: u2/cnt_reg<2>
      8: Mmult_bin_deg_mult0000_Mxor__index0031  17: N_PZ_907                        26: u2/cnt_reg<3>
      9: Mmult_bin_deg_mult0000_Mxor__index0032  18: N_PZ_929                        27: u2/cnt_reg<4>

    Signal                     1         2         3         4 FB
    Name             0----+----0----+----0----+----0----+----0 Inputs
    u2/Msub__sub0000__or0003
                      ..............X.....X..X.X.............. 4
    u2/_sub0000<3>    ..............X.....X....X.............. 3
    N_PZ_643          .............X.......XX...X............. 4
    N_PZ_680          .....................XX...X............. 3
    N_PZ_904          ...................X....X............... 2
    N_PZ_971          ....................XX...XX............. 4
    N_PZ_761          ......X...XX.......X.................... 4
    N_PZ_606          ......X...X........X.................... 3
    Mmult_bin_deg_mult0000_Mxor__index0029
                      ...X.............X.X.................... 3
    Mmult_bin_deg_mult0000__or0023
                      ...XXXX..........X.XX................... 7
    Mmult_bin_deg_mult0000_Mxor__index0030
                      ...XXX...........X.XX................... 6
    Mmult_bin_deg_mult0000_Mxor__index0020
                      X........X.........X.................... 3
    bin_deg<4>        .......XX......X..X.XX.................. 6
    bin_deg<3>        .......X.......X....X................... 3
    Mmult_bin_deg_mult0000_Mxor__index0022
                      XXXX.....X......X..XX................... 8
    u4/XLXN_33        ...........XX........................... 2
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    *********************************** FB15 ***********************************
    This function block is part of I/O Bank number:               1
    Number of function block inputs used/remaining:               19/21
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   33/23
    Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
    Name                          Pt            No.  Type    Use
    N_PZ_907                      2     FB15_1       (b)     (b)
    u1/rxd2                       2     FB15_2  83   I/O     (b)
    u2/cnt_catch<7>               3     FB15_3       (b)     (b)    +
    u2/cnt_catch<6>               3     FB15_4       (b)     (b)    +
    u2/cnt_catch<5>               3     FB15_5       (b)     (b)    +
    u2/cnt_catch<4>               3     FB15_6       (b)     (b)    +
    u2/cnt_catch<3>               3     FB15_7       (b)     (b)    +
    u2/cnt_catch<2>               3     FB15_8       (b)     (b)    +
    u2/cnt_catch<1>               3     FB15_9       (b)     (b)    +
    u2/cnt_catch<0>               3     FB15_10      (b)     (b)    +
    u1/clkdiv<0>                  2     FB15_11 85   I/O     (b)
    u1/clkdiv<1>                  3     FB15_12 86   I/O     (b)
    u1/clkdiv<2>                  3     FB15_13 87   I/O     (b)
    u1/regrx<39>                  1     FB15_14 88   I/O     I      +
    data_ready                    3     FB15_15 91   I/O     (b)
    u2/_sub0000<5>                3     FB15_16 92   I/O     (b)

    Signals Used by Logic in Function Block
      1: Mmult_bin_deg_mult0000_Mxor__index0016   8: rx_out<3>         14: u1/clkdiv<1>
      2: N_PZ_643                                 9: rx_out<4>         15: u1/clkdiv<2>
      3: clk32k                                  10: rx_out<5>         16: u1/edge
      4: data_ready                              11: rx_out<6>         17: u1/rxd1
      5: rx_out<0>                               12: rx_out<7>         18: u2/cnt_catch_cmp_le0000
      6: rx_out<1>                               13: u1/clkdiv<0>      19: u2/cnt_reg<5>
      7: rx_out<2>

    Signal                     1         2         3         4 FB
    Name             0----+----0----+----0----+----0----+----0 Inputs
    N_PZ_907          X.......X............................... 2
    u1/rxd2           ..X.............X....................... 2
    u2/cnt_catch<7>   ...X.......X.....X...................... 3
    u2/cnt_catch<6>   ...X......X......X...................... 3
    u2/cnt_catch<5>   ...X.....X.......X...................... 3
    u2/cnt_catch<4>   ...X....X........X...................... 3
    u2/cnt_catch<3>   ...X...X.........X...................... 3
    u2/cnt_catch<2>   ...X..X..........X...................... 3
    u2/cnt_catch<1>   ...X.X...........X...................... 3
    u2/cnt_catch<0>   ...XX............X...................... 3
    u1/clkdiv<0>      ..X.........X..X........................ 3
    u1/clkdiv<1>      ..X.........XX.X........................ 4
    u1/clkdiv<2>      ..X.........XXXX........................ 5
    data_ready        ..XX........XXXX........................ 6
    u2/_sub0000<5>    .X.......X........X..................... 3
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    *********************************** FB16 ***********************************
    This function block is part of I/O Bank number:               1
    Number of function block inputs used/remaining:               17/23
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   32/24
    Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
    Name                          Pt            No.  Type    Use
    (unused)                      0     FB16_1       (b)
    u1/edge                       3     FB16_2       (b)     (b)    +
    u4/XLXN_34                    4     FB16_3       (b)     (b)
    N_PZ_641                      4     FB16_4       (b)     (b)
    (unused)                      0     FB16_5  60   I/O
    (unused)                      0     FB16_6  59   I/O
    u4/XLXN_35                    4     FB16_7       (b)     (b)
    u4/XLXN_41                    3     FB16_8       (b)     (b)
    u4/XLXN_29                    4     FB16_9       (b)     (b)
    u4/XLXN_94                    5     FB16_10      (b)     (b)
    (unused)                      0     FB16_11 58   I/O
    (unused)                      0     FB16_12 57   I/O
    (unused)                      0     FB16_13 56   I/O
    u4/XLXN_28                    6     FB16_14      (b)     (b)
    (unused)                      0     FB16_15 54   I/O
    (unused)                      0     FB16_16 53   I/O

    Signals Used by Logic in Function Block
      1: N_PZ_604           7: u1/rxd1                13: u4/XLXN_35
      2: N_PZ_606           8: u1/rxd2                14: u4/XLXN_41
      3: N_PZ_666           9: u4/XLXI_46/S1_or00007  15: u4/XLXN_81
      4: bin_deg<3>        10: u4/XLXN_27             16: u4/XLXN_83
      5: bin_deg<4>        11: u4/XLXN_28             17: u4/XLXN_94
      6: clk32k            12: u4/XLXN_29

    Signal                     1         2         3         4 FB
    Name             0----+----0----+----0----+----0----+----0 Inputs
    u1/edge           .....XXX................................ 3
    u4/XLXN_34        .X.X.....XXXXX.......................... 7
    N_PZ_641          .X.X.....XXXXX.......................... 7
    u4/XLXN_35        .X.X.....XXX............................ 5
    u4/XLXN_41        ...X.....XXX............................ 4
    u4/XLXN_29        X.X.X....X....XXX....................... 7
    u4/XLXN_94        X.X.X...XX....XX........................ 7
    u4/XLXN_28        X.X.X...XX....XX........................ 7
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    *******************************  Equations  ********************************

    ********** Mapped Logic **********

    Mmult_bin_deg_mult0000_Mxor__index0014 <= ((u2/cnt_catch_cmp_le0000 AND rx_out(4) AND NOT N_PZ_621)
    	OR (u2/cnt_catch_cmp_le0000 AND NOT rx_out(4) AND N_PZ_621)
    	OR (u2/cnt_catch_cmp_le0000 AND NOT rx_out(4) AND rx_out(1) AND
    	NOT N_PZ_689)
    	OR (rx_out(6) AND NOT rx_out(7) AND NOT rx_out(4) AND N_PZ_689)
    	OR (NOT rx_out(6) AND rx_out(7) AND rx_out(3) AND NOT rx_out(4))
    	OR (NOT rx_out(6) AND NOT rx_out(7) AND rx_out(3) AND rx_out(4))
    	OR (rx_out(7) AND NOT rx_out(3) AND rx_out(4) AND NOT N_PZ_619)
    	OR (rx_out(7) AND NOT rx_out(4) AND NOT rx_out(5) AND N_PZ_619)
    	OR (rx_out(7) AND NOT rx_out(4) AND rx_out(0) AND N_PZ_619)
    	OR (NOT rx_out(7) AND NOT rx_out(3) AND NOT rx_out(4) AND NOT N_PZ_619)
    	OR (NOT rx_out(7) AND rx_out(4) AND NOT N_PZ_689 AND N_PZ_621)
    	OR (rx_out(6) AND NOT rx_out(7) AND NOT rx_out(4) AND NOT rx_out(1) AND
    	NOT N_PZ_621)
    	OR (rx_out(7) AND NOT rx_out(3) AND rx_out(4) AND NOT rx_out(1) AND
    	NOT N_PZ_621)
    	OR (NOT rx_out(7) AND rx_out(4) AND rx_out(0) AND rx_out(1) AND
    	N_PZ_619)
    	OR (rx_out(7) AND NOT rx_out(0) AND rx_out(1) AND NOT N_PZ_689 AND
    	N_PZ_619 AND NOT N_PZ_621)
    	OR (NOT rx_out(7) AND NOT rx_out(3) AND NOT rx_out(4) AND rx_out(5) AND
    	NOT rx_out(0) AND NOT rx_out(1)));

    Mmult_bin_deg_mult0000_Mxor__index0015 <= ((rx_out(6) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0016)
    	OR (rx_out(7) AND NOT rx_out(5) AND
    	Mmult_bin_deg_mult0000_Mxor__index0014)
    	OR (NOT rx_out(7) AND rx_out(4) AND rx_out(5))
    	OR (NOT rx_out(7) AND rx_out(3) AND rx_out(5) AND N_PZ_907)
    	OR (NOT rx_out(7) AND rx_out(5) AND rx_out(0) AND N_PZ_619)
    	OR (NOT rx_out(7) AND rx_out(5) AND rx_out(1) AND N_PZ_619)
    	OR (rx_out(3) AND rx_out(5) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0016 AND NOT N_PZ_907)
    	OR (NOT rx_out(7) AND rx_out(3) AND rx_out(2) AND rx_out(1) AND
    	NOT N_PZ_621)
    	OR (NOT rx_out(7) AND rx_out(4) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND N_PZ_689 AND N_PZ_619)
    	OR (NOT rx_out(7) AND rx_out(4) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND NOT N_PZ_689 AND N_PZ_621)
    	OR (rx_out(4) AND rx_out(5) AND rx_out(0) AND rx_out(1) AND
    	N_PZ_619)
    	OR (NOT rx_out(7) AND rx_out(4) AND rx_out(0) AND rx_out(1) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND N_PZ_619));

    Mmult_bin_deg_mult0000_Mxor__index0016 <= rx_out(6)
    	XOR ((rx_out(7) AND NOT rx_out(5) AND
    	Mmult_bin_deg_mult0000_Mxor__index0014)
    	OR (rx_out(6) AND NOT rx_out(4) AND NOT rx_out(5) AND
    	Mmult_bin_deg_mult0000_Mxor__index0014)
    	OR (rx_out(6) AND rx_out(7) AND NOT rx_out(3) AND NOT rx_out(4) AND
    	NOT rx_out(5))
    	OR (rx_out(6) AND NOT rx_out(3) AND NOT rx_out(5) AND NOT rx_out(2) AND
    	Mmult_bin_deg_mult0000_Mxor__index0014)
    	OR (rx_out(6) AND NOT rx_out(3) AND NOT rx_out(5) AND NOT rx_out(1) AND
    	Mmult_bin_deg_mult0000_Mxor__index0014)
    	OR (rx_out(6) AND rx_out(7) AND NOT rx_out(4) AND NOT rx_out(5) AND
    	NOT rx_out(2) AND NOT rx_out(1)));

    Mmult_bin_deg_mult0000_Mxor__index0020 <= rx_out(2)
    	XOR ((Mmult_bin_deg_mult0000_Mxor__index0014 AND
    	NOT Mmult_bin_deg_mult0000__or0014)
    	OR (NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND
    	Mmult_bin_deg_mult0000__or0014));

    Mmult_bin_deg_mult0000_Mxor__index0021 <= ((rx_out(3) AND rx_out(2) AND
    	Mmult_bin_deg_mult0000__or0014 AND Mmult_bin_deg_mult0000_Mxor__index0015)
    	OR (rx_out(3) AND NOT rx_out(2) AND
    	Mmult_bin_deg_mult0000_Mxor__index0020 AND NOT Mmult_bin_deg_mult0000_Mxor__index0015)
    	OR (rx_out(3) AND
    	Mmult_bin_deg_mult0000_Mxor__index0014 AND NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND
    	Mmult_bin_deg_mult0000_Mxor__index0015)
    	OR (rx_out(3) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND NOT Mmult_bin_deg_mult0000__or0014 AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0015)
    	OR (NOT rx_out(3) AND rx_out(2) AND
    	Mmult_bin_deg_mult0000__or0014 AND NOT Mmult_bin_deg_mult0000_Mxor__index0015)
    	OR (NOT rx_out(3) AND NOT rx_out(2) AND
    	Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000_Mxor__index0015)
    	OR (NOT rx_out(3) AND
    	Mmult_bin_deg_mult0000_Mxor__index0014 AND NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0015)
    	OR (NOT rx_out(3) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND NOT Mmult_bin_deg_mult0000__or0014 AND
    	Mmult_bin_deg_mult0000_Mxor__index0015));

    Mmult_bin_deg_mult0000_Mxor__index0022 <= ((rx_out(3) AND
    	Mmult_bin_deg_mult0000_Mxor__index0015 AND N_PZ_907)
    	OR (NOT rx_out(3) AND NOT N_PZ_907 AND
    	Mmult_bin_deg_mult0000_Mxor__index0021)
    	OR (rx_out(2) AND Mmult_bin_deg_mult0000__or0014 AND
    	N_PZ_907 AND NOT Mmult_bin_deg_mult0000_Mxor__index0021)
    	OR (NOT rx_out(2) AND
    	Mmult_bin_deg_mult0000_Mxor__index0020 AND NOT Mmult_bin_deg_mult0000_Mxor__index0015 AND NOT N_PZ_907)
    	OR (Mmult_bin_deg_mult0000_Mxor__index0014 AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND N_PZ_907 AND NOT Mmult_bin_deg_mult0000_Mxor__index0021)
    	OR (NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND
    	NOT Mmult_bin_deg_mult0000__or0014 AND NOT Mmult_bin_deg_mult0000_Mxor__index0015 AND NOT N_PZ_907));

    Mmult_bin_deg_mult0000_Mxor__index0029 <= rx_out(2)
    	XOR ((Mmult_bin_deg_mult0000_Mxor__index0021 AND NOT N_PZ_929)
    	OR (NOT Mmult_bin_deg_mult0000_Mxor__index0021 AND N_PZ_929));

    Mmult_bin_deg_mult0000_Mxor__index0030 <= ((rx_out(3) AND rx_out(2) AND
    	Mmult_bin_deg_mult0000_Mxor__index0022 AND N_PZ_929)
    	OR (rx_out(3) AND NOT rx_out(2) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0022 AND Mmult_bin_deg_mult0000_Mxor__index0029)
    	OR (rx_out(3) AND
    	Mmult_bin_deg_mult0000_Mxor__index0021 AND Mmult_bin_deg_mult0000_Mxor__index0022 AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0029)
    	OR (rx_out(3) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0021 AND NOT Mmult_bin_deg_mult0000_Mxor__index0022 AND NOT N_PZ_929)
    	OR (NOT rx_out(3) AND rx_out(2) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0022 AND N_PZ_929)
    	OR (NOT rx_out(3) AND NOT rx_out(2) AND
    	Mmult_bin_deg_mult0000_Mxor__index0022 AND Mmult_bin_deg_mult0000_Mxor__index0029)
    	OR (NOT rx_out(3) AND
    	Mmult_bin_deg_mult0000_Mxor__index0021 AND NOT Mmult_bin_deg_mult0000_Mxor__index0022 AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0029)
    	OR (NOT rx_out(3) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0021 AND Mmult_bin_deg_mult0000_Mxor__index0022 AND NOT N_PZ_929));

    Mmult_bin_deg_mult0000_Mxor__index0031 <= N_PZ_632
    	XOR ((rx_out(7) AND rx_out(5))
    	OR (NOT rx_out(7) AND NOT rx_out(5))
    	OR (NOT rx_out(6) AND rx_out(7) AND
    	Mmult_bin_deg_mult0000_Mxor__index0014));

    Mmult_bin_deg_mult0000_Mxor__index0032 <= ((rx_out(7) AND rx_out(5) AND
    	Mmult_bin_deg_mult0000_Mxor__index0033)
    	OR (NOT rx_out(7) AND NOT rx_out(5) AND
    	Mmult_bin_deg_mult0000_Mxor__index0033)
    	OR (rx_out(6) AND NOT rx_out(5) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0033 AND N_PZ_911)
    	OR (rx_out(6) AND NOT Mmult_bin_deg_mult0000__or0017 AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0033 AND N_PZ_911)
    	OR (NOT rx_out(6) AND rx_out(7) AND NOT N_PZ_615 AND NOT N_PZ_653)
    	OR (NOT rx_out(6) AND NOT rx_out(7) AND rx_out(5) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0033)
    	OR (NOT rx_out(6) AND NOT rx_out(7) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0033 AND NOT N_PZ_615)
    	OR (NOT rx_out(7) AND rx_out(5) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0033 AND NOT N_PZ_911)
    	OR (NOT rx_out(6) AND rx_out(5) AND
    	NOT Mmult_bin_deg_mult0000__or0017 AND NOT Mmult_bin_deg_mult0000__or0023 AND NOT N_PZ_911)
    	OR (NOT rx_out(6) AND NOT rx_out(5) AND
    	NOT Mmult_bin_deg_mult0000__or0017 AND NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND
    	Mmult_bin_deg_mult0000_Mxor__index0033)
    	OR (NOT rx_out(6) AND NOT rx_out(5) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND Mmult_bin_deg_mult0000_Mxor__index0033 AND NOT N_PZ_911)
    	OR (NOT rx_out(5) AND NOT Mmult_bin_deg_mult0000__or0017 AND
    	NOT Mmult_bin_deg_mult0000__or0023 AND Mmult_bin_deg_mult0000_Mxor__index0033 AND NOT N_PZ_911));

    Mmult_bin_deg_mult0000_Mxor__index0033 <= ((rx_out(6) AND rx_out(7) AND rx_out(5) AND N_PZ_615)
    	OR (rx_out(6) AND rx_out(7) AND NOT rx_out(5) AND
    	NOT Mmult_bin_deg_mult0000__or0017)
    	OR (rx_out(6) AND NOT rx_out(7) AND NOT rx_out(5) AND N_PZ_615)
    	OR (NOT rx_out(6) AND rx_out(7) AND NOT rx_out(5) AND NOT N_PZ_653)
    	OR (NOT rx_out(6) AND NOT rx_out(7) AND rx_out(5) AND
    	NOT Mmult_bin_deg_mult0000__or0017)
    	OR (NOT rx_out(6) AND NOT rx_out(7) AND rx_out(5) AND NOT N_PZ_911)
    	OR (rx_out(7) AND NOT rx_out(5) AND NOT N_PZ_911 AND NOT N_PZ_653)
    	OR (NOT rx_out(7) AND rx_out(5) AND
    	NOT Mmult_bin_deg_mult0000__or0017 AND NOT Mmult_bin_deg_mult0000__or0023 AND NOT N_PZ_615));

    Mmult_bin_deg_mult0000__or0014 <= ((rx_out(0) AND rx_out(1) AND N_PZ_689)
    	OR (NOT rx_out(6) AND NOT rx_out(3) AND rx_out(1) AND NOT N_PZ_619)
    	OR (rx_out(3) AND NOT rx_out(4) AND rx_out(1) AND N_PZ_689)
    	OR (NOT rx_out(3) AND rx_out(0) AND rx_out(1) AND NOT N_PZ_619)
    	OR (rx_out(4) AND rx_out(1) AND N_PZ_689 AND N_PZ_621)
    	OR (NOT rx_out(4) AND rx_out(0) AND rx_out(1) AND N_PZ_621)
    	OR (rx_out(0) AND rx_out(1) AND N_PZ_619 AND N_PZ_621)
    	OR (rx_out(6) AND rx_out(3) AND rx_out(4) AND rx_out(1) AND
    	NOT N_PZ_621)
    	OR (NOT rx_out(3) AND NOT rx_out(4) AND NOT rx_out(5) AND rx_out(1) AND
    	NOT N_PZ_619)
    	OR (NOT rx_out(3) AND NOT rx_out(4) AND rx_out(0) AND NOT N_PZ_689 AND
    	NOT N_PZ_619)
    	OR (NOT rx_out(4) AND rx_out(5) AND NOT rx_out(2) AND rx_out(0) AND
    	rx_out(1))
    	OR (NOT rx_out(4) AND rx_out(2) AND rx_out(1) AND N_PZ_689 AND
    	NOT N_PZ_621)
    	OR (rx_out(6) AND rx_out(3) AND rx_out(0) AND NOT rx_out(1) AND
    	NOT N_PZ_689 AND NOT N_PZ_621)
    	OR (rx_out(4) AND rx_out(0) AND NOT rx_out(1) AND NOT N_PZ_689 AND
    	N_PZ_619 AND NOT N_PZ_621)
    	OR (rx_out(4) AND NOT rx_out(0) AND rx_out(1) AND NOT N_PZ_689 AND
    	N_PZ_619 AND NOT N_PZ_621));

    Mmult_bin_deg_mult0000__or0017 <= ((NOT rx_out(4) AND
    	Mmult_bin_deg_mult0000_Mxor__index0022)
    	OR (NOT rx_out(3) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0016 AND Mmult_bin_deg_mult0000_Mxor__index0021)
    	OR (NOT rx_out(2) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0016 AND Mmult_bin_deg_mult0000_Mxor__index0020 AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0015)
    	OR (NOT Mmult_bin_deg_mult0000_Mxor__index0016 AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND NOT Mmult_bin_deg_mult0000__or0014 AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0015));

    Mmult_bin_deg_mult0000__or00213 <= ((rx_out(0) AND NOT rx_out(1) AND N_PZ_689 AND
    	Mmult_bin_deg_mult0000_Mxor__index0020)
    	OR (NOT rx_out(6) AND NOT rx_out(3) AND rx_out(0) AND rx_out(1) AND
    	NOT N_PZ_621)
    	OR (rx_out(3) AND rx_out(4) AND rx_out(0) AND rx_out(1) AND
    	NOT N_PZ_689)
    	OR (NOT rx_out(3) AND rx_out(0) AND rx_out(1) AND NOT N_PZ_619 AND
    	N_PZ_621)
    	OR (rx_out(6) AND rx_out(3) AND NOT rx_out(4) AND rx_out(0) AND
    	rx_out(1) AND NOT N_PZ_621)
    	OR (rx_out(3) AND NOT rx_out(4) AND rx_out(0) AND rx_out(1) AND
    	N_PZ_689 AND N_PZ_621));

    Mmult_bin_deg_mult0000__or0023 <= ((NOT rx_out(3) AND
    	Mmult_bin_deg_mult0000_Mxor__index0030)
    	OR (NOT rx_out(2) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0022 AND Mmult_bin_deg_mult0000_Mxor__index0029)
    	OR (NOT Mmult_bin_deg_mult0000_Mxor__index0021 AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0022 AND NOT N_PZ_929));

    Mmult_bin_deg_mult0000__or0028 <= ((rx_out(1) AND
    	Mmult_bin_deg_mult0000_Mxor__index0029)
    	OR (rx_out(0) AND rx_out(1) AND
    	Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000__or00213)
    	OR (rx_out(0) AND rx_out(1) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND NOT Mmult_bin_deg_mult0000__or00213)
    	OR (rx_out(0) AND N_PZ_689 AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000_Mxor__index0029)
    	OR (rx_out(0) AND
    	Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000_Mxor__index0029 AND
    	NOT Mmult_bin_deg_mult0000__or00213));

    Mmult_bin_deg_mult0000__or0031 <= ((NOT rx_out(4) AND bin_deg(4))
    	OR (NOT rx_out(3) AND bin_deg(3) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0032)
    	OR (NOT Mmult_bin_deg_mult0000_Mxor__index0031 AND NOT N_PZ_761 AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0032));

    N_PZ_1003 <= (NOT u2/forward_backward AND NOT u2/cnt_reg(0) AND
    	u2/sensor_set_cmp_ne0000 AND NOT u2/cnt_reg(1) AND NOT N_PZ_1032);

    N_PZ_1022 <= ((u4/XLXN_94)
    	OR (rx_out(7) AND NOT N_PZ_624 AND NOT u4/XLXN_83));

    N_PZ_1032 <= (NOT data_ready AND NOT u2/run);

    N_PZ_604 <= rx_out(5)
    	XOR ((Mmult_bin_deg_mult0000__or0031 AND
    	Mmult_bin_deg_mult0000_Mxor__index0033)
    	OR (NOT Mmult_bin_deg_mult0000__or0031 AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0033));

    N_PZ_606 <= rx_out(2)
    	XOR ((Mmult_bin_deg_mult0000_Mxor__index0030 AND
    	NOT Mmult_bin_deg_mult0000__or0028)
    	OR (NOT Mmult_bin_deg_mult0000_Mxor__index0030 AND
    	Mmult_bin_deg_mult0000__or0028));

    N_PZ_615 <= ((N_PZ_911)
    	OR (Mmult_bin_deg_mult0000__or0017 AND
    	Mmult_bin_deg_mult0000__or0023));

    N_PZ_619 <= ((NOT rx_out(6) AND NOT rx_out(5))
    	OR (NOT rx_out(6) AND rx_out(2)));

    N_PZ_621 <= (NOT rx_out(5) AND rx_out(2));

    N_PZ_624 <= ((NOT rx_out(6) AND NOT rx_out(5) AND
    	Mmult_bin_deg_mult0000__or0031 AND NOT N_PZ_653)
    	OR (NOT rx_out(6) AND NOT rx_out(5) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0033 AND NOT N_PZ_653));

    N_PZ_632 <= rx_out(4)
    	XOR ((Mmult_bin_deg_mult0000__or0017 AND
    	Mmult_bin_deg_mult0000__or0023)
    	OR (NOT Mmult_bin_deg_mult0000__or0017 AND
    	NOT Mmult_bin_deg_mult0000__or0023));

    N_PZ_641 <= ((u4/XLXN_27 AND u4/XLXN_41)
    	OR (NOT u4/XLXN_27 AND NOT u4/XLXN_41 AND NOT u4/XLXN_28)
    	OR (bin_deg(3) AND N_PZ_606 AND NOT u4/XLXN_27 AND u4/XLXN_29)
    	OR (NOT u4/XLXN_27 AND u4/XLXN_28 AND u4/XLXN_29 AND
    	NOT u4/XLXN_35));

    N_PZ_642 <= ((u2/cnt_reg(1) AND NOT rx_out(1))
    	OR (u2/cnt_reg(0) AND u2/cnt_reg(1) AND NOT rx_out(0))
    	OR (u2/cnt_reg(0) AND NOT rx_out(0) AND NOT rx_out(1)));

    N_PZ_643 <= ((NOT rx_out(4) AND N_PZ_680)
    	OR (u2/cnt_reg(4) AND u2/Msub__sub0000__or0003));

    N_PZ_653 <= (NOT Mmult_bin_deg_mult0000__or0017 AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND NOT Mmult_bin_deg_mult0000__or0023 AND NOT N_PZ_911);

    N_PZ_666 <= ((u4/XLXN_83 AND NOT u4/XLXI_46/S1_or00007 AND NOT u4/XLXN_81)
    	OR (NOT u4/XLXN_83 AND N_PZ_604 AND u4/XLXI_46/S1_or00007)
    	OR (NOT u4/XLXN_83 AND u4/XLXI_46/S1_or00007 AND u4/XLXN_81));

    N_PZ_680 <= rx_out(4)
    	XOR ((u2/cnt_reg(4) AND NOT u2/Msub__sub0000__or0003)
    	OR (NOT u2/cnt_reg(4) AND u2/Msub__sub0000__or0003));

    N_PZ_689 <= ((rx_out(3) AND N_PZ_619)
    	OR (NOT rx_out(4) AND N_PZ_619 AND N_PZ_621)
    	OR (rx_out(6) AND rx_out(3) AND rx_out(5) AND NOT rx_out(2))
    	OR (rx_out(6) AND NOT rx_out(3) AND rx_out(4) AND rx_out(2))
    	OR (rx_out(6) AND NOT rx_out(3) AND NOT rx_out(4) AND rx_out(5))
    	OR (rx_out(6) AND NOT rx_out(3) AND NOT rx_out(5) AND NOT rx_out(2))
    	OR (NOT rx_out(6) AND NOT rx_out(3) AND rx_out(4) AND NOT N_PZ_619));

    N_PZ_695 <= ((u2/cnt_reg(2) AND NOT rx_out(2))
    	OR (N_PZ_642 AND N_PZ_904));

    N_PZ_750 <= ((u1/regrx(17) AND u1/regrx(18) AND u1/regrx(19) AND
    	u1/regrx(21) AND u1/regrx(29) AND u1/regrx(31) AND u1/regrx(32) AND
    	NOT u1/regrx(33) AND u1/regrx(34) AND NOT u1/regrx(35) AND u1/regrx(36) AND
    	NOT u1/regrx(37) AND u1/regrx(38) AND u1/regrx(39) AND u1/regrx(1) AND
    	u1/regrx(2) AND NOT u1/regrx(3) AND u1/regrx(4) AND NOT u1/regrx(5) AND
    	u1/regrx(6) AND NOT u1/regrx(7) AND u1/regrx(8) AND u1/regrx(9) AND
    	NOT u1/rx_out_or000047 AND NOT u1/rx_out_or000044 AND NOT N_PZ_970)
    	OR (u1/regrx(17) AND u1/regrx(18) AND u1/regrx(19) AND
    	u1/regrx(29) AND u1/regrx(31) AND u1/regrx(32) AND NOT u1/regrx(33) AND
    	u1/regrx(34) AND NOT u1/regrx(35) AND u1/regrx(36) AND NOT u1/regrx(37) AND
    	u1/regrx(38) AND u1/regrx(39) AND u1/regrx(11) AND u1/regrx(1) AND
    	u1/regrx(2) AND NOT u1/regrx(3) AND u1/regrx(4) AND NOT u1/regrx(5) AND
    	u1/regrx(6) AND NOT u1/regrx(7) AND u1/regrx(8) AND u1/regrx(9) AND
    	NOT u1/rx_out_or000047 AND NOT u1/rx_out_or000044 AND NOT N_PZ_970)
    	OR (u1/regrx(17) AND u1/regrx(19) AND u1/regrx(21) AND
    	u1/regrx(28) AND u1/regrx(29) AND u1/regrx(31) AND u1/regrx(32) AND
    	NOT u1/regrx(33) AND u1/regrx(34) AND NOT u1/regrx(35) AND u1/regrx(36) AND
    	NOT u1/regrx(37) AND u1/regrx(38) AND u1/regrx(39) AND u1/regrx(1) AND
    	u1/regrx(2) AND NOT u1/regrx(3) AND u1/regrx(4) AND NOT u1/regrx(5) AND
    	u1/regrx(6) AND NOT u1/regrx(7) AND u1/regrx(8) AND u1/regrx(9) AND
    	NOT u1/rx_out_or000047 AND NOT u1/rx_out_or000044 AND NOT N_PZ_970)
    	OR (u1/regrx(17) AND u1/regrx(19) AND u1/regrx(28) AND
    	u1/regrx(29) AND u1/regrx(31) AND u1/regrx(32) AND NOT u1/regrx(33) AND
    	u1/regrx(34) AND NOT u1/regrx(35) AND u1/regrx(36) AND NOT u1/regrx(37) AND
    	u1/regrx(38) AND u1/regrx(39) AND u1/regrx(11) AND u1/regrx(1) AND
    	u1/regrx(2) AND NOT u1/regrx(3) AND u1/regrx(4) AND NOT u1/regrx(5) AND
    	u1/regrx(6) AND NOT u1/regrx(7) AND u1/regrx(8) AND u1/regrx(9) AND
    	NOT u1/rx_out_or000047 AND NOT u1/rx_out_or000044 AND NOT N_PZ_970)
    	OR (u1/regrx(18) AND u1/regrx(19) AND u1/regrx(21) AND
    	u1/regrx(27) AND u1/regrx(29) AND u1/regrx(31) AND u1/regrx(32) AND
    	NOT u1/regrx(33) AND u1/regrx(34) AND NOT u1/regrx(35) AND u1/regrx(36) AND
    	NOT u1/regrx(37) AND u1/regrx(38) AND u1/regrx(39) AND u1/regrx(1) AND
    	u1/regrx(2) AND NOT u1/regrx(3) AND u1/regrx(4) AND NOT u1/regrx(5) AND
    	u1/regrx(6) AND NOT u1/regrx(7) AND u1/regrx(8) AND u1/regrx(9) AND
    	NOT u1/rx_out_or000047 AND NOT u1/rx_out_or000044 AND NOT N_PZ_970)
    	OR (u1/regrx(18) AND u1/regrx(19) AND u1/regrx(27) AND
    	u1/regrx(29) AND u1/regrx(31) AND u1/regrx(32) AND NOT u1/regrx(33) AND
    	u1/regrx(34) AND NOT u1/regrx(35) AND u1/regrx(36) AND NOT u1/regrx(37) AND
    	u1/regrx(38) AND u1/regrx(39) AND u1/regrx(11) AND u1/regrx(1) AND
    	u1/regrx(2) AND NOT u1/regrx(3) AND u1/regrx(4) AND NOT u1/regrx(5) AND
    	u1/regrx(6) AND NOT u1/regrx(7) AND u1/regrx(8) AND u1/regrx(9) AND
    	NOT u1/rx_out_or000047 AND NOT u1/rx_out_or000044 AND NOT N_PZ_970)
    	OR (u1/regrx(19) AND u1/regrx(21) AND u1/regrx(27) AND
    	u1/regrx(28) AND u1/regrx(29) AND u1/regrx(31) AND u1/regrx(32) AND
    	NOT u1/regrx(33) AND u1/regrx(34) AND NOT u1/regrx(35) AND u1/regrx(36) AND
    	NOT u1/regrx(37) AND u1/regrx(38) AND u1/regrx(39) AND u1/regrx(1) AND
    	u1/regrx(2) AND NOT u1/regrx(3) AND u1/regrx(4) AND NOT u1/regrx(5) AND
    	u1/regrx(6) AND NOT u1/regrx(7) AND u1/regrx(8) AND u1/regrx(9) AND
    	NOT u1/rx_out_or000047 AND NOT u1/rx_out_or000044 AND NOT N_PZ_970)
    	OR (u1/regrx(19) AND u1/regrx(27) AND u1/regrx(28) AND
    	u1/regrx(29) AND u1/regrx(31) AND u1/regrx(32) AND NOT u1/regrx(33) AND
    	u1/regrx(34) AND NOT u1/regrx(35) AND u1/regrx(36) AND NOT u1/regrx(37) AND
    	u1/regrx(38) AND u1/regrx(39) AND u1/regrx(11) AND u1/regrx(1) AND
    	u1/regrx(2) AND NOT u1/regrx(3) AND u1/regrx(4) AND NOT u1/regrx(5) AND
    	u1/regrx(6) AND NOT u1/regrx(7) AND u1/regrx(8) AND u1/regrx(9) AND
    	NOT u1/rx_out_or000047 AND NOT u1/rx_out_or000044 AND NOT N_PZ_970));

    N_PZ_761 <= ((rx_out(2) AND NOT N_PZ_606)
    	OR (Mmult_bin_deg_mult0000_Mxor__index0030 AND
    	Mmult_bin_deg_mult0000__or0028));

    N_PZ_762 <= ((NOT rx_out(7) AND u2/cnt_reg(7) AND
    	u2/Mcompar_forward_backward_cmp_lt0000_ALB20)
    	OR (u2/Mcompar_forward_backward_cmp_lt0000_ALB20 AND
    	u2/Msub__sub0000__or0006 AND NOT u2/SF17)
    	OR (u2/Mcompar_forward_backward_cmp_lt0000_ALB20 AND
    	NOT u2/Msub__sub0000__or0006 AND u2/SF17)
    	OR (u2/Mcompar_forward_backward_cmp_lt0000_ALB20 AND
    	u2/_sub0000(5) AND N_PZ_680 AND NOT u2/_sub0000(6))
    	OR (u2/Mcompar_forward_backward_cmp_lt0000_ALB20 AND
    	u2/_sub0000(5) AND u2/_sub0000(3) AND NOT u2/_sub0000(6))
    	OR (u2/Mcompar_forward_backward_cmp_lt0000_ALB20 AND
    	u2/_sub0000(5) AND N_PZ_642 AND N_PZ_904 AND NOT u2/_sub0000(6))
    	OR (u2/Mcompar_forward_backward_cmp_lt0000_ALB20 AND
    	u2/_sub0000(5) AND NOT N_PZ_642 AND NOT N_PZ_904 AND NOT u2/_sub0000(6)));

    N_PZ_789 <= ((rx_out(6) AND NOT u2/cnt_reg(6))
    	OR (rx_out(5) AND NOT u2/cnt_reg(5)));

    N_PZ_904 <= ((u2/cnt_reg(2) AND rx_out(2))
    	OR (NOT u2/cnt_reg(2) AND NOT rx_out(2)));

    N_PZ_907 <= ((rx_out(4) AND
    	Mmult_bin_deg_mult0000_Mxor__index0016)
    	OR (NOT rx_out(4) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0016));

    N_PZ_911 <= (NOT rx_out(4) AND
    	Mmult_bin_deg_mult0000_Mxor__index0031);

    N_PZ_929 <= ((Mmult_bin_deg_mult0000__or00213)
    	OR (rx_out(1) AND
    	Mmult_bin_deg_mult0000_Mxor__index0020));

    N_PZ_936 <= (u3/khertz_count(0) AND u3/khertz_count(1) AND
    	u3/khertz_count(2) AND u3/khertz_count(4));

    N_PZ_967 <= ((NOT sensor_en AND u2/sensor_set_cmp_ne0000 AND NOT N_PZ_1032)
    	OR (u2/sensor_set_cmp_ne0000 AND NOT N_PZ_1032 AND
    	NOT u2/sensor_set));

    N_PZ_970 <= (NOT u1/regrx(26) AND NOT u1/regrx(16));

    N_PZ_971 <= ((rx_out(4) AND NOT u2/cnt_reg(4))
    	OR (rx_out(3) AND rx_out(4) AND NOT u2/cnt_reg(3))
    	OR (rx_out(3) AND NOT u2/cnt_reg(4) AND NOT u2/cnt_reg(3)));

    N_PZ_977 <= (u2/forward_backward AND u2/cnt_reg(0) AND
    	u2/sensor_set_cmp_ne0000 AND u2/cnt_reg(1) AND NOT N_PZ_1032);

    bin_deg(1) <= ((rx_out(1) AND NOT Mmult_bin_deg_mult0000__or0028)
    	OR (Mmult_bin_deg_mult0000_Mxor__index0029 AND
    	NOT Mmult_bin_deg_mult0000__or0028)
    	OR (rx_out(0) AND N_PZ_689 AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND NOT Mmult_bin_deg_mult0000__or0028)
    	OR (rx_out(0) AND
    	Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000_Mxor__index0029 AND
    	Mmult_bin_deg_mult0000__or00213)
    	OR (rx_out(0) AND
    	Mmult_bin_deg_mult0000_Mxor__index0020 AND NOT Mmult_bin_deg_mult0000_Mxor__index0029 AND
    	NOT Mmult_bin_deg_mult0000__or00213)
    	OR (rx_out(0) AND rx_out(1) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000_Mxor__index0029 AND
    	NOT Mmult_bin_deg_mult0000__or00213));

    bin_deg(3) <= rx_out(3)
    	XOR ((Mmult_bin_deg_mult0000_Mxor__index0031 AND NOT N_PZ_761)
    	OR (NOT Mmult_bin_deg_mult0000_Mxor__index0031 AND N_PZ_761));

    bin_deg(4) <= ((rx_out(3) AND rx_out(4) AND N_PZ_761 AND
    	Mmult_bin_deg_mult0000_Mxor__index0032)
    	OR (rx_out(3) AND NOT rx_out(4) AND N_PZ_761 AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0032)
    	OR (NOT rx_out(3) AND rx_out(4) AND bin_deg(3) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0032)
    	OR (NOT rx_out(3) AND NOT rx_out(4) AND bin_deg(3) AND
    	Mmult_bin_deg_mult0000_Mxor__index0032)
    	OR (rx_out(4) AND NOT bin_deg(3) AND
    	Mmult_bin_deg_mult0000_Mxor__index0031 AND Mmult_bin_deg_mult0000_Mxor__index0032)
    	OR (rx_out(4) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0031 AND NOT N_PZ_761 AND NOT Mmult_bin_deg_mult0000_Mxor__index0032)
    	OR (NOT rx_out(4) AND NOT bin_deg(3) AND
    	Mmult_bin_deg_mult0000_Mxor__index0031 AND NOT Mmult_bin_deg_mult0000_Mxor__index0032)
    	OR (NOT rx_out(4) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0031 AND NOT N_PZ_761 AND Mmult_bin_deg_mult0000_Mxor__index0032));

    FTCPE_clk32k: FTCPE port map (clk32k,clk32k_T,clk,'0','0','1');
    clk32k_T <= ((NOT clk32k AND NOT cnt_32k(1) AND NOT cnt_32k(5) AND NOT cnt_32k(6) AND
    	NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10))
    	OR (NOT clk32k AND NOT cnt_32k(2) AND NOT cnt_32k(5) AND NOT cnt_32k(6) AND
    	NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10))
    	OR (NOT clk32k AND NOT cnt_32k(3) AND NOT cnt_32k(5) AND NOT cnt_32k(6) AND
    	NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10))
    	OR (NOT clk32k AND NOT cnt_32k(4) AND NOT cnt_32k(5) AND NOT cnt_32k(6) AND
    	NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10))
    	OR (clk32k AND NOT cnt_32k(0) AND cnt_32k(1) AND NOT cnt_32k(2) AND
    	cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND NOT cnt_32k(6) AND
    	NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10)));

    FTCPE_clk_div0: FTCPE port map (clk_div(0),'0',clk,'0','0','1');

    FTCPE_clk_div1: FTCPE port map (clk_div(1),clk_div(0),clk,'0','0','1');

    FTCPE_clk_div2: FTCPE port map (clk_div(2),clk_div_T(2),clk,'0','0','1');
    clk_div_T(2) <= (clk_div(0) AND clk_div(1));

    FTCPE_clk_div3: FTCPE port map (clk_div(3),clk_div_T(3),clk,'0','0','1');
    clk_div_T(3) <= (clk_div(0) AND clk_div(1) AND clk_div(2));

    FTCPE_clk_div4: FTCPE port map (clk_div(4),clk_div_T(4),clk,'0','0','1');
    clk_div_T(4) <= (clk_div(0) AND clk_div(1) AND clk_div(2) AND
    	clk_div(3));

    FTCPE_clk_div5: FTCPE port map (clk_div(5),clk_div_T(5),clk,'0','0','1');
    clk_div_T(5) <= (clk_div(0) AND clk_div(1) AND clk_div(2) AND
    	clk_div(3) AND clk_div(4));

    FTCPE_clk_div6: FTCPE port map (clk_div(6),clk_div_T(6),clk,'0','0','1');
    clk_div_T(6) <= (clk_div(0) AND clk_div(1) AND clk_div(2) AND
    	clk_div(3) AND clk_div(4) AND clk_div(5));

    FTCPE_clk_div7: FTCPE port map (clk_div(7),clk_div_T(7),clk,'0','0','1');
    clk_div_T(7) <= (clk_div(0) AND clk_div(1) AND clk_div(2) AND
    	clk_div(3) AND clk_div(4) AND clk_div(5) AND clk_div(6));

    FTCPE_clk_div8: FTCPE port map (clk_div(8),clk_div_T(8),clk,'0','0','1');
    clk_div_T(8) <= (clk_div(0) AND clk_div(1) AND clk_div(2) AND
    	clk_div(3) AND clk_div(4) AND clk_div(5) AND clk_div(6) AND
    	clk_div(7));

    FTCPE_clk_div9: FTCPE port map (clk_div(9),clk_div_T(9),clk,'0','0','1');
    clk_div_T(9) <= (clk_div(0) AND clk_div(1) AND clk_div(2) AND
    	clk_div(3) AND clk_div(4) AND clk_div(5) AND clk_div(6) AND
    	clk_div(7) AND clk_div(8));

    FTCPE_clk_div10: FTCPE port map (clk_div(10),clk_div_T(10),clk,'0','0','1');
    clk_div_T(10) <= (clk_div(0) AND clk_div(1) AND clk_div(2) AND
    	clk_div(3) AND clk_div(4) AND clk_div(5) AND clk_div(6) AND
    	clk_div(7) AND clk_div(8) AND clk_div(9));

    FTCPE_clk_div11: FTCPE port map (clk_div(11),clk_div_T(11),clk,'0','0','1');
    clk_div_T(11) <= (clk_div(0) AND clk_div(10) AND clk_div(1) AND
    	clk_div(2) AND clk_div(3) AND clk_div(4) AND clk_div(5) AND
    	clk_div(6) AND clk_div(7) AND clk_div(8) AND clk_div(9));

    FTCPE_clk_div12: FTCPE port map (clk_div(12),clk_div_T(12),clk,'0','0','1');
    clk_div_T(12) <= (clk_div(0) AND clk_div(10) AND clk_div(1) AND
    	clk_div(2) AND clk_div(3) AND clk_div(4) AND clk_div(5) AND
    	clk_div(6) AND clk_div(7) AND clk_div(8) AND clk_div(9) AND
    	clk_div(11));

    FTCPE_clk_div13: FTCPE port map (clk_div(13),clk_div_T(13),clk,'0','0','1');
    clk_div_T(13) <= (clk_div(0) AND clk_div(10) AND clk_div(1) AND
    	clk_div(2) AND clk_div(3) AND clk_div(4) AND clk_div(5) AND
    	clk_div(6) AND clk_div(7) AND clk_div(8) AND clk_div(9) AND
    	clk_div(11) AND clk_div(12));

    FTCPE_cnt_32k0: FTCPE port map (cnt_32k(0),cnt_32k_T(0),clk,'0','0','1');
    cnt_32k_T(0) <= NOT ((NOT cnt_32k(0) AND cnt_32k(1) AND NOT cnt_32k(2) AND
    	cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND NOT cnt_32k(6) AND
    	NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10)));

    FTCPE_cnt_32k1: FTCPE port map (cnt_32k(1),cnt_32k_T(1),clk,'0','0','1');
    cnt_32k_T(1) <= ((cnt_32k(0))
    	OR (cnt_32k(1) AND NOT cnt_32k(2) AND cnt_32k(3) AND
    	cnt_32k(4) AND cnt_32k(5) AND NOT cnt_32k(6) AND NOT cnt_32k(7) AND
    	NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10)));

    FTCPE_cnt_32k2: FTCPE port map (cnt_32k(2),cnt_32k_T(2),clk,'0','0','1');
    cnt_32k_T(2) <= (cnt_32k(0) AND cnt_32k(1));

    FTCPE_cnt_32k3: FTCPE port map (cnt_32k(3),cnt_32k_T(3),clk,'0','0','1');
    cnt_32k_T(3) <= ((cnt_32k(0) AND cnt_32k(1) AND cnt_32k(2))
    	OR (NOT cnt_32k(0) AND cnt_32k(1) AND NOT cnt_32k(2) AND
    	cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND NOT cnt_32k(6) AND
    	NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10)));

    FTCPE_cnt_32k4: FTCPE port map (cnt_32k(4),cnt_32k_T(4),clk,'0','0','1');
    cnt_32k_T(4) <= ((cnt_32k(0) AND cnt_32k(1) AND cnt_32k(2) AND
    	cnt_32k(3))
    	OR (NOT cnt_32k(0) AND cnt_32k(1) AND NOT cnt_32k(2) AND
    	cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND NOT cnt_32k(6) AND
    	NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10)));

    FTCPE_cnt_32k5: FTCPE port map (cnt_32k(5),cnt_32k_T(5),clk,'0','0','1');
    cnt_32k_T(5) <= ((cnt_32k(0) AND cnt_32k(1) AND cnt_32k(2) AND
    	cnt_32k(3) AND cnt_32k(4))
    	OR (NOT cnt_32k(0) AND cnt_32k(1) AND NOT cnt_32k(2) AND
    	cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND NOT cnt_32k(6) AND
    	NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10)));

    FTCPE_cnt_32k6: FTCPE port map (cnt_32k(6),cnt_32k_T(6),clk,'0','0','1');
    cnt_32k_T(6) <= (cnt_32k(0) AND cnt_32k(1) AND cnt_32k(2) AND
    	cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5));

    FTCPE_cnt_32k7: FTCPE port map (cnt_32k(7),cnt_32k_T(7),clk,'0','0','1');
    cnt_32k_T(7) <= (cnt_32k(0) AND cnt_32k(1) AND cnt_32k(2) AND
    	cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND cnt_32k(6));

    FTCPE_cnt_32k8: FTCPE port map (cnt_32k(8),cnt_32k_T(8),clk,'0','0','1');
    cnt_32k_T(8) <= (cnt_32k(0) AND cnt_32k(1) AND cnt_32k(2) AND
    	cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND cnt_32k(6) AND
    	cnt_32k(7));

    FTCPE_cnt_32k9: FTCPE port map (cnt_32k(9),cnt_32k_T(9),clk,'0','0','1');
    cnt_32k_T(9) <= (cnt_32k(0) AND cnt_32k(1) AND cnt_32k(2) AND
    	cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND cnt_32k(6) AND
    	cnt_32k(7) AND cnt_32k(8));

    FTCPE_cnt_32k10: FTCPE port map (cnt_32k(10),cnt_32k_T(10),clk,'0','0','1');
    cnt_32k_T(10) <= (cnt_32k(0) AND cnt_32k(1) AND cnt_32k(2) AND
    	cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND cnt_32k(6) AND
    	cnt_32k(7) AND cnt_32k(8) AND cnt_32k(9));

    FTCPE_data_ready: FTCPE port map (data_ready,data_ready_T,clk32k,'0','0','1');
    data_ready_T <= ((data_ready AND u1/edge)
    	OR (NOT u1/edge AND u1/clkdiv(0) AND u1/clkdiv(1) AND
    	u1/clkdiv(2)));

    FDCPE_digit40: FDCPE port map (digit4(0),digit4_D(0),clk,'0','0','1');
    digit4_D(0) <= NOT ((NOT u3/cd(0) AND NOT u3/cd(1)));

    FDCPE_digit41: FDCPE port map (digit4(1),digit4_D(1),clk,'0','0','1');
    digit4_D(1) <= NOT ((u3/cd(0) AND NOT u3/cd(1)));

    FDCPE_digit42: FDCPE port map (digit4(2),digit4_D(2),clk,'0','0','1');
    digit4_D(2) <= NOT ((NOT u3/cd(0) AND u3/cd(1)));

    FDCPE_digit43: FDCPE port map (digit4(3),digit4_D(3),clk,'0','0','1');
    digit4_D(3) <= NOT ((u3/cd(0) AND u3/cd(1)));

    output_mot(0) <= ((u2/run AND u2/now_ST_FFd1)
    	OR (u2/now_ST_FFd3 AND u2/run AND NOT u2/now_ST_FFd2));

    output_mot(1) <= ((u2/run AND u2/now_ST_FFd1)
    	OR (NOT u2/now_ST_FFd3 AND u2/run AND u2/now_ST_FFd2));

    output_mot(2) <= ((u2/now_ST_FFd3 AND u2/run AND u2/now_ST_FFd2)
    	OR (u2/run AND u2/now_ST_FFd2 AND u2/now_ST_FFd4));

    output_mot(3) <= ((u2/run AND NOT u2/now_ST_FFd2 AND u2/now_ST_FFd4)
    	OR (u2/now_ST_FFd3 AND u2/run AND u2/now_ST_FFd2 AND
    	NOT u2/now_ST_FFd4));

    FDCPE_rx_out0: FDCPE port map (rx_out(0),u1/regrx(11),data_ready,'0','0',N_PZ_750);

    FDCPE_rx_out1: FDCPE port map (rx_out(1),u1/regrx(12),data_ready,'0','0',N_PZ_750);

    FDCPE_rx_out2: FDCPE port map (rx_out(2),u1/regrx(13),data_ready,'0','0',N_PZ_750);

    FDCPE_rx_out3: FDCPE port map (rx_out(3),u1/regrx(14),data_ready,'0','0',N_PZ_750);

    FDCPE_rx_out4: FDCPE port map (rx_out(4),u1/regrx(15),data_ready,'0','0',N_PZ_750);

    FDCPE_rx_out5: FDCPE port map (rx_out(5),u1/regrx(16),data_ready,'0','0',N_PZ_750);

    FDCPE_rx_out6: FDCPE port map (rx_out(6),u1/regrx(17),data_ready,'0','0',N_PZ_750);

    FDCPE_rx_out7: FDCPE port map (rx_out(7),u1/regrx(18),data_ready,'0','0',N_PZ_750);

    FDCPE_seg40: FDCPE port map (seg4(0),u3/dp,clk,'0','0','1');

    FDCPE_seg41: FDCPE port map (seg4(1),seg4_D(1),clk,'0','0','1');
    seg4_D(1) <= ((NOT u3/curr(1) AND NOT u3/curr(2) AND NOT u3/curr(3))
    	OR (u3/curr(1) AND u3/curr(2) AND NOT u3/curr(3) AND
    	u3/curr(0)));

    FDCPE_seg42: FDCPE port map (seg4(2),seg4_D(2),clk,'0','0','1');
    seg4_D(2) <= ((u3/curr(1) AND NOT u3/curr(2) AND NOT u3/curr(3))
    	OR (u3/curr(1) AND u3/curr(2) AND NOT u3/curr(3) AND
    	u3/curr(0))
    	OR (NOT u3/curr(1) AND NOT u3/curr(2) AND NOT u3/curr(3) AND
    	u3/curr(0)));

    FDCPE_seg43: FDCPE port map (seg4(3),seg4_D(3),clk,'0','0','1');
    seg4_D(3) <= NOT (((u3/curr(1) AND NOT u3/curr(3) AND NOT u3/curr(0))
    	OR (NOT u3/curr(1) AND NOT u3/curr(2) AND NOT u3/curr(0))));

    FDCPE_seg44: FDCPE port map (seg4(4),seg4_D(4),clk,'0','0','1');
    seg4_D(4) <= NOT (NOT u3/curr(2)
    	XOR ((u3/curr(1) AND NOT u3/curr(2) AND u3/curr(3))
    	OR (NOT u3/curr(1) AND NOT u3/curr(3) AND u3/curr(0))
    	OR (u3/curr(1) AND u3/curr(2) AND NOT u3/curr(3) AND
    	NOT u3/curr(0))));

    FDCPE_seg45: FDCPE port map (seg4(5),seg4_D(5),clk,'0','0','1');
    seg4_D(5) <= NOT (((NOT u3/curr(1) AND NOT u3/curr(2))
    	OR (u3/curr(2) AND NOT u3/curr(3))
    	OR (NOT u3/curr(3) AND u3/curr(0))));

    FDCPE_seg46: FDCPE port map (seg4(6),seg4_D(6),clk,'0','0','1');
    seg4_D(6) <= ((u3/curr(1) AND u3/curr(2) AND NOT u3/curr(3) AND
    	NOT u3/curr(0))
    	OR (NOT u3/curr(1) AND u3/curr(2) AND NOT u3/curr(3) AND
    	u3/curr(0)));

    FDCPE_seg47: FDCPE port map (seg4(7),seg4_D(7),clk,'0','0','1');
    seg4_D(7) <= ((NOT u3/curr(1) AND u3/curr(2) AND NOT u3/curr(3) AND
    	NOT u3/curr(0))
    	OR (NOT u3/curr(1) AND NOT u3/curr(2) AND NOT u3/curr(3) AND
    	u3/curr(0)));

    FDCPE_u1/clkdiv0: FDCPE port map (u1/clkdiv(0),u1/clkdiv_D(0),clk32k,'0','0','1');
    u1/clkdiv_D(0) <= NOT ((NOT u1/edge AND u1/clkdiv(0)));

    FDCPE_u1/clkdiv1: FDCPE port map (u1/clkdiv(1),u1/clkdiv_D(1),clk32k,'0','0','1');
    u1/clkdiv_D(1) <= NOT (((NOT u1/edge AND u1/clkdiv(0) AND u1/clkdiv(1))
    	OR (NOT u1/edge AND NOT u1/clkdiv(0) AND NOT u1/clkdiv(1))));

    FTCPE_u1/clkdiv2: FTCPE port map (u1/clkdiv(2),u1/clkdiv_T(2),clk32k,'0','0','1');
    u1/clkdiv_T(2) <= ((u1/edge AND u1/clkdiv(2))
    	OR (NOT u1/edge AND u1/clkdiv(0) AND u1/clkdiv(1)));

    FDCPE_u1/edge: FDCPE port map (u1/edge,u1/edge_D,clk32k,'0','0','1');
    u1/edge_D <= ((u1/rxd1 AND NOT u1/rxd2)
    	OR (NOT u1/rxd1 AND u1/rxd2));

    FDCPE_u1/regrx0: FDCPE port map (u1/regrx(0),u1/regrx(1),data_ready,'0','0','1');

    FDCPE_u1/regrx1: FDCPE port map (u1/regrx(1),u1/regrx(2),data_ready,'0','0','1');

    FDCPE_u1/regrx2: FDCPE port map (u1/regrx(2),u1/regrx(3),data_ready,'0','0','1');

    FDCPE_u1/regrx3: FDCPE port map (u1/regrx(3),u1/regrx(4),data_ready,'0','0','1');

    FDCPE_u1/regrx4: FDCPE port map (u1/regrx(4),u1/regrx(5),data_ready,'0','0','1');

    FDCPE_u1/regrx5: FDCPE port map (u1/regrx(5),u1/regrx(6),data_ready,'0','0','1');

    FDCPE_u1/regrx6: FDCPE port map (u1/regrx(6),u1/regrx(7),data_ready,'0','0','1');

    FDCPE_u1/regrx7: FDCPE port map (u1/regrx(7),u1/regrx(8),data_ready,'0','0','1');

    FDCPE_u1/regrx8: FDCPE port map (u1/regrx(8),u1/regrx(9),data_ready,'0','0','1');

    FDCPE_u1/regrx9: FDCPE port map (u1/regrx(9),u1/regrx(10),data_ready,'0','0','1');

    FDCPE_u1/regrx10: FDCPE port map (u1/regrx(10),u1/regrx(11),data_ready,'0','0','1');

    FDCPE_u1/regrx11: FDCPE port map (u1/regrx(11),u1/regrx(12),data_ready,'0','0','1');

    FDCPE_u1/regrx12: FDCPE port map (u1/regrx(12),u1/regrx(13),data_ready,'0','0','1');

    FDCPE_u1/regrx13: FDCPE port map (u1/regrx(13),u1/regrx(14),data_ready,'0','0','1');

    FDCPE_u1/regrx14: FDCPE port map (u1/regrx(14),u1/regrx(15),data_ready,'0','0','1');

    FDCPE_u1/regrx15: FDCPE port map (u1/regrx(15),u1/regrx(16),data_ready,'0','0','1');

    FDCPE_u1/regrx16: FDCPE port map (u1/regrx(16),u1/regrx(17),data_ready,'0','0','1');

    FDCPE_u1/regrx17: FDCPE port map (u1/regrx(17),u1/regrx(18),data_ready,'0','0','1');

    FDCPE_u1/regrx18: FDCPE port map (u1/regrx(18),u1/regrx(19),data_ready,'0','0','1');

    FDCPE_u1/regrx19: FDCPE port map (u1/regrx(19),u1/regrx(20),data_ready,'0','0','1');

    FDCPE_u1/regrx20: FDCPE port map (u1/regrx(20),u1/regrx(21),data_ready,'0','0','1');

    FDCPE_u1/regrx21: FDCPE port map (u1/regrx(21),u1/regrx(22),data_ready,'0','0','1');

    FDCPE_u1/regrx22: FDCPE port map (u1/regrx(22),u1/regrx(23),data_ready,'0','0','1');

    FDCPE_u1/regrx23: FDCPE port map (u1/regrx(23),u1/regrx(24),data_ready,'0','0','1');

    FDCPE_u1/regrx24: FDCPE port map (u1/regrx(24),u1/regrx(25),data_ready,'0','0','1');

    FDCPE_u1/regrx25: FDCPE port map (u1/regrx(25),u1/regrx(26),data_ready,'0','0','1');

    FDCPE_u1/regrx26: FDCPE port map (u1/regrx(26),u1/regrx(27),data_ready,'0','0','1');

    FDCPE_u1/regrx27: FDCPE port map (u1/regrx(27),u1/regrx(28),data_ready,'0','0','1');

    FDCPE_u1/regrx28: FDCPE port map (u1/regrx(28),u1/regrx(29),data_ready,'0','0','1');

    FDCPE_u1/regrx29: FDCPE port map (u1/regrx(29),u1/regrx(30),data_ready,'0','0','1');

    FDCPE_u1/regrx30: FDCPE port map (u1/regrx(30),u1/regrx(31),data_ready,'0','0','1');

    FDCPE_u1/regrx31: FDCPE port map (u1/regrx(31),u1/regrx(32),data_ready,'0','0','1');

    FDCPE_u1/regrx32: FDCPE port map (u1/regrx(32),u1/regrx(33),data_ready,'0','0','1');

    FDCPE_u1/regrx33: FDCPE port map (u1/regrx(33),u1/regrx(34),data_ready,'0','0','1');

    FDCPE_u1/regrx34: FDCPE port map (u1/regrx(34),u1/regrx(35),data_ready,'0','0','1');

    FDCPE_u1/regrx35: FDCPE port map (u1/regrx(35),u1/regrx(36),data_ready,'0','0','1');

    FDCPE_u1/regrx36: FDCPE port map (u1/regrx(36),u1/regrx(37),data_ready,'0','0','1');

    FDCPE_u1/regrx37: FDCPE port map (u1/regrx(37),u1/regrx(38),data_ready,'0','0','1');

    FDCPE_u1/regrx38: FDCPE port map (u1/regrx(38),u1/regrx(39),data_ready,'0','0','1');

    FDCPE_u1/regrx39: FDCPE port map (u1/regrx(39),rx_data,data_ready,'0','0','1');

    u1/rx_out_or000044 <= ((u1/regrx(20))
    	OR (u1/regrx(30))
    	OR (u1/regrx(10))
    	OR (u1/regrx(0))
    	OR (u1/regrx(21) AND u1/regrx(11))
    	OR (u1/regrx(22) AND u1/regrx(12))
    	OR (u1/regrx(23) AND u1/regrx(13))
    	OR (u1/regrx(24) AND u1/regrx(14)));

    u1/rx_out_or000047 <= ((u1/regrx(17) AND u1/regrx(27))
    	OR (u1/regrx(18) AND u1/regrx(28))
    	OR (NOT u1/regrx(22) AND NOT u1/regrx(12))
    	OR (NOT u1/regrx(23) AND NOT u1/regrx(13))
    	OR (NOT u1/regrx(24) AND NOT u1/regrx(14))
    	OR (u1/regrx(25) AND u1/regrx(15))
    	OR (NOT u1/regrx(25) AND NOT u1/regrx(15))
    	OR (u1/regrx(26) AND u1/regrx(16)));

    FDCPE_u1/rxd1: FDCPE port map (u1/rxd1,rx_data,clk32k,'0','0','1');

    FDCPE_u1/rxd2: FDCPE port map (u1/rxd2,u1/rxd1,clk32k,'0','0','1');

    u2/Mcompar_forward_backward_cmp_lt0000_ALB20 <= ((u2/SF17)
    	OR (rx_out(7) AND NOT u2/Msub__sub0000__or0006 AND NOT u2/SF17)
    	OR (NOT u2/cnt_reg(7) AND NOT u2/Msub__sub0000__or0006 AND
    	NOT u2/SF17)
    	OR (NOT rx_out(7) AND u2/cnt_reg(7) AND
    	u2/Msub__sub0000__or0006 AND u2/_sub0000(5))
    	OR (NOT rx_out(7) AND u2/cnt_reg(7) AND
    	u2/Msub__sub0000__or0006 AND u2/_sub0000(3))
    	OR (NOT rx_out(7) AND u2/cnt_reg(7) AND
    	u2/Msub__sub0000__or0006 AND NOT u2/_sub0000(6))
    	OR (NOT u2/_sub0000(5) AND NOT u2/_sub0000(3) AND N_PZ_695 AND
    	u2/_sub0000(6))
    	OR (NOT u2/_sub0000(5) AND NOT N_PZ_695 AND N_PZ_642 AND
    	u2/_sub0000(6))
    	OR (NOT rx_out(7) AND u2/cnt_reg(7) AND NOT u2/cnt_reg(0) AND
    	rx_out(0) AND u2/Msub__sub0000__or0006)
    	OR (NOT rx_out(7) AND u2/cnt_reg(7) AND NOT u2/cnt_reg(1) AND
    	rx_out(1) AND u2/Msub__sub0000__or0006)
    	OR (u2/cnt_reg(2) AND NOT rx_out(2) AND NOT u2/_sub0000(5) AND
    	N_PZ_642 AND u2/_sub0000(6))
    	OR (u2/cnt_reg(2) AND NOT u2/_sub0000(5) AND N_PZ_680 AND
    	NOT N_PZ_695 AND u2/_sub0000(6))
    	OR (NOT u2/cnt_reg(2) AND rx_out(2) AND NOT u2/_sub0000(5) AND
    	NOT u2/_sub0000(3) AND u2/_sub0000(6))
    	OR (NOT rx_out(2) AND NOT u2/_sub0000(5) AND N_PZ_680 AND
    	NOT N_PZ_695 AND u2/_sub0000(6))
    	OR (rx_out(7) AND u2/Msub__sub0000__or0006 AND
    	NOT u2/_sub0000(5) AND NOT N_PZ_680 AND u2/_sub0000(6) AND NOT u2/SF17)
    	OR (NOT rx_out(7) AND u2/cnt_reg(7) AND
    	NOT u2/Msub__sub0000__or0006 AND NOT u2/_sub0000(5) AND NOT N_PZ_680 AND u2/_sub0000(6))
    	OR (NOT u2/cnt_reg(7) AND u2/Msub__sub0000__or0006 AND
    	NOT u2/_sub0000(5) AND NOT N_PZ_680 AND u2/_sub0000(6) AND NOT u2/SF17)
    	OR (u2/cnt_reg(0) AND u2/cnt_reg(1) AND NOT u2/_sub0000(5) AND
    	N_PZ_680 AND NOT N_PZ_642 AND u2/_sub0000(6))
    	OR (u2/cnt_reg(0) AND NOT rx_out(1) AND NOT u2/_sub0000(5) AND
    	N_PZ_680 AND NOT N_PZ_642 AND u2/_sub0000(6))
    	OR (u2/cnt_reg(1) AND NOT rx_out(0) AND NOT u2/_sub0000(5) AND
    	N_PZ_680 AND NOT N_PZ_642 AND u2/_sub0000(6))
    	OR (NOT rx_out(0) AND NOT rx_out(1) AND NOT u2/_sub0000(5) AND
    	N_PZ_680 AND NOT N_PZ_642 AND u2/_sub0000(6)));

    u2/Msub__sub0000__or0003 <= ((NOT rx_out(3) AND u2/_sub0000(3))
    	OR (u2/cnt_reg(3) AND N_PZ_695));

    u2/Msub__sub0000__or0006 <= ((NOT rx_out(6) AND u2/cnt_reg(6))
    	OR (NOT rx_out(5) AND u2/_sub0000(5) AND NOT N_PZ_789)
    	OR (u2/cnt_reg(5) AND N_PZ_643 AND NOT N_PZ_789));

    u2/SF17 <= (rx_out(7) AND NOT u2/cnt_reg(7));

    u2/_mux0000 <= ((u2/cnt_catch(7))
    	OR (u2/cnt_catch(2) AND u2/cnt_catch(5) AND
    	u2/cnt_catch(6))
    	OR (u2/cnt_catch(3) AND u2/cnt_catch(5) AND
    	u2/cnt_catch(6))
    	OR (u2/cnt_catch(4) AND u2/cnt_catch(5) AND
    	u2/cnt_catch(6))
    	OR (NOT u2/cnt_catch(2) AND NOT u2/cnt_catch(3) AND
    	NOT u2/cnt_catch(4) AND NOT u2/cnt_catch(5) AND NOT u2/cnt_catch(6) AND
    	NOT u2/cnt_catch(0) AND NOT u2/cnt_catch(1)));

    u2/_sub0000(3) <= rx_out(3)
    	XOR ((u2/cnt_reg(3) AND NOT N_PZ_695)
    	OR (NOT u2/cnt_reg(3) AND N_PZ_695));

    u2/_sub0000(5) <= rx_out(5)
    	XOR ((u2/cnt_reg(5) AND NOT N_PZ_643)
    	OR (NOT u2/cnt_reg(5) AND N_PZ_643));

    u2/_sub0000(6) <= ((NOT rx_out(6) AND NOT u2/Msub__sub0000__or0006)
    	OR (u2/cnt_reg(6) AND NOT u2/Msub__sub0000__or0006)
    	OR (NOT rx_out(5) AND NOT u2/Msub__sub0000__or0006 AND
    	u2/_sub0000(5))
    	OR (u2/cnt_reg(5) AND NOT u2/Msub__sub0000__or0006 AND
    	N_PZ_643)
    	OR (NOT rx_out(6) AND NOT rx_out(5) AND u2/cnt_reg(6) AND
    	u2/_sub0000(5))
    	OR (NOT rx_out(6) AND u2/cnt_reg(6) AND u2/cnt_reg(5) AND
    	N_PZ_643));

    FDCPE_u2/cnt_catch0: FDCPE port map (u2/cnt_catch(0),rx_out(0),data_ready,'0','0',NOT u2/cnt_catch_cmp_le0000);

    FDCPE_u2/cnt_catch1: FDCPE port map (u2/cnt_catch(1),rx_out(1),data_ready,'0','0',NOT u2/cnt_catch_cmp_le0000);

    FDCPE_u2/cnt_catch2: FDCPE port map (u2/cnt_catch(2),rx_out(2),data_ready,'0','0',NOT u2/cnt_catch_cmp_le0000);

    FDCPE_u2/cnt_catch3: FDCPE port map (u2/cnt_catch(3),rx_out(3),data_ready,'0','0',NOT u2/cnt_catch_cmp_le0000);

    FDCPE_u2/cnt_catch4: FDCPE port map (u2/cnt_catch(4),rx_out(4),data_ready,'0','0',NOT u2/cnt_catch_cmp_le0000);

    FDCPE_u2/cnt_catch5: FDCPE port map (u2/cnt_catch(5),rx_out(5),data_ready,'0','0',NOT u2/cnt_catch_cmp_le0000);

    FDCPE_u2/cnt_catch6: FDCPE port map (u2/cnt_catch(6),rx_out(6),data_ready,'0','0',NOT u2/cnt_catch_cmp_le0000);

    FDCPE_u2/cnt_catch7: FDCPE port map (u2/cnt_catch(7),rx_out(7),data_ready,'0','0',NOT u2/cnt_catch_cmp_le0000);

    u2/cnt_catch_cmp_le0000 <= (rx_out(6) AND rx_out(7))
    	XOR (rx_out(6) AND rx_out(7) AND NOT rx_out(3) AND NOT rx_out(4) AND
    	NOT rx_out(5));

    FTCPE_u2/cnt_reg0: FTCPE port map (u2/cnt_reg(0),u2/cnt_reg_T(0),clk_div(13),u2/cnt_reg_CLR(0),'0','1');
    u2/cnt_reg_T(0) <= (u2/sensor_set_cmp_ne0000 AND NOT N_PZ_1032);
    u2/cnt_reg_CLR(0) <= (sensor_en AND u2/sensor_set);

    FTCPE_u2/cnt_reg1: FTCPE port map (u2/cnt_reg(1),u2/cnt_reg_T(1),clk_div(13),u2/cnt_reg_CLR(1),'0','1');
    u2/cnt_reg_T(1) <= ((u2/forward_backward AND u2/cnt_reg(0) AND
    	u2/sensor_set_cmp_ne0000 AND NOT N_PZ_1032)
    	OR (NOT u2/forward_backward AND NOT u2/cnt_reg(0) AND
    	u2/sensor_set_cmp_ne0000 AND NOT N_PZ_1032));
    u2/cnt_reg_CLR(1) <= (sensor_en AND u2/sensor_set);

    FTCPE_u2/cnt_reg2: FTCPE port map (u2/cnt_reg(2),u2/cnt_reg_T(2),clk_div(13),u2/cnt_reg_CLR(2),'0','1');
    u2/cnt_reg_T(2) <= NOT ((NOT N_PZ_977 AND NOT N_PZ_1003));
    u2/cnt_reg_CLR(2) <= (sensor_en AND u2/sensor_set);

    FTCPE_u2/cnt_reg3: FTCPE port map (u2/cnt_reg(3),u2/cnt_reg_T(3),clk_div(13),u2/cnt_reg_CLR(3),'0','1');
    u2/cnt_reg_T(3) <= NOT (((u2/cnt_reg(2) AND NOT N_PZ_977)
    	OR (NOT u2/cnt_reg(2) AND NOT N_PZ_1003)
    	OR (u2/cnt_reg(7) AND NOT u2/cnt_reg(4) AND u2/cnt_reg(2) AND
    	NOT u2/cnt_reg(3) AND u2/cnt_reg(6) AND NOT u2/cnt_reg(5))
    	OR (NOT u2/cnt_reg(7) AND NOT u2/cnt_reg(4) AND NOT u2/cnt_reg(2) AND
    	NOT u2/cnt_reg(3) AND NOT u2/cnt_reg(6) AND NOT u2/cnt_reg(5))));
    u2/cnt_reg_CLR(3) <= (sensor_en AND u2/sensor_set);

    FTCPE_u2/cnt_reg4: FTCPE port map (u2/cnt_reg(4),u2/cnt_reg_T(4),clk_div(13),u2/cnt_reg_CLR(4),'0','1');
    u2/cnt_reg_T(4) <= (NOT u2/cnt_reg(2) AND NOT u2/cnt_reg(3) AND N_PZ_1003)
    	XOR ((u2/cnt_reg(2) AND N_PZ_977 AND u2/cnt_reg(3))
    	OR (NOT u2/cnt_reg(7) AND NOT u2/cnt_reg(4) AND NOT u2/cnt_reg(2) AND
    	NOT u2/cnt_reg(3) AND NOT u2/cnt_reg(6) AND NOT u2/cnt_reg(5) AND N_PZ_1003));
    u2/cnt_reg_CLR(4) <= (sensor_en AND u2/sensor_set);

    FTCPE_u2/cnt_reg5: FTCPE port map (u2/cnt_reg(5),u2/cnt_reg_T(5),clk_div(13),u2/cnt_reg_CLR(5),'0','1');
    u2/cnt_reg_T(5) <= ((u2/cnt_reg(4) AND u2/cnt_reg(2) AND N_PZ_977 AND
    	u2/cnt_reg(3))
    	OR (u2/cnt_reg(7) AND NOT u2/cnt_reg(4) AND NOT u2/cnt_reg(2) AND
    	NOT u2/cnt_reg(3) AND N_PZ_1003)
    	OR (NOT u2/cnt_reg(4) AND NOT u2/cnt_reg(2) AND NOT u2/cnt_reg(3) AND
    	u2/cnt_reg(6) AND N_PZ_1003)
    	OR (NOT u2/cnt_reg(4) AND NOT u2/cnt_reg(2) AND NOT u2/cnt_reg(3) AND
    	u2/cnt_reg(5) AND N_PZ_1003));
    u2/cnt_reg_CLR(5) <= (sensor_en AND u2/sensor_set);

    FTCPE_u2/cnt_reg6: FTCPE port map (u2/cnt_reg(6),u2/cnt_reg_T(6),clk_div(13),u2/cnt_reg_CLR(6),'0','1');
    u2/cnt_reg_T(6) <= ((u2/cnt_reg(4) AND u2/cnt_reg(2) AND N_PZ_977 AND
    	u2/cnt_reg(3) AND u2/cnt_reg(5))
    	OR (NOT u2/cnt_reg(4) AND NOT u2/cnt_reg(2) AND NOT u2/cnt_reg(3) AND
    	NOT u2/cnt_reg(5) AND N_PZ_1003)
    	OR (u2/cnt_reg(7) AND NOT u2/cnt_reg(4) AND u2/cnt_reg(2) AND
    	N_PZ_977 AND NOT u2/cnt_reg(3) AND u2/cnt_reg(6) AND NOT u2/cnt_reg(5)));
    u2/cnt_reg_CLR(6) <= (sensor_en AND u2/sensor_set);

    FTCPE_u2/cnt_reg7: FTCPE port map (u2/cnt_reg(7),u2/cnt_reg_T(7),clk_div(13),u2/cnt_reg_CLR(7),'0','1');
    u2/cnt_reg_T(7) <= ((u2/cnt_reg(4) AND u2/cnt_reg(2) AND N_PZ_977 AND
    	u2/cnt_reg(3) AND u2/cnt_reg(6) AND u2/cnt_reg(5))
    	OR (NOT u2/cnt_reg(4) AND NOT u2/cnt_reg(2) AND NOT u2/cnt_reg(3) AND
    	NOT u2/cnt_reg(6) AND NOT u2/cnt_reg(5) AND N_PZ_1003)
    	OR (u2/cnt_reg(7) AND NOT u2/cnt_reg(4) AND u2/cnt_reg(2) AND
    	N_PZ_977 AND NOT u2/cnt_reg(3) AND u2/cnt_reg(6) AND NOT u2/cnt_reg(5)));
    u2/cnt_reg_CLR(7) <= (sensor_en AND u2/sensor_set);

    FDCPE_u2/forward_backward: FDCPE port map (u2/forward_backward,u2/forward_backward_D,data_ready,u2/forward_backward_CLR,u2/forward_backward_PRE,'1');
    u2/forward_backward_D <= NOT (((NOT u2/forward_backward AND u2/cnt_catch_cmp_le0000)
    	OR (NOT u2/cnt_catch_cmp_le0000 AND sensor_en AND
    	u2/_mux0000)
    	OR (NOT u2/cnt_catch_cmp_le0000 AND NOT sensor_en AND
    	NOT u2/forward_backward_mux000876 AND N_PZ_762)
    	OR (NOT rx_out(7) AND NOT sensor_en AND u2/cnt_reg(7) AND
    	NOT u2/forward_backward_mux000876)
    	OR (NOT rx_out(6) AND NOT sensor_en AND u2/cnt_reg(6) AND
    	NOT u2/forward_backward_mux000876 AND NOT u2/SF17)
    	OR (NOT u2/cnt_catch_cmp_le0000 AND NOT rx_out(5) AND NOT sensor_en AND
    	u2/cnt_reg(5) AND NOT u2/forward_backward_mux000876 AND NOT N_PZ_789 AND
    	NOT u2/SF17)
    	OR (NOT u2/cnt_catch_cmp_le0000 AND NOT rx_out(3) AND NOT sensor_en AND
    	u2/cnt_reg(3) AND NOT u2/forward_backward_mux000876 AND NOT N_PZ_789 AND
    	NOT u2/SF17 AND NOT N_PZ_971)
    	OR (NOT u2/cnt_catch_cmp_le0000 AND NOT rx_out(4) AND NOT sensor_en AND
    	u2/cnt_reg(4) AND NOT u2/forward_backward_mux000876 AND NOT N_PZ_789 AND
    	NOT u2/SF17 AND NOT N_PZ_971)
    	OR (NOT u2/cnt_catch_cmp_le0000 AND NOT sensor_en AND
    	u2/cnt_reg(2) AND NOT rx_out(2) AND NOT u2/forward_backward_mux000876 AND
    	NOT N_PZ_789 AND NOT u2/SF17 AND NOT N_PZ_971)
    	OR (NOT u2/cnt_catch_cmp_le0000 AND NOT sensor_en AND
    	u2/cnt_reg(0) AND u2/cnt_reg(1) AND NOT u2/forward_backward_mux000876 AND
    	N_PZ_904 AND NOT N_PZ_789 AND NOT u2/SF17 AND NOT N_PZ_971)
    	OR (NOT u2/cnt_catch_cmp_le0000 AND NOT sensor_en AND
    	u2/cnt_reg(0) AND NOT rx_out(1) AND NOT u2/forward_backward_mux000876 AND
    	N_PZ_904 AND NOT N_PZ_789 AND NOT u2/SF17 AND NOT N_PZ_971)
    	OR (NOT u2/cnt_catch_cmp_le0000 AND NOT sensor_en AND
    	u2/cnt_reg(1) AND NOT rx_out(0) AND NOT u2/forward_backward_mux000876 AND
    	N_PZ_904 AND NOT N_PZ_789 AND NOT u2/SF17 AND NOT N_PZ_971)
    	OR (NOT u2/cnt_catch_cmp_le0000 AND NOT sensor_en AND
    	u2/cnt_reg(1) AND NOT rx_out(1) AND NOT u2/forward_backward_mux000876 AND
    	N_PZ_904 AND NOT N_PZ_789 AND NOT u2/SF17 AND NOT N_PZ_971)
    	OR (NOT u2/cnt_catch_cmp_le0000 AND NOT sensor_en AND NOT rx_out(0) AND
    	NOT rx_out(1) AND NOT u2/forward_backward_mux000876 AND N_PZ_904 AND
    	NOT N_PZ_789 AND NOT u2/SF17 AND NOT N_PZ_971)));
    u2/forward_backward_CLR <= (sensor_en AND u2/_mux0000);
    u2/forward_backward_PRE <= (sensor_en AND NOT u2/_mux0000);

    u2/forward_backward_mux000876 <= ((NOT rx_out(7) AND u2/cnt_reg(7) AND N_PZ_762)
    	OR (NOT rx_out(6) AND u2/cnt_reg(6) AND N_PZ_762 AND NOT u2/SF17)
    	OR (N_PZ_762 AND N_PZ_643 AND NOT N_PZ_789 AND NOT u2/SF17)
    	OR (NOT rx_out(5) AND u2/cnt_reg(5) AND N_PZ_762 AND NOT N_PZ_789 AND
    	NOT u2/SF17));

    FDCPE_u2/now_ST_FFd1: FDCPE port map (u2/now_ST_FFd1,u2/now_ST_FFd1_D,clk_div(13),'0','0','1');
    u2/now_ST_FFd1_D <= ((NOT N_PZ_967 AND u2/now_ST_FFd1)
    	OR (u2/now_ST_FFd3 AND NOT u2/forward_backward AND N_PZ_967 AND
    	NOT u2/now_ST_FFd2 AND NOT u2/now_ST_FFd4)
    	OR (NOT u2/now_ST_FFd3 AND u2/forward_backward AND N_PZ_967 AND
    	u2/now_ST_FFd2 AND NOT u2/now_ST_FFd4 AND NOT u2/now_ST_FFd1));

    FTCPE_u2/now_ST_FFd2: FTCPE port map (u2/now_ST_FFd2,u2/now_ST_FFd2_T,clk_div(13),'0','0','1');
    u2/now_ST_FFd2_T <= ((NOT u2/forward_backward AND N_PZ_967 AND NOT u2/now_ST_FFd2 AND
    	u2/now_ST_FFd1)
    	OR (u2/now_ST_FFd3 AND NOT u2/forward_backward AND N_PZ_967 AND
    	NOT u2/now_ST_FFd4 AND NOT u2/now_ST_FFd1)
    	OR (NOT u2/now_ST_FFd3 AND u2/forward_backward AND N_PZ_967 AND
    	NOT u2/now_ST_FFd2 AND u2/now_ST_FFd4)
    	OR (NOT u2/now_ST_FFd3 AND u2/forward_backward AND N_PZ_967 AND
    	u2/now_ST_FFd2 AND NOT u2/now_ST_FFd4 AND u2/now_ST_FFd1));

    FDCPE_u2/now_ST_FFd3: FDCPE port map (u2/now_ST_FFd3,u2/now_ST_FFd3_D,clk_div(13),'0','0','1');
    u2/now_ST_FFd3_D <= NOT (((NOT u2/now_ST_FFd3 AND NOT N_PZ_967)
    	OR (NOT u2/now_ST_FFd3 AND NOT u2/now_ST_FFd4 AND NOT u2/now_ST_FFd1)
    	OR (NOT u2/forward_backward AND N_PZ_967 AND NOT u2/now_ST_FFd4)
    	OR (NOT u2/now_ST_FFd3 AND u2/forward_backward AND
    	u2/now_ST_FFd2 AND NOT u2/now_ST_FFd1)
    	OR (u2/now_ST_FFd3 AND u2/forward_backward AND N_PZ_967 AND
    	u2/now_ST_FFd4 AND NOT u2/now_ST_FFd1)));

    FDCPE_u2/now_ST_FFd4: FDCPE port map (u2/now_ST_FFd4,u2/now_ST_FFd4_D,clk_div(13),'0','0','1');
    u2/now_ST_FFd4_D <= NOT (((NOT N_PZ_967 AND NOT u2/now_ST_FFd4)
    	OR (u2/now_ST_FFd3 AND NOT u2/forward_backward AND N_PZ_967 AND
    	u2/now_ST_FFd4)
    	OR (u2/now_ST_FFd3 AND NOT u2/forward_backward AND
    	NOT u2/now_ST_FFd2 AND NOT u2/now_ST_FFd4)
    	OR (NOT u2/now_ST_FFd3 AND u2/forward_backward AND N_PZ_967 AND
    	u2/now_ST_FFd4)
    	OR (NOT u2/now_ST_FFd3 AND u2/forward_backward AND
    	u2/now_ST_FFd2 AND NOT u2/now_ST_FFd4)
    	OR (NOT u2/now_ST_FFd3 AND u2/now_ST_FFd2 AND NOT u2/now_ST_FFd4 AND
    	u2/now_ST_FFd1)));

    FDCPE_u2/run: FDCPE port map (u2/run,u2/run_D,clk_div(13),'0','0','1');
    u2/run_D <= ((N_PZ_967)
    	OR (sensor_en AND u2/run AND u2/sensor_set));

    FTCPE_u2/sensor_set: FTCPE port map (u2/sensor_set,u2/sensor_set_T,clk_div(13),u2/sensor_set_CLR,'0','1');
    u2/sensor_set_T <= (NOT u2/sensor_set_cmp_ne0000 AND NOT N_PZ_1032 AND
    	NOT u2/sensor_set);
    u2/sensor_set_CLR <= (sensor_en AND u2/sensor_set);

    u2/sensor_set_cmp_ne0000 <= ((u2/cnt_reg(7) AND NOT u2/cnt_catch(7))
    	OR (NOT u2/cnt_reg(7) AND u2/cnt_catch(7))
    	OR (u2/cnt_reg(4) AND NOT u2/cnt_catch(4))
    	OR (NOT u2/cnt_reg(4) AND u2/cnt_catch(4))
    	OR (u2/cnt_reg(2) AND NOT u2/cnt_catch(2))
    	OR (NOT u2/cnt_reg(2) AND u2/cnt_catch(2))
    	OR (u2/cnt_reg(0) AND NOT u2/cnt_catch(0))
    	OR (NOT u2/cnt_reg(0) AND u2/cnt_catch(0))
    	OR (u2/cnt_reg(3) AND NOT u2/cnt_catch(3))
    	OR (NOT u2/cnt_reg(3) AND u2/cnt_catch(3))
    	OR (u2/cnt_reg(6) AND NOT u2/cnt_catch(6))
    	OR (NOT u2/cnt_reg(6) AND u2/cnt_catch(6))
    	OR (u2/cnt_reg(5) AND NOT u2/cnt_catch(5))
    	OR (NOT u2/cnt_reg(5) AND u2/cnt_catch(5))
    	OR (u2/cnt_reg(1) AND NOT u2/cnt_catch(1))
    	OR (NOT u2/cnt_reg(1) AND u2/cnt_catch(1)));

    FTCPE_u3/cd0: FTCPE port map (u3/cd(0),u3/khertz_en,clk,'0','0','1');

    FTCPE_u3/cd1: FTCPE port map (u3/cd(1),u3/cd_T(1),clk,'0','0','1');
    u3/cd_T(1) <= (u3/cd(0) AND u3/khertz_en);

    FDCPE_u3/curr0: FDCPE port map (u3/curr(0),u3/curr_D(0),clk,'0','0','1');
    u3/curr_D(0) <= ((NOT u3/cd(0) AND NOT u3/cd(1))
    	OR (NOT u3/cd(0) AND u4/XLXN_35 AND NOT u4/XLXN_34 AND NOT u4/XLXN_33)
    	OR (NOT u3/cd(0) AND NOT u4/XLXN_35 AND u4/XLXN_34 AND bin_deg(1))
    	OR (NOT u3/cd(0) AND NOT u4/XLXN_35 AND u4/XLXN_34 AND u4/XLXN_33)
    	OR (u3/cd(0) AND u3/cd(1) AND u4/XLXN_36 AND u4/XLXN_37 AND
    	u4/XLXN_38)
    	OR (u3/cd(0) AND u3/cd(1) AND NOT u4/XLXN_36 AND NOT u4/XLXN_37 AND
    	N_PZ_641)
    	OR (u3/cd(0) AND u3/cd(1) AND NOT u4/XLXN_36 AND NOT u4/XLXN_37 AND
    	NOT u4/XLXN_38)
    	OR (NOT u3/cd(1) AND rx_out(0) AND rx_out(1) AND
    	Mmult_bin_deg_mult0000_Mxor__index0020 AND NOT Mmult_bin_deg_mult0000__or00213)
    	OR (NOT u3/cd(1) AND rx_out(0) AND rx_out(1) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000__or00213)
    	OR (NOT u3/cd(1) AND rx_out(0) AND NOT rx_out(1) AND NOT N_PZ_689 AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0020)
    	OR (NOT u3/cd(1) AND rx_out(0) AND NOT rx_out(1) AND
    	Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000__or00213)
    	OR (NOT u3/cd(1) AND NOT rx_out(0) AND rx_out(1) AND
    	Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000__or00213)
    	OR (NOT u3/cd(1) AND NOT rx_out(0) AND rx_out(1) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND NOT N_PZ_929)
    	OR (NOT u3/cd(1) AND NOT rx_out(0) AND NOT rx_out(1) AND
    	Mmult_bin_deg_mult0000_Mxor__index0020 AND NOT Mmult_bin_deg_mult0000__or00213));

    FDCPE_u3/curr1: FDCPE port map (u3/curr(1),u3/curr_D(1),clk,'0','0','1');
    u3/curr_D(1) <= ((NOT u3/cd(0) AND NOT u3/cd(1))
    	OR (NOT u3/cd(0) AND NOT u4/XLXN_36 AND u4/XLXN_37 AND N_PZ_641)
    	OR (NOT u3/cd(1) AND NOT u4/XLXN_35 AND NOT u4/XLXN_34 AND bin_deg(1))
    	OR (u3/cd(0) AND u3/cd(1) AND NOT u4/XLXI_47/S0_or000011 AND
    	N_PZ_666 AND NOT u4/XLXN_36)
    	OR (NOT u3/cd(0) AND NOT u4/XLXN_36 AND NOT u4/XLXN_37 AND NOT N_PZ_641 AND
    	NOT u4/XLXN_38)
    	OR (NOT u3/cd(1) AND u4/XLXN_35 AND NOT u4/XLXN_34 AND NOT bin_deg(1) AND
    	NOT u4/XLXN_33)
    	OR (NOT u3/cd(1) AND NOT u4/XLXN_35 AND u4/XLXN_34 AND NOT bin_deg(1) AND
    	u4/XLXN_33)
    	OR (NOT u3/cd(0) AND u3/cd(1) AND u4/XLXN_36 AND u4/XLXN_37 AND
    	NOT N_PZ_641 AND u4/XLXN_38)
    	OR (u3/cd(0) AND u3/cd(1) AND rx_out(7) AND NOT N_PZ_624 AND
    	NOT u4/XLXN_83 AND NOT u4/XLXI_47/S0_or000011 AND NOT N_PZ_666 AND u4/XLXN_94));

    FDCPE_u3/curr2: FDCPE port map (u3/curr(2),u3/curr_D(2),clk,'0','0','1');
    u3/curr_D(2) <= ((u3/cd(0) AND NOT u3/cd(1) AND NOT u4/XLXN_35 AND NOT u4/XLXN_34 AND
    	u4/XLXN_33)
    	OR (u3/cd(0) AND NOT u3/cd(1) AND NOT u4/XLXN_35 AND bin_deg(1) AND
    	u4/XLXN_33)
    	OR (NOT u3/cd(0) AND u3/cd(1) AND NOT u4/XLXN_36 AND u4/XLXN_37 AND
    	NOT u4/XLXN_38)
    	OR (NOT u3/cd(0) AND u3/cd(1) AND NOT u4/XLXN_36 AND N_PZ_641 AND
    	NOT u4/XLXN_38)
    	OR (u3/cd(0) AND u3/cd(1) AND rx_out(7) AND NOT N_PZ_624 AND
    	NOT u4/XLXN_83 AND N_PZ_666)
    	OR (u3/cd(0) AND u3/cd(1) AND rx_out(7) AND NOT N_PZ_624 AND
    	NOT u4/XLXN_83 AND NOT u4/XLXN_94)
    	OR (u3/cd(0) AND NOT u3/cd(1) AND u4/XLXN_35 AND NOT u4/XLXN_34 AND
    	NOT bin_deg(1) AND NOT u4/XLXN_33)
    	OR (NOT u3/cd(0) AND u3/cd(1) AND u4/XLXN_36 AND u4/XLXN_37 AND
    	NOT N_PZ_641 AND u4/XLXN_38));

    FDCPE_u3/curr3: FDCPE port map (u3/curr(3),u3/curr_D(3),clk,'0','0','1');
    u3/curr_D(3) <= ((NOT u3/cd(0) AND NOT u3/cd(1))
    	OR (NOT u3/cd(0) AND u4/XLXN_36 AND u4/XLXN_37 AND N_PZ_641 AND
    	u4/XLXN_38)
    	OR (NOT u3/cd(0) AND NOT u4/XLXN_36 AND NOT u4/XLXN_37 AND NOT N_PZ_641 AND
    	u4/XLXN_38)
    	OR (NOT u3/cd(1) AND u4/XLXN_35 AND NOT u4/XLXN_34 AND bin_deg(1) AND
    	NOT u4/XLXN_33)
    	OR (NOT u3/cd(1) AND NOT u4/XLXN_35 AND u4/XLXN_34 AND NOT bin_deg(1) AND
    	NOT u4/XLXN_33));

    FDCPE_u3/dp: FDCPE port map (u3/dp,NOT '0',clk,'0','0','1');

    FTCPE_u3/khertz_count0: FTCPE port map (u3/khertz_count(0),u3/khertz_count_T(0),clk,'0','0','1');
    u3/khertz_count_T(0) <= NOT (((NOT u3/mhertz_en)
    	OR (NOT u3/khertz_count(0) AND NOT u3/khertz_count(1) AND
    	NOT u3/khertz_count(2) AND u3/khertz_count(3) AND NOT u3/khertz_count(4) AND
    	u3/khertz_count(5) AND u3/khertz_count(6) AND u3/khertz_count(7) AND
    	u3/khertz_count(8) AND u3/khertz_count(9))));

    FTCPE_u3/khertz_count1: FTCPE port map (u3/khertz_count(1),u3/khertz_count_T(1),clk,'0','0','1');
    u3/khertz_count_T(1) <= (u3/khertz_count(0) AND u3/mhertz_en);

    FTCPE_u3/khertz_count2: FTCPE port map (u3/khertz_count(2),u3/khertz_count_T(2),clk,'0','0','1');
    u3/khertz_count_T(2) <= (u3/khertz_count(0) AND u3/khertz_count(1) AND
    	u3/mhertz_en);

    FTCPE_u3/khertz_count3: FTCPE port map (u3/khertz_count(3),u3/khertz_count_T(3),clk,'0','0','1');
    u3/khertz_count_T(3) <= ((u3/khertz_count(0) AND u3/khertz_count(1) AND
    	u3/mhertz_en AND u3/khertz_count(2))
    	OR (NOT u3/khertz_count(0) AND NOT u3/khertz_count(1) AND
    	u3/mhertz_en AND NOT u3/khertz_count(2) AND u3/khertz_count(3) AND
    	NOT u3/khertz_count(4) AND u3/khertz_count(5) AND u3/khertz_count(6) AND
    	u3/khertz_count(7) AND u3/khertz_count(8) AND u3/khertz_count(9)));

    FTCPE_u3/khertz_count4: FTCPE port map (u3/khertz_count(4),u3/khertz_count_T(4),clk,'0','0','1');
    u3/khertz_count_T(4) <= (u3/khertz_count(0) AND u3/khertz_count(1) AND
    	u3/mhertz_en AND u3/khertz_count(2) AND u3/khertz_count(3));

    FDCPE_u3/khertz_count5: FDCPE port map (u3/khertz_count(5),u3/khertz_count_D(5),clk,'0','0','1');
    u3/khertz_count_D(5) <= NOT (((NOT u3/mhertz_en AND NOT u3/khertz_count(5))
    	OR (NOT u3/khertz_count(3) AND NOT u3/khertz_count(5))
    	OR (NOT u3/khertz_count(5) AND NOT N_PZ_936)
    	OR (u3/mhertz_en AND u3/khertz_count(3) AND
    	u3/khertz_count(5) AND N_PZ_936)
    	OR (NOT u3/khertz_count(0) AND NOT u3/khertz_count(1) AND
    	u3/mhertz_en AND NOT u3/khertz_count(2) AND u3/khertz_count(3) AND
    	NOT u3/khertz_count(4) AND u3/khertz_count(6) AND u3/khertz_count(7) AND
    	u3/khertz_count(8) AND u3/khertz_count(9))));

    FDCPE_u3/khertz_count6: FDCPE port map (u3/khertz_count(6),u3/khertz_count_D(6),clk,'0','0','1');
    u3/khertz_count_D(6) <= NOT (((NOT u3/mhertz_en AND NOT u3/khertz_count(6))
    	OR (NOT u3/khertz_count(3) AND NOT u3/khertz_count(6))
    	OR (NOT u3/khertz_count(5) AND NOT u3/khertz_count(6))
    	OR (NOT u3/khertz_count(6) AND NOT N_PZ_936)
    	OR (u3/mhertz_en AND u3/khertz_count(3) AND
    	u3/khertz_count(5) AND u3/khertz_count(6) AND N_PZ_936)
    	OR (NOT u3/khertz_count(0) AND NOT u3/khertz_count(1) AND
    	u3/mhertz_en AND NOT u3/khertz_count(2) AND u3/khertz_count(3) AND
    	NOT u3/khertz_count(4) AND u3/khertz_count(5) AND u3/khertz_count(7) AND
    	u3/khertz_count(8) AND u3/khertz_count(9))));

    FDCPE_u3/khertz_count7: FDCPE port map (u3/khertz_count(7),u3/khertz_count_D(7),clk,'0','0','1');
    u3/khertz_count_D(7) <= NOT (((NOT u3/mhertz_en AND NOT u3/khertz_count(7))
    	OR (NOT u3/khertz_count(3) AND NOT u3/khertz_count(7))
    	OR (NOT u3/khertz_count(5) AND NOT u3/khertz_count(7))
    	OR (NOT u3/khertz_count(6) AND NOT u3/khertz_count(7))
    	OR (NOT u3/khertz_count(7) AND NOT N_PZ_936)
    	OR (u3/mhertz_en AND u3/khertz_count(3) AND
    	u3/khertz_count(5) AND u3/khertz_count(6) AND u3/khertz_count(7) AND
    	N_PZ_936)
    	OR (NOT u3/khertz_count(0) AND NOT u3/khertz_count(1) AND
    	u3/mhertz_en AND NOT u3/khertz_count(2) AND u3/khertz_count(3) AND
    	NOT u3/khertz_count(4) AND u3/khertz_count(5) AND u3/khertz_count(6) AND
    	u3/khertz_count(8) AND u3/khertz_count(9))));

    FTCPE_u3/khertz_count8: FTCPE port map (u3/khertz_count(8),u3/khertz_count_T(8),clk,'0','0','1');
    u3/khertz_count_T(8) <= ((u3/mhertz_en AND u3/khertz_count(3) AND
    	u3/khertz_count(5) AND u3/khertz_count(6) AND u3/khertz_count(7) AND
    	N_PZ_936)
    	OR (NOT u3/khertz_count(0) AND NOT u3/khertz_count(1) AND
    	u3/mhertz_en AND NOT u3/khertz_count(2) AND u3/khertz_count(3) AND
    	NOT u3/khertz_count(4) AND u3/khertz_count(5) AND u3/khertz_count(6) AND
    	u3/khertz_count(7) AND u3/khertz_count(8) AND u3/khertz_count(9)));

    FTCPE_u3/khertz_count9: FTCPE port map (u3/khertz_count(9),u3/khertz_count_T(9),clk,'0','0','1');
    u3/khertz_count_T(9) <= ((u3/mhertz_en AND u3/khertz_count(3) AND
    	u3/khertz_count(5) AND u3/khertz_count(6) AND u3/khertz_count(7) AND
    	u3/khertz_count(8) AND N_PZ_936)
    	OR (NOT u3/khertz_count(0) AND NOT u3/khertz_count(1) AND
    	u3/mhertz_en AND NOT u3/khertz_count(2) AND u3/khertz_count(3) AND
    	NOT u3/khertz_count(4) AND u3/khertz_count(5) AND u3/khertz_count(6) AND
    	u3/khertz_count(7) AND u3/khertz_count(8) AND u3/khertz_count(9)));

    FDCPE_u3/khertz_en: FDCPE port map (u3/khertz_en,u3/khertz_en_D,clk,'0','0','1');
    u3/khertz_en_D <= (NOT u3/khertz_count(0) AND NOT u3/khertz_count(1) AND
    	u3/mhertz_en AND NOT u3/khertz_count(2) AND u3/khertz_count(3) AND
    	NOT u3/khertz_count(4) AND u3/khertz_count(5) AND u3/khertz_count(6) AND
    	u3/khertz_count(7) AND u3/khertz_count(8) AND u3/khertz_count(9));

    FTCPE_u3/mhertz_count: FTCPE port map (u3/mhertz_count,'0',clk,'0','0','1');

    FDCPE_u3/mhertz_en: FDCPE port map (u3/mhertz_en,u3/mhertz_count,clk,'0','0','1');

    u4/XLXI_22/S1_or00006 <= (rx_out(7) AND NOT N_PZ_624 AND NOT u4/XLXN_83 AND
    	NOT u4/XLXI_47/S0_or000011 AND NOT N_PZ_666 AND u4/XLXN_94 AND NOT u4/XLXN_41);

    u4/XLXI_46/S1_or00007 <= ((rx_out(7) AND N_PZ_624)
    	OR (rx_out(6) AND NOT rx_out(7) AND rx_out(5) AND NOT N_PZ_624)
    	OR (rx_out(6) AND NOT rx_out(7) AND NOT N_PZ_624 AND NOT N_PZ_615)
    	OR (rx_out(6) AND NOT rx_out(7) AND NOT N_PZ_624 AND
    	Mmult_bin_deg_mult0000_Mxor__index0033 AND NOT N_PZ_604)
    	OR (rx_out(6) AND rx_out(5) AND NOT N_PZ_624 AND
    	NOT Mmult_bin_deg_mult0000__or0031 AND NOT N_PZ_615)
    	OR (rx_out(6) AND rx_out(5) AND NOT N_PZ_624 AND NOT N_PZ_615 AND
    	NOT N_PZ_604));

    u4/XLXI_47/S0_or000011 <= (rx_out(7) AND NOT N_PZ_624 AND NOT u4/XLXN_83 AND N_PZ_666 AND
    	u4/XLXN_94);

    u4/XLXN_27 <= ((bin_deg(4) AND u4/XLXN_83 AND N_PZ_604 AND
    	NOT u4/XLXI_46/S1_or00007 AND NOT u4/XLXN_81)
    	OR (bin_deg(4) AND NOT u4/XLXN_83 AND NOT N_PZ_604 AND
    	u4/XLXI_46/S1_or00007 AND NOT u4/XLXN_81)
    	OR (NOT bin_deg(4) AND NOT u4/XLXN_83 AND N_PZ_604 AND
    	u4/XLXI_46/S1_or00007 AND u4/XLXN_81)
    	OR (NOT bin_deg(4) AND NOT u4/XLXN_83 AND NOT N_PZ_604 AND
    	NOT u4/XLXI_46/S1_or00007 AND u4/XLXN_81));

    u4/XLXN_28 <= ((u4/XLXN_27)
    	OR (u4/XLXN_83 AND NOT N_PZ_666)
    	OR (N_PZ_604 AND u4/XLXI_46/S1_or00007)
    	OR (NOT bin_deg(4) AND NOT N_PZ_666 AND u4/XLXN_81)
    	OR (NOT N_PZ_604 AND NOT N_PZ_666 AND NOT u4/XLXI_46/S1_or00007)
    	OR (NOT bin_deg(4) AND u4/XLXN_83 AND NOT N_PZ_604 AND N_PZ_666));

    u4/XLXN_29 <= ((NOT bin_deg(4) AND NOT u4/XLXN_94)
    	OR (bin_deg(4) AND u4/XLXN_83 AND NOT N_PZ_666 AND NOT u4/XLXN_27)
    	OR (bin_deg(4) AND NOT u4/XLXN_83 AND NOT u4/XLXN_81 AND
    	NOT u4/XLXN_27)
    	OR (bin_deg(4) AND NOT u4/XLXN_83 AND NOT N_PZ_604 AND N_PZ_666 AND
    	NOT u4/XLXN_27));

    u4/XLXN_33 <= ((N_PZ_606 AND NOT N_PZ_641)
    	OR (NOT N_PZ_606 AND N_PZ_641));

    u4/XLXN_34 <= ((NOT bin_deg(3) AND N_PZ_606 AND u4/XLXN_41)
    	OR (bin_deg(3) AND N_PZ_606 AND NOT u4/XLXN_27 AND u4/XLXN_28)
    	OR (bin_deg(3) AND NOT N_PZ_606 AND u4/XLXN_28 AND NOT u4/XLXN_29)
    	OR (NOT bin_deg(3) AND NOT u4/XLXN_27 AND NOT u4/XLXN_28 AND
    	NOT u4/XLXN_35));

    u4/XLXN_35 <= ((bin_deg(3) AND N_PZ_606 AND u4/XLXN_27 AND u4/XLXN_28 AND
    	NOT u4/XLXN_29)
    	OR (bin_deg(3) AND NOT N_PZ_606 AND NOT u4/XLXN_27 AND NOT u4/XLXN_28 AND
    	u4/XLXN_29)
    	OR (NOT bin_deg(3) AND N_PZ_606 AND NOT u4/XLXN_27 AND NOT u4/XLXN_28 AND
    	NOT u4/XLXN_29)
    	OR (NOT bin_deg(3) AND NOT N_PZ_606 AND NOT u4/XLXN_27 AND u4/XLXN_28 AND
    	u4/XLXN_29));

    u4/XLXN_36 <= ((NOT u4/XLXI_47/S0_or000011 AND N_PZ_666 AND NOT u4/XLXN_41 AND
    	N_PZ_1022)
    	OR (rx_out(7) AND NOT N_PZ_624 AND NOT u4/XLXN_83 AND
    	NOT u4/XLXI_47/S0_or000011 AND NOT N_PZ_666 AND u4/XLXN_94 AND u4/XLXN_41 AND N_PZ_1022));

    u4/XLXN_37 <= ((NOT u4/XLXI_47/S0_or000011 AND N_PZ_1022 AND
    	NOT u4/XLXI_22/S1_or00006)
    	OR (N_PZ_666 AND NOT u4/XLXN_41 AND NOT N_PZ_1022));

    u4/XLXN_38 <= ((u4/XLXN_36 AND u4/XLXN_37)
    	OR (u4/XLXI_47/S0_or000011 AND NOT u4/XLXN_41 AND
    	NOT u4/XLXI_22/S1_or00006)
    	OR (NOT u4/XLXI_47/S0_or000011 AND N_PZ_666 AND u4/XLXN_41)
    	OR (NOT N_PZ_666 AND NOT u4/XLXN_41 AND NOT u4/XLXI_22/S1_or00006)
    	OR (rx_out(7) AND NOT N_PZ_624 AND NOT u4/XLXN_83 AND NOT N_PZ_666 AND
    	u4/XLXN_94 AND NOT u4/XLXI_22/S1_or00006));

    u4/XLXN_41 <= ((bin_deg(3) AND NOT u4/XLXN_27 AND NOT u4/XLXN_28)
    	OR (u4/XLXN_27 AND u4/XLXN_28 AND NOT u4/XLXN_29)
    	OR (NOT u4/XLXN_27 AND NOT u4/XLXN_28 AND u4/XLXN_29));

    u4/XLXN_81 <= ((rx_out(7) AND N_PZ_624)
    	OR (NOT rx_out(7) AND rx_out(5) AND NOT N_PZ_604)
    	OR (rx_out(6) AND rx_out(5) AND N_PZ_615 AND NOT N_PZ_604)
    	OR (NOT rx_out(6) AND NOT rx_out(7) AND
    	NOT Mmult_bin_deg_mult0000__or0031 AND Mmult_bin_deg_mult0000_Mxor__index0033)
    	OR (NOT rx_out(7) AND NOT Mmult_bin_deg_mult0000__or0031 AND
    	Mmult_bin_deg_mult0000_Mxor__index0033 AND NOT N_PZ_615)
    	OR (rx_out(6) AND rx_out(7) AND rx_out(5) AND NOT N_PZ_615 AND
    	NOT u4/XLXI_46/S1_or00007)
    	OR (rx_out(6) AND NOT rx_out(7) AND NOT rx_out(5) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0033 AND N_PZ_615)
    	OR (rx_out(6) AND NOT rx_out(7) AND
    	Mmult_bin_deg_mult0000_Mxor__index0033 AND N_PZ_615 AND N_PZ_604)
    	OR (rx_out(6) AND NOT N_PZ_624 AND
    	NOT Mmult_bin_deg_mult0000__or0031 AND Mmult_bin_deg_mult0000_Mxor__index0033 AND
    	NOT u4/XLXI_46/S1_or00007));

    u4/XLXN_83 <= ((NOT rx_out(6) AND rx_out(7) AND NOT rx_out(5) AND NOT N_PZ_624 AND
    	NOT N_PZ_653)
    	OR (NOT rx_out(6) AND rx_out(7) AND NOT rx_out(5) AND
    	NOT Mmult_bin_deg_mult0000_Mxor__index0033 AND N_PZ_653)
    	OR (NOT rx_out(6) AND rx_out(7) AND NOT N_PZ_624 AND
    	Mmult_bin_deg_mult0000__or0031 AND N_PZ_604));

    u4/XLXN_94 <= ((NOT bin_deg(4) AND u4/XLXN_27)
    	OR (u4/XLXN_83 AND NOT N_PZ_666)
    	OR (NOT u4/XLXN_83 AND N_PZ_666 AND NOT u4/XLXN_81)
    	OR (NOT N_PZ_604 AND N_PZ_666 AND u4/XLXN_81)
    	OR (NOT N_PZ_666 AND NOT u4/XLXI_46/S1_or00007 AND NOT u4/XLXN_81));

    Register Legend:
     FDCPE (Q,D,C,CLR,PRE,CE);
     FDDCPE (Q,D,C,CLR,PRE,CE);
     FTCPE (Q,D,C,CLR,PRE,CE);
     FTDCPE (Q,D,C,CLR,PRE,CE);
     LDCP  (Q,D,G,CLR,PRE);

    ******************************  Device Pin Out *****************************

    Device : XC2C256-7-TQ144

    Pin Signal                         Pin Signal
    No. Name                           No. Name
      1 VCC                              73 VCCIO-3.3
      2 KPR                              74 KPR
      3 KPR                              75 KPR
      4 KPR                              76 KPR
      5 KPR                              77 KPR
      6 KPR                              78 KPR
      7 KPR                              79 KPR
      8 VCCAUX                           80 KPR
      9 KPR                              81 KPR
     10 KPR                              82 KPR
     11 KPR                              83 KPR
     12 KPR                              84 VCC
     13 KPR                              85 KPR
     14 KPR                              86 KPR
     15 digit4<0>                        87 KPR
     16 digit4<1>                        88 rx_data
     17 digit4<2>                        89 GND
     18 digit4<3>                        90 GND
     19 KPR                              91 KPR
     20 KPR                              92 KPR
     21 KPR                              93 VCCIO-3.3
     22 KPR                              94 KPR
     23 rx_out<2>                        95 KPR
     24 rx_out<7>                        96 KPR
     25 KPR                              97 KPR
     26 rx_out<6>                        98 KPR
     27 VCCIO-3.3                        99 GND
     28 KPR                             100 KPR
     29 GND                             101 KPR
     30 rx_out<5>                       102 KPR
     31 KPR                             103 KPR
     32 rx_out<4>                       104 KPR
     33 KPR                             105 KPR
     34 KPR                             106 KPR
     35 rx_out<3>                       107 KPR
     36 GND                             108 GND
     37 VCC                             109 VCCIO-3.3
     38 clk                             110 KPR
     39 rx_out<1>                       111 KPR
     40 KPR                             112 KPR
     41 KPR                             113 KPR
     42 rx_out<0>                       114 KPR
     43 KPR                             115 KPR
     44 KPR                             116 KPR
     45 output_mot<0>                   117 KPR
     46 KPR                             118 KPR
     47 GND                             119 KPR
     48 output_mot<1>                   120 KPR
     49 KPR                             121 KPR
     50 output_mot<2>                   122 TDO
     51 KPR                             123 GND
     52 output_mot<3>                   124 KPR
     53 KPR                             125 sensor_en
     54 KPR                             126 seg4<0>
     55 VCCIO-3.3                       127 VCCIO-3.3
     56 KPR                             128 KPR
     57 KPR                             129 seg4<1>
     58 KPR                             130 KPR
     59 KPR                             131 seg4<2>
     60 KPR                             132 KPR
     61 KPR                             133 seg4<3>
     62 GND                             134 KPR
     63 TDI                             135 seg4<4>
     64 KPR                             136 KPR
     65 TMS                             137 seg4<5>
     66 KPR                             138 KPR
     67 TCK                             139 seg4<6>
     68 KPR                             140 KPR
     69 KPR                             141 VCCIO-3.3
     70 KPR                             142 seg4<7>
     71 KPR                             143 KPR
     72 GND                             144 GND

    Legend :  NC  = Not Connected, unbonded pin
            PGND  = Unused I/O configured as additional Ground pin
             KPR  = Unused I/O with weak keeper (leave unconnected)
             WPU  = Unused I/O with weak pull up (leave unconnected)
             TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
             VCC  = Dedicated Power Pin
          VCCAUX  = Power supply for JTAG pins
       VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
       VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
       VCCIO-1.8  = I/O supply voltage for LVCMOS18
       VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
            VREF  = Reference voltage for indicated input standard
           *VREF  = Reference voltage pin selected by software
             GND  = Dedicated Ground Pin
             TDI  = Test Data In, JTAG pin
             TDO  = Test Data Out, JTAG pin
             TCK  = Test Clock, JTAG pin
             TMS  = Test Mode Select, JTAG pin
      PROHIBITED  = User reserved pin
    ****************************  Compiler Options  ****************************

    Following is a list of all global compiler options used by the fitter run.

    Device(s) Specified                         : xc2c256-7-TQ144
    Optimization Method                         : DENSITY
    Multi-Level Logic Optimization              : ON
    Ignore Timing Specifications                : OFF
    Default Register Power Up Value             : LOW
    Keep User Location Constraints              : ON
    What-You-See-Is-What-You-Get                : OFF
    Exhaustive Fitting                          : OFF
    Keep Unused Inputs                          : OFF
    Slew Rate                                   : FAST
    Set Unused I/O Pin Termination              : KEEPER
    Global Clock Optimization                   : ON
    Global Set/Reset Optimization               : ON
    Global Ouput Enable Optimization            : ON
    Enable Input Registers                      : ON
    Function Block Fan-in Limit                 : 38
    Use DATA_GATE Attribute                     : ON
    Set Tristate Outputs to Termination Mode    : KEEPER
    Default Voltage Standard for All Outputs    : LVCMOS18
    Input Limit                                 : 32
    Pterm Limit                                 : 28