### Errors and Warnings

There are 0 error(s), 2 warning(s), and 0 information.

[Warning]:INFO:Cpld - Inferring BUFG constraint for signal 'clk' based upon the LOC constraint 'P38'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
[Warning]:Cpld:945 - The component 'u4/XLXI_40' has no outputs and will be deleted.