//---------------------------------------------------------------------
//               Copyright(c) Virage Logic Corporation.
//     All Rights reserved - Unpublished -rights reserved under
//     the Copyright laws of the United States of America.
//
//  U.S. Patents: 7,093,156 B1 and 7,406,620 B2 (and more pending).
//
//  This file includes the Confidential information of Virage Logic
//  and AMI.
//  The receiver of this Confidential Information shall not disclose
//  it to any third party and shall protect its confidentiality by
//  using the same degree of care, but not less then a reasonable
//  degree of care, as the receiver uses to protect receiver's own
//  Confidential Information.
//  Licensee acknowledges and agrees that all output generated for
//  Licensee by Virage Logic as described in the pertinent Program
//  Schedule(s), or generated by Licensee through use of any Compiler
//  licensed hereunder contains information that complies with the
//  Virtual Component Identification Physical Tagging Standard (VCID)
//  as maintained by the Virtual Socket Interface Alliance (VSIA).
//  Such information may be expressed in GDSII Layer 63 or other such
//  layer designated by the VSIA, hardware definition languages, or
//  other formats.  Licensee is not authorized to alter or change any
//  such information.
//
//                    Virage Logic Corporation.
//                    47100 Bayside Pkwy
//                    Fremont , California 94538.
//
//---------------------------------------------------------------------
//
//  Software           : Rev: 6.8.1 (build REL-6-8-1-2010-04-08)
//  Library Format     : Rev: 1.05.00
//  Compiler Name      : ai35uass1p11asdsr512sa07
//  Platform           : Linux2.6.18-238.el5
//                     : #1 SMP Sun Dec 19 14:22:44 EST 2010x86_64
//  Date of Generation : Mon Jun 03 07:03:51 MDT 2013
//
//---------------------------------------------------------------------
//   --------------------------------------------------------------
//                       Template Revision : 3.6.1
//   --------------------------------------------------------------
//                      * Synchronous, 1-Port SRAM *
//                      * Verilog Behavioral Model *
//                THIS IS A SYNCHRONOUS 1-PORT MEMORY MODEL
//
//   Memory Name:spram512x22cm4Mhz10
//   Memory Size:512 words x 22 bits
//
//                               PORT NAME
//                               ---------
//               Output Ports
//                                   Q[21:0]
//                                   QM
//               Input Ports:
//                                   ADR[8:0]
//                                   D[21:0]
//                                   WE
//                                   ME
//                                   CLK
//                                   AWT
//                                   TADR[8:0]
//                                   TD[21:0]
//                                   TWE
//                                   TME
//                                   TCLK
//                                   BISTE
//                                   RM[3:0]
//                                   RME

`resetall
`timescale 1 ns / 1 ps
`celldefine
`ifdef verifault // for fault simulation purpose
`suppress_faults
`enable_portfaults
`endif

`define True    1'b1
`define False   1'b0

`define VIRAGE_FAST_VERILOG


module spram512x22cm4Mhz10 ( Q, QM, ADR, D, WE, ME, CLK, AWT, TADR, TD, TWE, TME, TCLK, BISTE, RM, RME);

output  [21:0] Q;
output QM;
input  [8:0] ADR;
input  [21:0] D;
input WE;
input ME;
input CLK;
input AWT;
input  [8:0] TADR;
input  [21:0] TD;
input TWE;
input TME;
input TCLK;
input BISTE;
input  [3:0] RM;
input RME;


// Local registers, wires, etc

`ifdef MEM_CHECK_OFF
parameter MES_ALL = "OFF";
`else
parameter MES_ALL = "ON";
`endif // MEM_CHECK_OFF

`ifdef VIRAGE_IGNORE_SAME_ADDR_MSG
parameter debug_mode = 0;
`else
parameter debug_mode = 1;
`endif // VIRAGE_IGNORE_SAME_ADDR_MSG


`ifdef VIRAGE_FAST_VERILOG
`else
reg notif_adr;
reg notif_d;
reg notif_we;
reg notif_me;
reg notif_clk;
reg notif_biste;
reg notif_rm;
reg notif_rme;
`endif // VIRAGE_FAST_VERILOG

reg  [8 : 0 ] ADR_pre;
reg  ME_pre;
reg  WE_pre;

reg WE_tmp;
reg [8:0] ADR_tmp;
reg [21:0] D_tmp;
reg ME_tmp;
reg CLK_tmp;




`ifdef VIRAGE_FAST_VERILOG
wire [21:0] Q_buf;
assign Q[0] = Q_buf[0];
assign Q[1] = Q_buf[1];
assign Q[2] = Q_buf[2];
assign Q[3] = Q_buf[3];
assign Q[4] = Q_buf[4];
assign Q[5] = Q_buf[5];
assign Q[6] = Q_buf[6];
assign Q[7] = Q_buf[7];
assign Q[8] = Q_buf[8];
assign Q[9] = Q_buf[9];
assign Q[10] = Q_buf[10];
assign Q[11] = Q_buf[11];
assign Q[12] = Q_buf[12];
assign Q[13] = Q_buf[13];
assign Q[14] = Q_buf[14];
assign Q[15] = Q_buf[15];
assign Q[16] = Q_buf[16];
assign Q[17] = Q_buf[17];
assign Q[18] = Q_buf[18];
assign Q[19] = Q_buf[19];
assign Q[20] = Q_buf[20];
assign Q[21] = Q_buf[21];
wire QM_buf;
assign  QM = QM_buf;
wire [8:0] ADR_buf;
assign  ADR_buf[0] =  ADR[0];
assign  ADR_buf[1] =  ADR[1];
assign  ADR_buf[2] =  ADR[2];
assign  ADR_buf[3] =  ADR[3];
assign  ADR_buf[4] =  ADR[4];
assign  ADR_buf[5] =  ADR[5];
assign  ADR_buf[6] =  ADR[6];
assign  ADR_buf[7] =  ADR[7];
assign  ADR_buf[8] =  ADR[8];
wire [21:0] D_buf;
assign  D_buf[0] =  D[0];
assign  D_buf[1] =  D[1];
assign  D_buf[2] =  D[2];
assign  D_buf[3] =  D[3];
assign  D_buf[4] =  D[4];
assign  D_buf[5] =  D[5];
assign  D_buf[6] =  D[6];
assign  D_buf[7] =  D[7];
assign  D_buf[8] =  D[8];
assign  D_buf[9] =  D[9];
assign  D_buf[10] =  D[10];
assign  D_buf[11] =  D[11];
assign  D_buf[12] =  D[12];
assign  D_buf[13] =  D[13];
assign  D_buf[14] =  D[14];
assign  D_buf[15] =  D[15];
assign  D_buf[16] =  D[16];
assign  D_buf[17] =  D[17];
assign  D_buf[18] =  D[18];
assign  D_buf[19] =  D[19];
assign  D_buf[20] =  D[20];
assign  D_buf[21] =  D[21];
wire WE_buf;
assign  WE_buf =  WE;
wire ME_buf;
assign  ME_buf =  ME;
wire CLK_buf;
assign  CLK_buf =  CLK;
wire AWT_buf;
assign  AWT_buf =  AWT;
wire [8:0] TADR_buf;
assign  TADR_buf[0] =  TADR[0];
assign  TADR_buf[1] =  TADR[1];
assign  TADR_buf[2] =  TADR[2];
assign  TADR_buf[3] =  TADR[3];
assign  TADR_buf[4] =  TADR[4];
assign  TADR_buf[5] =  TADR[5];
assign  TADR_buf[6] =  TADR[6];
assign  TADR_buf[7] =  TADR[7];
assign  TADR_buf[8] =  TADR[8];
wire [21:0] TD_buf;
assign  TD_buf[0] =  TD[0];
assign  TD_buf[1] =  TD[1];
assign  TD_buf[2] =  TD[2];
assign  TD_buf[3] =  TD[3];
assign  TD_buf[4] =  TD[4];
assign  TD_buf[5] =  TD[5];
assign  TD_buf[6] =  TD[6];
assign  TD_buf[7] =  TD[7];
assign  TD_buf[8] =  TD[8];
assign  TD_buf[9] =  TD[9];
assign  TD_buf[10] =  TD[10];
assign  TD_buf[11] =  TD[11];
assign  TD_buf[12] =  TD[12];
assign  TD_buf[13] =  TD[13];
assign  TD_buf[14] =  TD[14];
assign  TD_buf[15] =  TD[15];
assign  TD_buf[16] =  TD[16];
assign  TD_buf[17] =  TD[17];
assign  TD_buf[18] =  TD[18];
assign  TD_buf[19] =  TD[19];
assign  TD_buf[20] =  TD[20];
assign  TD_buf[21] =  TD[21];
wire TWE_buf;
assign  TWE_buf =  TWE;
wire TME_buf;
assign  TME_buf =  TME;
wire TCLK_buf;
assign  TCLK_buf =  TCLK;
wire BISTE_buf;
assign  BISTE_buf =  BISTE;
wire [3:0] RM_buf;
assign  RM_buf[0] =  RM[0];
assign  RM_buf[1] =  RM[1];
assign  RM_buf[2] =  RM[2];
assign  RM_buf[3] =  RM[3];
wire RME_buf;
assign  RME_buf =  RME;
`else
wire [21:0] Q_buf;
buf (Q[0], Q_buf[0]);
buf (Q[1], Q_buf[1]);
buf (Q[2], Q_buf[2]);
buf (Q[3], Q_buf[3]);
buf (Q[4], Q_buf[4]);
buf (Q[5], Q_buf[5]);
buf (Q[6], Q_buf[6]);
buf (Q[7], Q_buf[7]);
buf (Q[8], Q_buf[8]);
buf (Q[9], Q_buf[9]);
buf (Q[10], Q_buf[10]);
buf (Q[11], Q_buf[11]);
buf (Q[12], Q_buf[12]);
buf (Q[13], Q_buf[13]);
buf (Q[14], Q_buf[14]);
buf (Q[15], Q_buf[15]);
buf (Q[16], Q_buf[16]);
buf (Q[17], Q_buf[17]);
buf (Q[18], Q_buf[18]);
buf (Q[19], Q_buf[19]);
buf (Q[20], Q_buf[20]);
buf (Q[21], Q_buf[21]);
wire QM_buf;
buf (QM, QM_buf);
wire [8:0] ADR_buf;
buf (ADR_buf[0], ADR[0]);
buf (ADR_buf[1], ADR[1]);
buf (ADR_buf[2], ADR[2]);
buf (ADR_buf[3], ADR[3]);
buf (ADR_buf[4], ADR[4]);
buf (ADR_buf[5], ADR[5]);
buf (ADR_buf[6], ADR[6]);
buf (ADR_buf[7], ADR[7]);
buf (ADR_buf[8], ADR[8]);
wire [21:0] D_buf;
buf (D_buf[0], D[0]);
buf (D_buf[1], D[1]);
buf (D_buf[2], D[2]);
buf (D_buf[3], D[3]);
buf (D_buf[4], D[4]);
buf (D_buf[5], D[5]);
buf (D_buf[6], D[6]);
buf (D_buf[7], D[7]);
buf (D_buf[8], D[8]);
buf (D_buf[9], D[9]);
buf (D_buf[10], D[10]);
buf (D_buf[11], D[11]);
buf (D_buf[12], D[12]);
buf (D_buf[13], D[13]);
buf (D_buf[14], D[14]);
buf (D_buf[15], D[15]);
buf (D_buf[16], D[16]);
buf (D_buf[17], D[17]);
buf (D_buf[18], D[18]);
buf (D_buf[19], D[19]);
buf (D_buf[20], D[20]);
buf (D_buf[21], D[21]);
buf (WE_buf, WE);
buf (ME_buf, ME);
buf (CLK_buf, CLK);
buf (AWT_buf, AWT);
wire [8:0] TADR_buf;
buf (TADR_buf[0], TADR[0]);
buf (TADR_buf[1], TADR[1]);
buf (TADR_buf[2], TADR[2]);
buf (TADR_buf[3], TADR[3]);
buf (TADR_buf[4], TADR[4]);
buf (TADR_buf[5], TADR[5]);
buf (TADR_buf[6], TADR[6]);
buf (TADR_buf[7], TADR[7]);
buf (TADR_buf[8], TADR[8]);
wire [21:0] TD_buf;
buf (TD_buf[0], TD[0]);
buf (TD_buf[1], TD[1]);
buf (TD_buf[2], TD[2]);
buf (TD_buf[3], TD[3]);
buf (TD_buf[4], TD[4]);
buf (TD_buf[5], TD[5]);
buf (TD_buf[6], TD[6]);
buf (TD_buf[7], TD[7]);
buf (TD_buf[8], TD[8]);
buf (TD_buf[9], TD[9]);
buf (TD_buf[10], TD[10]);
buf (TD_buf[11], TD[11]);
buf (TD_buf[12], TD[12]);
buf (TD_buf[13], TD[13]);
buf (TD_buf[14], TD[14]);
buf (TD_buf[15], TD[15]);
buf (TD_buf[16], TD[16]);
buf (TD_buf[17], TD[17]);
buf (TD_buf[18], TD[18]);
buf (TD_buf[19], TD[19]);
buf (TD_buf[20], TD[20]);
buf (TD_buf[21], TD[21]);
buf (TWE_buf, TWE);
buf (TME_buf, TME);
buf (TCLK_buf, TCLK);
buf (BISTE_buf, BISTE);
wire [3:0] RM_buf;
buf (RM_buf[0], RM[0]);
buf (RM_buf[1], RM[1]);
buf (RM_buf[2], RM[2]);
buf (RM_buf[3], RM[3]);
buf (RME_buf, RME);
`endif // VIRAGE_FAST_VERILOG

`ifdef VIRAGE_FAST_VERILOG
`else
// Setup/hold condition for CLK: ENCLK
reg  ENCLK_P_reg,ENCLKI_P;
wire ENCLK;
wire ENTCLK;
reg  ENCLKIB_P;

reg  BISTE_trans;

always @( BISTE_buf)
begin
  if ( ENCLKI_P == 1'b1 || ENCLKIB_P == 1'b1)
    BISTE_trans = 1'b1;
  else
    BISTE_trans = 1'b0;
end
always @( ME_buf)
begin
  ENCLK_P_reg = 1'b1;
  if ( ENCLKI_P == 1'b1 )
     ENCLKI_P = 1'b0;
end

always @( TME_buf)
begin
  ENCLK_P_reg = 1'b1;
  if ( ENCLKIB_P == 1'b1 )
     ENCLKIB_P = 1'b0;
end
always @(posedge CLK_buf or posedge TCLK_buf)
begin
  #0.001;
  if ( BISTE_trans == 1'b1 && ME_buf === 1'b0 && TME_buf === 1'b0 && ENCLKI_P == 1'b1 && ENCLKIB_P == 1'b1)
    ENCLK_P_reg = 1'b0;
  if (ME_buf === 1'b0 )
  begin
    if (ENCLKI_P == 1'b1)
    begin
      if (BISTE_buf === 1'b0 && BISTE_trans == 1'b0)
        ENCLK_P_reg = 1'b0;
    end
    else
      ENCLKI_P = 1'b1;
  end
  if (TME_buf === 1'b0)
  begin
    if (ENCLKIB_P == 1'b1)
    begin
      if (BISTE_buf === 1'b1 && BISTE_trans == 1'b0)
        ENCLK_P_reg = 1'b0;
    end
    else
      ENCLKIB_P = 1'b1;
  end
end

assign ENCLK = ENCLK_P_reg ;
assign ENTCLK = ENCLK_P_reg ;

`endif // VIRAGE_FAST_VERILOG

`ifdef VIRAGE_FAST_VERILOG
`else
wire ADR_valid;
assign ADR_valid = ( ( ADR_pre < 512 )?1'b1:1'b0);

wire ADR_valid_rec;
assign ADR_valid_rec = ( ( ADR_pre < 512  )?1'b1:1'b0);

wire TADR_valid;
assign TADR_valid = ( ( ADR_pre < 512 )?1'b1:1'b0);

wire TADR_valid_rec;
assign TADR_valid_rec = ( ( ADR_pre < 512 )?1'b1:1'b0);

`endif // VIRAGE_FAST_VERILOG

// Setup/hold conditions for syncronous signals
`ifdef VIRAGE_FAST_VERILOG
`else

// Setup/hold condition for BISTE: BISTE is : ENBISTE
`endif // VIRAGE_FAST_VERILOG
real ENBISTE_time,ENTBISTE_time;
reg  ENBISTE_reg,ENBISTEI,ENTBISTE_reg,ENTBISTEI;
wire ENBISTE,ENTBISTE;

always @( ME_buf or TME_buf ) begin
  if ( ME_buf === 1'b0 && TME_buf === 1'b0 && ($realtime == ENBISTE_time) )
     ENBISTEI = 1'b0;
  else if ((ENBISTE_reg === 1'b0) & (CLK_buf === 1'b0))
    ENBISTE_reg = 1'b1;
  else
     ENBISTEI = 1'b1;
end

always @(negedge CLK_buf) begin
  if (ENBISTEI === 1'b0)
    ENBISTE_reg = 1'b0;
  else
    ENBISTE_reg = 1'b1;
end

always @(posedge CLK_buf) begin
    ENBISTE_time = $realtime;
    ENBISTEI = ME_buf || TME_buf;
end

always @( ME_buf or TME_buf ) begin
  if ( ME_buf === 1'b0 && TME_buf === 1'b0 && ($realtime == ENTBISTE_time) )
    ENTBISTEI = 1'b0;
  else if ((ENTBISTE_reg === 1'b0) & (TCLK_buf === 1'b0))
    ENTBISTE_reg = 1'b1;
  else
    ENTBISTEI = 1'b1;
end

always @(negedge TCLK_buf) begin
  if (ENTBISTEI === 1'b0)
    ENTBISTE_reg = 1'b0;
  else
    ENTBISTE_reg = 1'b1;
end

always @(posedge TCLK_buf) begin
    ENTBISTE_time = $realtime;
    ENTBISTEI = ME_buf || TME_buf;
end

assign ENTBISTE = ENTBISTE_reg ;
assign ENBISTE = ENBISTE_reg ;
`ifdef VIRAGE_FAST_VERILOG
`else

// Setup/hold condition for Address: ADR is : ENADR
wire ENADR;
assign ENADR = ((ME_pre !== 1'b0 && BISTE_buf === 1'b0 ) ?1'b1:1'b0);

// Setup/hold condition for Memory Enable: ME is : ENME
wire ENME;
assign ENME = ((BISTE_buf === 1'b0 && ADR_valid) ?1'b1:1'b0);

// Setup/hold condition for Write Enable: WE is : ENWE
wire ENWE;
assign ENWE = ((ADR_valid  && ME_pre !== 1'b0 && BISTE_buf === 1'b0 ) ?1'b1:1'b0);

// Setup/hold condition for Data In: D is : END
wire END;
assign END = ((ADR_valid  && ME_pre !== 1'b0 && WE_pre !== 1'b0 && BISTE_buf === 1'b0 )?1'b1:1'b0) ;

// Setup/hold condition for Read Margin Vector: RM is : ENRM
wire ENTRM;
wire ENRM;
assign ENTRM = (( BISTE_buf === 1'b1  && (ME_pre !== 1'b0 && TADR_valid && RME_buf === 1'b1 ))?1'b1:1'b0);
assign ENRM = (( BISTE_buf === 1'b0  && (ME_pre !== 1'b0 && TADR_valid && RME_buf === 1'b1 ))?1'b1:1'b0);

// Setup/hold condition for Read Margin Vector: RME is : ENRME
wire ENTRME;
wire ENRME;
assign ENTRME = (( BISTE_buf === 1'b1  && (ME_pre !== 1'b0 && TADR_valid ))?1'b1:1'b0);
assign ENRME = (( BISTE_buf === 1'b0  && (ME_pre !== 1'b0 && TADR_valid ))?1'b1:1'b0);
// Setup/hold condition for Address: TADR is : ENTADR
wire ENTADR;
assign ENTADR = ((ME_pre !== 1'b0  && BISTE_buf === 1'b1 ) ?1'b1:1'b0);

// Setup/hold condition for Memory Enable: TME is : ENTME
wire ENTME;
assign ENTME =  (( TADR_valid  && BISTE_buf === 1'b1 )?1'b1:1'b0);

// Setup/hold condition for Write Enable: TWE is : ENTWE
wire ENTWE;
assign ENTWE = ((TADR_valid  && ME_pre !== 1'b0 && BISTE_buf === 1'b1 ) ?1'b1:1'b0);

// Setup/hold condition for Data In: TD is : ENTD
wire ENTD;
assign ENTD = ((TADR_valid  && ME_pre !== 1'b0 && WE_pre !== 1'b0 && BISTE_buf === 1'b1 )?1'b1:1'b0) ;


`endif // VIRAGE_FAST_VERILOG

reg ME_buf_L;
reg WE_buf_L;

`ifdef VIRAGE_FAST_VERILOG
`else
`endif // VIRAGE_FAST_VERILOG

`ifdef VIRAGE_FAST_VERILOG
`else
specify


    specparam

        Tac = 1.182,
        Tcax = 0.326,
        Tdc = 0.844,
        Tcdx = 0.000,
        Twc = 0.701,
        Tcwx = 0.126,
        Tmc = 0.824,
        Tcmx = 0.400,
        Tcl = 1.258,
        Tch = 0.899,
        Tcc = 3.246,
        Tbc = 1.941,
        Tcbx = 0.326,
        Trmc = 3.246,
        Tcrmx = 3.246,
        Tcq = 3.214,
        Tcqx = 3.070,
        Tdq = 1.189,
        Tdqx = 1.055,
        Taq = 1.391,
        Taqx = 1.293,
        Tbq = 2.074,
        Tbqx = 1.900,
        Taqm = 0.545,
        Tmxqm = 6.303,
        Tbqm = 6.487;
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[21]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[20]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[19]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[18]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[17]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[16]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[15]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[14]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[13]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[12]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[11]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[10]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[9]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[8]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[7]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[6]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[5]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[4]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[3]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[2]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[1]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & !BISTE )
       ( posedge CLK => (  Q[0]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[21]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[20]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[19]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[18]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[17]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[16]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[15]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[14]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[13]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[12]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[11]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[10]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[9]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[8]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[7]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[6]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[5]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[4]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[3]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[2]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[1]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( !AWT & BISTE )
       ( posedge TCLK => (  Q[0]  : 1'bx )) = (  Tcq, Tcq, Tcqx, Tcq, Tcqx, Tcq );
     if ( AWT & !BISTE )
       ( posedge D[0] => (  Q[0]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[0] => (  Q[0]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[1] => (  Q[1]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[1] => (  Q[1]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[2] => (  Q[2]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[2] => (  Q[2]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[3] => (  Q[3]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[3] => (  Q[3]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[4] => (  Q[4]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[4] => (  Q[4]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[5] => (  Q[5]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[5] => (  Q[5]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[6] => (  Q[6]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[6] => (  Q[6]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[7] => (  Q[7]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[7] => (  Q[7]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[8] => (  Q[8]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[8] => (  Q[8]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[9] => (  Q[9]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[9] => (  Q[9]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[10] => (  Q[10]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[10] => (  Q[10]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[11] => (  Q[11]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[11] => (  Q[11]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[12] => (  Q[12]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[12] => (  Q[12]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[13] => (  Q[13]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[13] => (  Q[13]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[14] => (  Q[14]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[14] => (  Q[14]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[15] => (  Q[15]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[15] => (  Q[15]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[16] => (  Q[16]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[16] => (  Q[16]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[17] => (  Q[17]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[17] => (  Q[17]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[18] => (  Q[18]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[18] => (  Q[18]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[19] => (  Q[19]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[19] => (  Q[19]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[20] => (  Q[20]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[20] => (  Q[20]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( posedge D[21] => (  Q[21]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & !BISTE )
       ( negedge D[21] => (  Q[21]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );

       ( posedge AWT => (  Q[21]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[21]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[20]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[20]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[19]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[19]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[18]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[18]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[17]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[17]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[16]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[16]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[15]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[15]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[14]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[14]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[13]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[13]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[12]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[12]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[11]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[11]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[10]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[10]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[9]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[9]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[8]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[8]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[7]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[7]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[6]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[6]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[5]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[5]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[4]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[4]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[3]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[3]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[2]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[2]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[1]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[1]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( posedge AWT => (  Q[0]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );

       ( negedge AWT => (  Q[0]  : 1'bx )) = (  Taq, Taq, Taqx, Taq, Taqx, Taq );
     if ( AWT & BISTE )
       ( posedge TD[0] => (  Q[0]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[0] => (  Q[0]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[1] => (  Q[1]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[1] => (  Q[1]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[2] => (  Q[2]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[2] => (  Q[2]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[3] => (  Q[3]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[3] => (  Q[3]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[4] => (  Q[4]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[4] => (  Q[4]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[5] => (  Q[5]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[5] => (  Q[5]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[6] => (  Q[6]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[6] => (  Q[6]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[7] => (  Q[7]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[7] => (  Q[7]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[8] => (  Q[8]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[8] => (  Q[8]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[9] => (  Q[9]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[9] => (  Q[9]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[10] => (  Q[10]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[10] => (  Q[10]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[11] => (  Q[11]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[11] => (  Q[11]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[12] => (  Q[12]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[12] => (  Q[12]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[13] => (  Q[13]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[13] => (  Q[13]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[14] => (  Q[14]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[14] => (  Q[14]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[15] => (  Q[15]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[15] => (  Q[15]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[16] => (  Q[16]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[16] => (  Q[16]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[17] => (  Q[17]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[17] => (  Q[17]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[18] => (  Q[18]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[18] => (  Q[18]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[19] => (  Q[19]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[19] => (  Q[19]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[20] => (  Q[20]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[20] => (  Q[20]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( posedge TD[21] => (  Q[21]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if ( AWT & BISTE )
       ( negedge TD[21] => (  Q[21]  : 1'bx )) = (  Tdq, Tdq, Tdqx, Tdq, Tdqx, Tdq );
     if (  AWT )
       ( posedge BISTE => (  Q[21]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[21]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[20]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[20]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[19]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[19]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[18]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[18]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[17]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[17]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[16]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[16]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[15]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[15]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[14]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[14]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[13]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[13]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[12]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[12]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[11]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[11]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[10]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[10]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[9]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[9]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[8]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[8]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[7]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[7]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[6]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[6]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[5]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[5]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[4]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[4]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[3]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[3]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[2]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[2]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[1]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[1]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( posedge BISTE => (  Q[0]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );
     if (  AWT )
       ( negedge BISTE => (  Q[0]  : 1'bx )) = (  Tbq, Tbq, Tbqx, Tbq, Tbqx, Tbq );

       ( posedge AWT => (  QM  : 1'bx )) = (  Taqm, Taqm );

       ( negedge AWT => (  QM  : 1'bx )) = (  Taqm, Taqm );
     if ( AWT  & !BISTE )
       ( posedge WE => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( negedge WE => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( posedge TWE => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( negedge TWE => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if (  AWT   )
       ( posedge BISTE => (  QM  : 1'bx )) = (  Tbqm, Tbqm );
     if (  AWT   )
       ( negedge BISTE => (  QM  : 1'bx )) = (  Tbqm, Tbqm );
     if ( AWT  & !BISTE )
       ( posedge ME => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( negedge ME => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( posedge ADR[8] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( negedge ADR[8] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( posedge ADR[7] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( negedge ADR[7] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( posedge ADR[6] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( negedge ADR[6] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( posedge ADR[5] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( negedge ADR[5] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( posedge ADR[4] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( negedge ADR[4] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( posedge ADR[3] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( negedge ADR[3] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( posedge ADR[2] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( negedge ADR[2] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( posedge ADR[1] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( negedge ADR[1] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( posedge ADR[0] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & !BISTE )
       ( negedge ADR[0] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( posedge TME => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( negedge TME => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( posedge TADR[8] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( negedge TADR[8] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( posedge TADR[7] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( negedge TADR[7] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( posedge TADR[6] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( negedge TADR[6] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( posedge TADR[5] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( negedge TADR[5] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( posedge TADR[4] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( negedge TADR[4] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( posedge TADR[3] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( negedge TADR[3] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( posedge TADR[2] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( negedge TADR[2] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( posedge TADR[1] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( negedge TADR[1] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( posedge TADR[0] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );
     if ( AWT  & BISTE )
       ( negedge TADR[0] => (  QM  : 1'bx )) = (  Tmxqm, Tmxqm );



// Timing Checks

  $width (negedge CLK &&& ENCLK, Tcl, 0, notif_clk);
  $width (posedge CLK &&& ENCLK, Tch, 0, notif_clk);
  $period (posedge CLK &&& ENCLK, Tcc, notif_clk);
  $period (negedge CLK &&& ENCLK, Tcc, notif_clk);
  $width (negedge TCLK &&& ENTCLK, Tcl, 0, notif_clk);
  $width (posedge TCLK &&& ENTCLK, Tch, 0, notif_clk);
  $period (posedge TCLK &&& ENTCLK, Tcc, notif_clk);
  $period (negedge TCLK &&& ENTCLK, Tcc, notif_clk);

  $setuphold (posedge CLK  &&& ENADR, posedge ADR[0], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& ENADR, negedge ADR[0], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& ENADR, posedge ADR[1], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& ENADR, negedge ADR[1], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& ENADR, posedge ADR[2], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& ENADR, negedge ADR[2], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& ENADR, posedge ADR[3], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& ENADR, negedge ADR[3], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& ENADR, posedge ADR[4], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& ENADR, negedge ADR[4], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& ENADR, posedge ADR[5], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& ENADR, negedge ADR[5], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& ENADR, posedge ADR[6], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& ENADR, negedge ADR[6], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& ENADR, posedge ADR[7], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& ENADR, negedge ADR[7], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& ENADR, posedge ADR[8], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& ENADR, negedge ADR[8], Tac, Tcax, notif_adr );
  $setuphold (posedge CLK  &&& END, posedge D[0], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[0], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[1], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[1], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[2], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[2], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[3], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[3], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[4], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[4], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[5], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[5], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[6], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[6], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[7], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[7], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[8], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[8], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[9], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[9], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[10], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[10], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[11], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[11], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[12], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[12], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[13], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[13], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[14], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[14], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[15], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[15], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[16], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[16], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[17], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[17], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[18], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[18], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[19], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[19], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[20], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[20], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, posedge D[21], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& END, negedge D[21], Tdc, Tcdx, notif_d );
  $setuphold (posedge CLK  &&& ENWE, posedge WE,Twc, Tcwx, notif_we );
  $setuphold (posedge CLK  &&& ENWE, negedge WE,Twc, Tcwx, notif_we );
  $setuphold (posedge CLK  &&& ENME, posedge ME,Tmc, Tcmx, notif_me );
  $setuphold (posedge CLK  &&& ENME, negedge ME,Tmc, Tcmx, notif_me );
  $setuphold (posedge TCLK  &&& ENTADR, posedge TADR[0], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTADR, negedge TADR[0], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTADR, posedge TADR[1], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTADR, negedge TADR[1], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTADR, posedge TADR[2], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTADR, negedge TADR[2], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTADR, posedge TADR[3], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTADR, negedge TADR[3], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTADR, posedge TADR[4], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTADR, negedge TADR[4], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTADR, posedge TADR[5], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTADR, negedge TADR[5], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTADR, posedge TADR[6], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTADR, negedge TADR[6], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTADR, posedge TADR[7], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTADR, negedge TADR[7], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTADR, posedge TADR[8], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTADR, negedge TADR[8], Tac, Tcax, notif_adr );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[0], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[0], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[1], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[1], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[2], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[2], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[3], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[3], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[4], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[4], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[5], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[5], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[6], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[6], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[7], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[7], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[8], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[8], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[9], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[9], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[10], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[10], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[11], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[11], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[12], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[12], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[13], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[13], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[14], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[14], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[15], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[15], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[16], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[16], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[17], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[17], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[18], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[18], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[19], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[19], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[20], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[20], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, posedge TD[21], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTD, negedge TD[21], Tdc, Tcdx, notif_d );
  $setuphold (posedge TCLK  &&& ENTWE, posedge TWE,Twc, Tcwx, notif_we );
  $setuphold (posedge TCLK  &&& ENTWE, negedge TWE,Twc, Tcwx, notif_we );
  $setuphold (posedge TCLK  &&& ENTME, posedge TME,Tmc, Tcmx, notif_me );
  $setuphold (posedge TCLK  &&& ENTME, negedge TME,Tmc, Tcmx, notif_me );
  $hold (negedge CLK  &&& ENBISTE, posedge BISTE, Tcbx, notif_biste );
  $hold (negedge CLK  &&& ENBISTE, negedge BISTE, Tcbx, notif_biste );
  $setup ( posedge BISTE,posedge CLK  &&& ENBISTE, Tbc, notif_biste );
  $setup ( negedge BISTE,posedge CLK  &&& ENBISTE, Tbc, notif_biste );
  $hold (negedge TCLK  &&& ENTBISTE, posedge BISTE, Tcbx, notif_biste );
  $hold (negedge TCLK  &&& ENTBISTE, negedge BISTE, Tcbx, notif_biste );
  $setup ( posedge BISTE,posedge TCLK  &&& ENTBISTE, Tbc, notif_biste );
  $setup ( negedge BISTE,posedge TCLK  &&& ENTBISTE, Tbc, notif_biste );
  $setuphold (posedge CLK  &&& ENRM, posedge RM[0], Trmc, Tcrmx, notif_rm );
  $setuphold (posedge CLK  &&& ENRM, negedge RM[0], Trmc, Tcrmx, notif_rm );
  $setuphold (posedge CLK  &&& ENRM, posedge RM[1], Trmc, Tcrmx, notif_rm );
  $setuphold (posedge CLK  &&& ENRM, negedge RM[1], Trmc, Tcrmx, notif_rm );
  $setuphold (posedge CLK  &&& ENRM, posedge RM[2], Trmc, Tcrmx, notif_rm );
  $setuphold (posedge CLK  &&& ENRM, negedge RM[2], Trmc, Tcrmx, notif_rm );
  $setuphold (posedge CLK  &&& ENRM, posedge RM[3], Trmc, Tcrmx, notif_rm );
  $setuphold (posedge CLK  &&& ENRM, negedge RM[3], Trmc, Tcrmx, notif_rm );
  $setuphold (posedge TCLK  &&& ENTRM, posedge RM[0], Trmc, Tcrmx, notif_rm );
  $setuphold (posedge TCLK  &&& ENTRM, negedge RM[0], Trmc, Tcrmx, notif_rm );
  $setuphold (posedge TCLK  &&& ENTRM, posedge RM[1], Trmc, Tcrmx, notif_rm );
  $setuphold (posedge TCLK  &&& ENTRM, negedge RM[1], Trmc, Tcrmx, notif_rm );
  $setuphold (posedge TCLK  &&& ENTRM, posedge RM[2], Trmc, Tcrmx, notif_rm );
  $setuphold (posedge TCLK  &&& ENTRM, negedge RM[2], Trmc, Tcrmx, notif_rm );
  $setuphold (posedge TCLK  &&& ENTRM, posedge RM[3], Trmc, Tcrmx, notif_rm );
  $setuphold (posedge TCLK  &&& ENTRM, negedge RM[3], Trmc, Tcrmx, notif_rm );
  $setuphold (posedge CLK  &&& ENRME, posedge RME,Trmc, Tcrmx, notif_rme );
  $setuphold (posedge CLK  &&& ENRME, negedge RME,Trmc, Tcrmx, notif_rme );
  $setuphold (posedge TCLK  &&& ENTRME, posedge RME,Trmc, Tcrmx, notif_rme );
  $setuphold (posedge TCLK  &&& ENTRME, negedge RME,Trmc, Tcrmx, notif_rme );

endspecify
`endif // VIRAGE_FAST_VERILOG






`ifdef VIRAGE_FAST_VERILOG

generic_behav_spram512x22cm4Mhz10 #(MES_ALL ,debug_mode) u0 (  .Q (Q_buf), .QM(QM_buf), .ADR (ADR_tmp), .D (D_tmp), .WE(WE_tmp), .ME(ME_tmp), .CLK(CLK_tmp), .AWT(AWT_buf), .BISTE(BISTE_buf), .RM (RM_buf), .RME(RME_buf) );

`else

generic_behav_spram512x22cm4Mhz10 #(MES_ALL ,debug_mode) u0 (  .Q (Q_buf), .QM(QM_buf), .ADR (ADR_tmp), .D (D_tmp), .WE(WE_tmp), .ME(ME_tmp), .CLK(CLK_tmp), .AWT(AWT_buf), .BISTE(BISTE_buf), .RM (RM_buf), .RME(RME_buf),.notif_adr(notif_adr), .notif_d(notif_d), .notif_we(notif_we), .notif_me(notif_me), .notif_clk(notif_clk), .notif_biste(notif_biste), .notif_rm(notif_rm), .notif_rme(notif_rme) );

`endif // VIRAGE_FAST_VERILOG


always @( ADR_tmp or negedge CLK_tmp)
 begin
   if ( CLK_tmp == 1'b0) ADR_pre = ADR_tmp;
 end

always @( ME_tmp or negedge CLK_tmp)
  begin
    if ( CLK_tmp == 1'b0) ME_pre = ME_tmp;
  end

always @( WE_tmp or negedge CLK_tmp)
  begin
    if ( CLK_tmp == 1'b0) WE_pre = WE_tmp;
  end

always @( posedge CLK_tmp)
begin
    ME_buf_L = ME_pre;
    WE_buf_L = WE_pre;

end  // end of always @( posedge CLK_tmp)


always @( BISTE_buf or WE_buf or TWE_buf or ADR_buf or TADR_buf or D_buf or TD_buf or ME_buf or TME_buf or CLK_buf or TCLK_buf  ) begin
   if ( BISTE_buf == 1'b1 ) begin
       WE_tmp = TWE_buf;
       ADR_tmp = TADR_buf;
       D_tmp = TD_buf;
       ME_tmp = TME_buf;
       CLK_tmp = TCLK_buf;
   end
   else if ( BISTE_buf == 1'b0 ) begin
       WE_tmp = WE_buf;
       ADR_tmp = ADR_buf;
       D_tmp = D_buf;
       ME_tmp = ME_buf;
       CLK_tmp = CLK_buf;
   end
   else begin
      u0.report_unknown("BISTE","","");
       WE_tmp = 1'bx;
       ADR_tmp = 9'bx;
       D_tmp = 22'bx;
       ME_tmp = 1'bx;
       CLK_tmp = 1'bx;
   end
end

always @( BISTE_buf )
begin
#0;
  if ( ((ENBISTE && CLK_buf)  || (ENTBISTE && TCLK_buf)) == 1'b1)
  begin
    $display("\n %m VERILOG> WARNING: CLOCKS SIGNALS CANNOT BE HIGH AT BIST TRANSITION (time %0t)", $time);
     u0.corrupt_all_loc(`True);
     u0.Q_local <=  u0.DataX;
  end // end of if CLK_buf
end // end of always BISTE_buf

endmodule
`endcelldefine
`ifdef verifault
`disable_portfaults
`nosuppress_faults
`endif


`ifdef VIRAGE_FAST_VERILOG

module generic_behav_spram512x22cm4Mhz10 (  Q, QM, ADR, D, WE, ME, CLK, AWT, BISTE, RM, RME );

`else

module generic_behav_spram512x22cm4Mhz10 (  Q, QM, ADR, D, WE, ME, CLK, AWT, BISTE, RM, RME,notif_adr, notif_d, notif_we, notif_me, notif_clk, notif_biste, notif_rm, notif_rme );

`endif //VIRAGE_FAST_VERILOG

 parameter MES_ALL = "ON";
parameter debug_mode = 1;
parameter words = 512, bits = 22, addrbits = 9, timingmode = 1, rmbits=4;

output [bits-1:0] Q;
output QM;
input [addrbits-1:0] ADR;
input [bits-1:0] D;
input WE;
input ME;
input CLK;
input AWT;
input BISTE;
input [rmbits-1:0] RM;
input RME;


    `ifdef  virage_ignore_read_addx
       parameter flag_ignore_read_addx = 0;
    `else
       parameter flag_ignore_read_addx = 1;
    `endif

`ifdef VIRAGE_FAST_VERILOG
`else
input notif_adr, notif_d, notif_we, notif_me, notif_clk, notif_biste, notif_rm, notif_rme;

`endif // VIRAGE_FAST_VERILOG

parameter DataX = { bits { 1'bx } };
parameter DataZ = { bits { 1'bz } };

reg  [bits-1:0]  Q_local;
reg  [bits-1:0]  Q_awt;

wire    [3:0] RM_set;
reg
        flaga_read_ok,
        flaga_we_ok,
        flaga_d_ok,
        flaga_rm_ok,
        flaga_adr_ok,
        flaga_range_ok;
reg     flaga_clk_valid;
reg     flaga_adr_x;

event   event_on_A_port;

reg  [addrbits-1:0] ADRlatched;
reg  [addrbits-1:0] ADR_old;
reg  [bits-1:0] Dlatched;
reg  [bits-1:0] D_old;
reg WElatched;
reg WE_old;
reg  MElatched;
reg  ME_old;
real CLK_TIME;

`ifdef VIRAGE_FAST_VERILOG
`else
`endif // VIRAGE_FAST_VERILOG

integer i;
reg  [bits-1:0] mem_core_array [0:words -1];
reg  [bits-1:0] mem_fault_array_XOR [0:words -1];
initial
  begin
    for (i=0; i< words ; i=i+1)
      mem_fault_array_XOR[i]=0;
`ifdef MEMFAULTINJ
    if ($test$plusargs("asap_error"))
      mem_fault_array_XOR[1] = 1'b1 << (bits - 1);
`endif
  end


reg mes_flag;

initial
begin
  mes_flag = 0;
end

function is_adr_Valid;  // 1-bit return value
 input [addrbits-1:0] addr_to_check;
 reg     ret_value;
 begin
  ret_value = `True;
   if ((^addr_to_check) === 1'bx ) begin
    flaga_adr_x = `True;
    ret_value = `False;
   end
   if((addr_to_check > words -1) )
    begin
     ret_value = `False;
    end
   is_adr_Valid = ret_value;
end
endfunction

// -------------------------------------------------------------------
// Common tasks
// -------------------------------------------------------------------

// Task to report unknown messages
task report_unknown;
input [8*5:1] signal;
input [8*5:1] bsignal;
input [8*5:1] tsignal;
reg bist_reg;
begin
  if ( bsignal !== "" )
  begin
      bist_reg = BISTE;

    if( MES_ALL=="ON" && $realtime != 0 && mes_flag)
    begin
      if ( bist_reg === 1'b0 )
        $display("<<%0s unknown>> at time=%t; instance=%m (RAMS1H)",signal,$realtime);
      else if ( bist_reg === 1'b1 )
        $display("<<%0s unknown>> at time=%t; instance=%m (RAMS1H)",tsignal,$realtime);
    end
  end
  else
    if( MES_ALL=="ON" && $realtime != 0 && mes_flag )
    begin
      $display("<<%0s unknown>> at time=%t; instance=%m (RAMS1H)",signal,$realtime);
    end
end
endtask


task corrupt_all_loc;
 input flag_range_ok;
 integer addr_index;
 begin
                                     // do not corrupt entire memory if write to
                                    // out of range address, for all other cases
                                    // flag_range_ok is true, therefore corruption
                                    // will occur as before
  if( flag_range_ok == `True)
   begin
    for( addr_index = 0; addr_index < words; addr_index = addr_index + 1) begin
     mem_core_array[ addr_index] = DataX;
    end
   end
 end
endtask

task corrupt_cur_loc;
 input[addrbits-1:0] loc_to_corrupt;
  mem_core_array[loc_to_corrupt] = DataX;
endtask


always @( negedge CLK or WE )
   begin
       if ( CLK == 1'b0 )
       WE_old = WE;
   end
always @( negedge CLK or ADR )
   begin
       if ( CLK == 1'b0 )
       ADR_old = ADR;
   end
always @( negedge CLK or D )
   begin
       if ( CLK == 1'b0 )
       D_old = D;
   end
always @( negedge CLK or ME )
   begin
       if ( CLK == 1'b0 )
       ME_old = ME;
   end
// Perform Sanity Check on Port A, Corrupt memory if required

task checkSanityOnAport;

 #0                // let CLOCK and NOTIFIER stuff execute first
 case ( {flaga_adr_ok, flaga_we_ok, flaga_d_ok} ) // only 1 and 0

  3'b111   : ;                                                // everything ok!!!

  3'b101,
  3'b100   : corrupt_cur_loc(ADRlatched);          // WE is unstable

  3'b110   : if (WElatched !== 1'b0)
              corrupt_cur_loc(ADRlatched);         // Data is unstable
  3'b000,
  3'b001   : corrupt_all_loc(flaga_range_ok);            // ADR and WE unstable
  3'b010,
  3'b011   : if (WElatched !== 1'b0)    // ADR unstable, WE stable
              corrupt_all_loc(flaga_range_ok);
 endcase
endtask

// PORT A FUNCTIONALITY (Handle violation behavior)

initial
 begin
  flaga_adr_ok  = `True;
  flaga_range_ok = `True;
  flaga_we_ok   = `True;
  flaga_d_ok    = `True;
  flaga_read_ok = `True;
  flaga_rm_ok = `True;
  flaga_clk_valid = `True;
  flaga_adr_x = `False;
 end


`ifdef VIRAGE_FAST_VERILOG
`else

always @(notif_we)            // PORT A WE violation
 begin
#0;
    flaga_we_ok = `False;
    checkSanityOnAport;
    disable OUTPUT_0;
    flaga_read_ok = `False;
    -> event_on_A_port;
 end
always @(notif_clk)            // PORT A CLK violation
 begin
#0;
  disable OUTPUT_0;
  flaga_adr_ok = `False;
  flaga_we_ok  = `False;
  checkSanityOnAport;
  flaga_read_ok = `False;     // irrespective of WE
  -> event_on_A_port;
 end

always @(notif_me)            // PORT A ME violation
 begin
#0;
  flaga_adr_ok = `False;
  flaga_read_ok = `False;     // irrespective of WE
  disable OUTPUT_0;
  checkSanityOnAport;
  -> event_on_A_port;
  corrupt_all_loc(`True);
 end


always @(notif_adr)           // PORT A ADR violation
 begin
#0;
    if (WElatched === 1'b0)
      begin
    corrupt_all_loc(`True);
    flaga_read_ok = `False; // irrespective of WE
    disable OUTPUT_0;
    -> event_on_A_port;
      end
     else  begin
    flaga_adr_ok = `False;
    flaga_read_ok = `False; // irrespective of WE
    disable OUTPUT_0;
    checkSanityOnAport;
    -> event_on_A_port;
      end
 end

always @(notif_d)             // PORT A D violation
 begin
#0;
    flaga_d_ok = `False;
    disable OUTPUT_0;
    checkSanityOnAport;
    flaga_read_ok = `False;
    -> event_on_A_port;
 end
always @(notif_biste)               // PORT A BISTE violation
 begin
#0;
    disable OUTPUT_0;
    flaga_read_ok = `False;
    -> event_on_A_port;
    flaga_adr_ok  = `False;
    flaga_d_ok  = `False;
    flaga_we_ok  = `False;
    checkSanityOnAport;
 end

always @(notif_rm)               //PORT A RM violation
 begin
    disable OUTPUT_0;
    flaga_read_ok = `False;
    -> event_on_A_port;
    flaga_d_ok  = `False;
    checkSanityOnAport;
 end
always @(notif_rme)               //PORT A RMEN violation
 begin
    disable OUTPUT_0;
    flaga_read_ok = `False;
    -> event_on_A_port;
    flaga_d_ok  = `False;
    checkSanityOnAport;
 end



`endif // VIRAGE_FAST_VERILOG


always @(negedge CLK)          // reset for next cycle
 begin
  if ( CLK !== 1'bx ) begin
   #0.001;
   flaga_range_ok  = `True;
   flaga_read_ok = `True;
   flaga_rm_ok = `True;
   flaga_clk_valid = `True;
   flaga_adr_x = `False;
  end
  else
  begin
    report_unknown("CLK","BISTE","TCLK");
    flaga_clk_valid = `False;
    Q_local =  DataX;
    corrupt_all_loc(`True);
   end
 end

// PORT A FUNCTIONALITY (Handle normal read/write)

always @(posedge CLK)
begin
  flaga_adr_ok  = `True;
  flaga_we_ok   = `True;
  flaga_d_ok    = `True;

  if (CLK === 1'bx)
  begin
    report_unknown("CLK","BISTE","TCLK");
    flaga_clk_valid = `False;
    Q_local =  DataX;
    corrupt_all_loc(`True);
  end // end of if (CLK === 1'bx)

  CLK_TIME = $realtime;
  MElatched = ME_old;
  WElatched = WE_old;
  ADRlatched = ADR_old;
  Dlatched = D_old;
    if ((^Dlatched === 1'bx) && MElatched == 1'b1)
    begin
      if (Dlatched === 22'bx)
      begin
        flaga_d_ok  = `False;
      end
      if (WElatched !== 1'b0)
      begin
        report_unknown("D","BISTE","TD");
      end
    end



  if (!flaga_clk_valid) begin
    Q_local =  DataX;
  end
  else
  begin
    if (MElatched!== 1'b0)
    begin
      if (WElatched === 1'bx)
      begin
        report_unknown("WE","BISTE","TWE");
        flaga_we_ok = `False;
        flaga_read_ok = `False;
      end
      if (MElatched !== 1'b1)
       flaga_we_ok = `False;       // don't know if cycle is On or Off
      if (is_adr_Valid(ADRlatched) != `True ) begin
       if ( flaga_adr_x ) begin
         report_unknown("ADR","BISTE","TADR");
       end
       flaga_adr_ok = `False;
       if( !(flaga_adr_x) )
       begin
         if( MES_ALL=="ON" && $realtime != 0 && mes_flag == 1'b1)
         $display("\n%m WARNING:address ADR is out of range, RANGE:0 to 511\n");
         flaga_range_ok = `False;
       end
      else
      begin
        if (WElatched === 1'b0 && MElatched === 1'b1 && flag_ignore_read_addx == 1)
          corrupt_all_loc(`True);
      end
      end

      if ( MElatched === 1'bx )
      begin
         report_unknown("ME","BISTE","TME");
          Q_local =  DataX;
        if ( !(WElatched == 1'b0 && flag_ignore_read_addx == 0) )
          corrupt_all_loc(flaga_range_ok);
      end
      else
      begin
         if (flaga_we_ok && flaga_adr_ok && flaga_d_ok && (WElatched == 1'b1))
         begin
           mem_core_array[ADRlatched] = Dlatched;  // write data in
           if (mes_flag == 0) mes_flag = 1;
	 end
         else
         begin
           checkSanityOnAport;
         end


        -> event_on_A_port;
       end
     end
   end
 end

always @ (AWT)
begin : AWT_blk
  if ( AWT === 1'b1)
  begin

     `ifdef VIRAGE_FAST_VERILOG
       #0;
     `else
        Q_awt = DataX;
        #0.001
     `endif // VIRAGE_FAST_VERILOG
      Q_awt =  D;
  end // end of if AWT
  else
  begin
    if (AWT === 1'bx)
    begin
      report_unknown("AWT","","");
      Q_awt =  DataX;
    end
  end
end

always @ (D)
begin :D_blk
  if ( AWT === 1'b1 )
  begin
     `ifdef VIRAGE_FAST_VERILOG
       #0;
     `else
        Q_awt = DataX;
        #0.001
     `endif // VIRAGE_FAST_VERILOG
    Q_awt =  D;
  end
end // end of always @ (D)



// START OF PORT A READ-OUT BLOCK

always @(event_on_A_port)
begin
  #0 // let CLOCK and NOTIFIER module execute first
  if (RM_set != 4'b0101)
  begin
    if( MES_ALL=="ON" && $realtime != 0 && mes_flag == 1'b1)
    begin
      $display("RM = %b is not recommended value ; time = %t, instance = %m (spram512x22cm4Mhz10_core)",RM,$realtime);
    end // MES_ALL=="ON"
  end // RM_set != 4'b0101
  if (^RM_set === 1'bx) begin
    flaga_rm_ok = `False;
    if (RME !== 1'bx) begin
      report_unknown("RM","","");
    end
  end
    if (flaga_adr_ok && (ADRlatched <= words -1) && flaga_read_ok && flaga_rm_ok) begin : OUTPUT_0
      if (WElatched == 1'b1)
      begin
        `ifdef VIRAGE_FAST_VERILOG
        `else
           Q_local = DataX;
        `endif // VIRAGE_FAST_VERILOG
         `ifdef VIRAGE_FAST_VERILOG
         `else
             #0.001
         `endif // VIRAGE_FAST_VERILOG

            Q_local = Dlatched;

      end // end of WElatched
      else
      begin
        `ifdef VIRAGE_FAST_VERILOG
        `else
           Q_local = DataX;
        `endif // VIRAGE_FAST_VERILOG
          `ifdef VIRAGE_FAST_VERILOG
          `else
             #0.001
          `endif // VIRAGE_FAST_VERILOG

            Q_local = mem_core_array[ADRlatched]^mem_fault_array_XOR[ADRlatched];

            if (mes_flag == 0) mes_flag = 1;
      end // else WE
    end // end of if (flaga_adr_ok && (ADRlatched))
    else
    begin
      if (is_adr_Valid(ADRlatched) != `True && WElatched == 1'b1)
      begin
          `ifdef VIRAGE_FAST_VERILOG
          `else
             Q_local = DataX;
          `endif // VIRAGE_FAST_VERILOG
          `ifdef VIRAGE_FAST_VERILOG
          `else
              #0.001
          `endif // VIRAGE_FAST_VERILOG

            Q_local = Dlatched;

      end // end of if (is_adr_Valid(ADRlatched)
      else
        Q_local =   DataX;
        flaga_read_ok = `True;
   end
end // end of always @(event_on_A_port

// END OF PORT A READ-OUT BLOCK



assign Q = (AWT===1'b1)?Q_awt:(AWT === 1'b0)?Q_local:DataX;


// START OF PORT A OUTPUT ENABLE BLOCK



assign RM_set = (RME === 1'b0) ? 4'b0101:((RME === 1'b1) ? RM: 4'bx);
assign QM = ( AWT &  (WE ^ ME ^ (^ADR)));
endmodule
