Microcode-controlled RAM BIST
=============================

Tool for generating HDL IP core from March algorithm description

Content fo directories
  -DP - TeX source for text part of this work
  -dads.lite - Small development directory structure for simulating
                MBIST IP core. It is expecting installed Altera-ModelSim
                witch is shipped with Quartus 16.0 in /opt/altera/16.0 directory
  -sw -source codes for mbistgen application
       -Application requires POSIX environment, Tcl > 8.5 libraries,
        Bison and Flex to be available on computer
  -example - memory model of example memory (spram512x22cm4Mhz10)

Building
========

Go into sw/src directory and type:
  make

Expected output is:

gcc -std=c99 --pedantic -Wall -I /usr/include/tcl -I /usr/include/readline -ggdb -c main.c -o main.o
bison -d -v -Wall -p microcode_yy microcode.y -o microcode.tab.c
flex -P microcode_yy -o microcode.yy.c microcode.l
gcc -std=c99 --pedantic -Wall -I /usr/include/tcl -I /usr/include/readline -ggdb -c microcode.yy.c -o microcode.yy.o
gcc -std=c99 --pedantic -Wall -I /usr/include/tcl -I /usr/include/readline -ggdb -c microcode.tab.c -o microcode.tab.o
gcc -std=c99 --pedantic -Wall -I /usr/include/tcl -I /usr/include/readline -ggdb -c microcode.c -o microcode.o
bison -d -v -Wall -p lfsr_yy lfsr.y -o lfsr.tab.c
gcc -std=c99 --pedantic -Wall -I /usr/include/tcl -I /usr/include/readline -ggdb -c lfsr.tab.c -o lfsr.tab.o
gcc -std=c99 --pedantic -Wall -I /usr/include/tcl -I /usr/include/readline -ggdb -c ncnt.c -o ncnt.o
bison -d -v -Wall -p config_lvlib_yy config_lvlib.y -o config_lvlib.tab.c
gcc -std=c99 --pedantic -Wall -I /usr/include/tcl -I /usr/include/readline -ggdb -c config_lvlib.tab.c -o config_lvlib.tab.o
flex -P config_lvlib_yy -o config_lvlib.yy.c config_lvlib.l
gcc -std=c99 --pedantic -Wall -I /usr/include/tcl -I /usr/include/readline -ggdb -c config_lvlib.yy.c -o config_lvlib.yy.o
gcc -std=c99 --pedantic -Wall -I /usr/include/tcl -I /usr/include/readline -ggdb main.o microcode.yy.o microcode.tab.o microcode.o lfsr.tab.o ncnt.o config_lvlib.tab.o config_lvlib.yy.o -o mbistgen -ltcl -lreadline -lm  -Lcdk -lcdk
rm config_lvlib.yy.c microcode.tab.c microcode.yy.c lfsr.tab.c config_lvlib.tab.c
--END OF EXPECTED OUTPUT--

Then application is ready to use

Example usage
=============

To generate MATS++ BIST controller for memory in example directory (spram512x22cm4Mhz10)
(Algorithm MATS++ is stored in sw/src/march/MATS++.m, otherwise path to file can be provided)

mbistgen -s --memory (path)/example/spram512x22cm4Mhz10.lvlib --target (path)/dads.lite --name (name of memory) --algorithm MATS++

Successful generation log should look like, paths can vary:
Memory model file       : ../../smarch/model/spram512x22cm4Mhz10.lvlib
Target directory        : /projekty/mbist/dads.lite
Memory interface prefix : B
Selected algorithm      : march/MATS++.m
Generating interface for SSRAM ../../smarch/model/spram512x22cm4Mhz10.lvlib
        CellName: spram512x22cm4Mhz10
        Memory ports:  Q[21:0] QM ADR[8:0] D[21:0] WE ME CLK AWT BISTE RM[3:0] RME
        Row address width : 7
        Col address width : 2
        Number of bits in world: 22
        Target file : /projekty/mbist/dads.lite/hdl/rtl/mbist_mai_spram512x22cm4Mhz10.rtl.vhd
Test sequencer:
        Word width: 22
        Column counter width: 2
        Row counter width: 7
        March algorithm source: march/MATS++.m
        # microinstructions: 12
        Microinstruction address width: 4
        Row CFSR polynom: x^7 + x^1 + 1
        Column CFSR polynom: x^2 + x^1 + 1
        Target file: /projekty/mbist/dads.lite/hdl/rtl/mbist_ts_core.str.vhd
Generate BIST package
        Row width: 7
        Column width: 2
        Total number of bits in word: 22
        Microcode address width: 4
        Target file: /projekty/mbist/dads.lite/hdl/rtl/mbist_pkg.vhd
Generating TOP
        Target file : /projekty/mbist/dads.lite/hdl/rtl/mbist_top.str.vhd
Generating TB
        Target file : /projekty/mbist/dads.lite/hdl/model/tb.sv
Copying counters to target folder
Generating BFM
        Width of word: 22
        Width of row address: 7
        Width of column address: 2
        Length of microcode : 12
        Target file: /projekty/mbist/dads.lite/hdl/model/mbist.sv
Generating FOF
        Target file: /projekty/mbist/dads.lite/config/mbist.fof.tcl
--END OF EXPECTED OUTPUT--

Now in dads.lite we can run simulations:

source quartus/config.sh
quartus/sim.sh nogui mbist
quartus/sim.sh nogui serial

First one will test march algorithm error detection on memory. Second one will test serial access to memory.
