/*
  SMarchCHKBcil test algorithm
 
  Source: Tessent MemoryBIST User's and Reference Manual v2016.4
  
  Test coverage:
  ==========================================
  || |  Defect || Defect types | Coverage ||
  ==========================================
  ||S|  SaF    || 2            |          ||
  ||i|  SoF    || 1            |          ||
  ||n|  Tf     || 2            |          ||
  ||g|  DR     || 2            |          ||
  ||l|  dDR    || 2            |          ||
  ||e|  DRF    || 2            | 2        ||
  ||.|  WDF    || 2            |          ||
  ------------------------------------------
  ||C|  CDst   || 8            |          ||
  ||o|  CFid   || 8            |          ||
  ||u|  CFin   || 4            |          ||
  ||p|         ||              |          ||
  ||l|         ||              |          ||
  ||e|         ||              |          ||
  ||d|         ||              |          ||
  ========================================== 
*/

.((w1rx)^n, r1, w1) // \
.((w0r1)^n, r0, r0) // / Scans 1's and 0's trough data word. This will check data lines that they're intact

^|((wc0rcx)^n, rc0) // Write checkerboard 0 into memory
^|((wc0rc0)^n)      // Here we should have rx for another memory ports. This test controller currently support only single port memories.
                    // Stimulated defect would be Shadow Write 

DELAY               //Data retention delay (DRF(0))

^|((wc1rc0)^n)      // Write checkerboard 1 into memory
^|((wc1rc1)^n)      // Here we should have rx for another memory ports. This test controller currently support only single port memories.
                    // Stimulated defect would be Shadow Write 

DELAY               // Data retention delay (DRF(1))

^|((wc0rc1)^n)      // Inverse data in memory

.((w0rx)^n, r0, r0)
^_(w0,r0)           // Here should be rx but we can't say ignore data in standard march test
^_((w1r0)^n, r1,w1)
^_((w0r1)^n, r0,w0)
V_((w1r0)^n, r1,r1)
V_((w0r1)^n, r0,r0)
V_((w0r0)^n)        // Shadow Write should be on TBD cant implement phase 15 
.((w1rx)^n, r1,r1)
^_(w1, r1)
^_((w1r1)^n)        // TBD can't implement phase 18
.((w0r1)^n, w0, r0)
^_(w0, r0)
