/**
 * \file
 *
 * \brief User board definition template
 *
 */

 /* This file is intended to contain definitions and configuration details for
 * features and devices that are available on the board, e.g., frequency and
 * startup time for an external crystal, external memory devices, LED and USART
 * pins.
 */

#ifndef USER_BOARD_H
#define USER_BOARD_H

#include <conf_board.h>

/** Board oscillator settings */
#define BOARD_XOSC_HZ				(12000000U)
#define BOARD_XOSC_TYPE				XOSC_TYPE_XTAL
#define BOARD_XOSC_STARTUP_US		(500000U)

#define BOARD_FREQ_SLCK_XTAL        (32768U)
#define BOARD_FREQ_SLCK_BYPASS      BOARD_FREQ_SLCK_XTAL 
#define BOARD_FREQ_MAINCK_XTAL      (12000000U)
#define BOARD_FREQ_MAINCK_BYPASS    BOARD_FREQ_MAINCK_XTAL 
#define BOARD_OSC_STARTUP_US		(500000U)

/** Master clock frequency */
#define BOARD_MCK                   CHIP_FREQ_CPU_MAX

/*----------------------------------------------------------------------------*/
/**
 * \page digital_IO_USB_info "Digital I/O USB card - Board informations"
 * This page lists several definition related to the board description.
 *
 * \section Definitions
 * - \ref BOARD_NAME
 */

/** Name of the board */
#define BOARD_NAME "Digital I/O USB card"
/** Board definition */
#define sam3sek
/** Family definition (already defined) */
#define sam3s
/** Core definition */
#define cortexm3

/*----------------------------------------------------------------------------*/
/** USB */

#define USB_PIN_GPIO				PIO_PA31_IDX	// Out, H - Enable USB 
#define USB_PIN_FLAGS				(PIO_OUTPUT_1 | PIO_DEFAULT)

/** USB VBus monitoring pin definition. */
#define USB_VBUS_FLAGS				(PIO_INPUT | PIO_DEBOUNCE | PIO_IT_EDGE)
#define USB_VBUS_PIN_IRQn			(PIOB_IRQn)
#define USB_VBUS_PIO_ID				(ID_PIOB)
#define PIN_USB_VBUS				{PIO_PB13, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP}
#define USB_VBUS_PIN				(PIO_PB13_IDX)
#define USB_VBUS_PIO_MASK			(PIO_PB13)

/*-----------------------------------------------------------*/
/** Debug Console */

#define CONSOLE_UART				UART0
#define CONSOLE_UART_ID				ID_UART0

/*-----------------------------------------------------------*/
/** UART0 pins (UTXD0 and URXD0) definitions, PA9,10. */

#ifdef CONF_BOARD_UART_CONSOLE_RW 
	#define CONF_BOARD_UART_CONSOLE
	#define PINS_UART0				(PIO_PA9A_URXD0 | PIO_PA10A_UTXD0)
	#define PINS_UART0_MASK			PIO_PA9A_URXD0|PIO_PA10A_UTXD0
#endif

#ifdef CONF_BOARD_UART_CONSOLE_W
	#define CONF_BOARD_UART_CONSOLE
	#define PINS_UART0				(PIO_PA10A_UTXD0)
	#define PINS_UART0_MASK			PIO_PA10A_UTXD0
#endif


#define PINS_UART0_FLAGS			(PIO_PERIPH_A | PIO_DEFAULT)
#define PINS_UART0_PIO				PIOA
#define PINS_UART0_ID				ID_PIOA
#define PINS_UART0_TYPE				PIO_PERIPH_A
#define PINS_UART0_ATTR				PIO_DEFAULT

/*-----------------------------------------------------------*/
/* TWI configuration */

/** TWI0 pins definition */
#define TWI0_DATA_GPIO				PIO_PA3_IDX
#define TWI0_DATA_FLAGS				(PIO_PERIPH_A | PIO_DEFAULT)
#define TWI0_CLK_GPIO				PIO_PA4_IDX
#define TWI0_CLK_FLAGS				(PIO_PERIPH_A | PIO_DEFAULT)

/** TWI1 pins definition */
#define TWI1_DATA_GPIO				PIO_PB4_IDX
#define TWI1_DATA_FLAGS				(PIO_PERIPH_A | PIO_DEFAULT)
#define TWI1_CLK_GPIO				PIO_PB5_IDX
#define TWI1_CLK_FLAGS				(PIO_PERIPH_A | PIO_DEFAULT)

/*-----------------------------------------------------------*/
/** I/O Expander */

#define IOEXP_INT_GPIO				PIO_PA5_IDX	// In, L - Px port fault

/* Run LED */

#define IOEXP_RUN_LED_MASK			IOEXP_P01_MASK
#define IOEXP_RUN_LED_ACTIVE		ioexp_get_high_active_mask(IOEXP_RUN_LED_MASK)

/* Power for ports */

#define IOEXP_PX_PWR_MASK			IOEXP_P06_MASK
#define IOEXP_PX_PWR_ACTIVE			ioexp_get_high_active_mask(IOEXP_PX_PWR_MASK)
#define IOEXP_PX_OE_MASK			IOEXP_P07_MASK
#define IOEXP_PX_OE_ACTIVE			ioexp_get_low_active_mask(IOEXP_P07_MASK)

/* Pull up/down resistors */

/* Port A */
#define IOEXP_PA_PULL_RES_MASK		IOEXP_P13_MASK
#define IOEXP_PA_PULL_RES_ENABLE	ioexp_get_low_active_mask(IOEXP_PA_PULL_RES_MASK)
#define IOEXP_PA_PULL_RES_DISABLE	ioexp_get_high_active_mask(IOEXP_PA_PULL_RES_MASK)
#define IOEXP_PA_PULL_UP_RES		ioexp_get_high_active_mask(IOEXP_PA_PULL_RES_MASK)
#define IOEXP_PA_PULL_DOWN_RES		ioexp_get_low_active_mask(IOEXP_PA_PULL_RES_MASK)
/* Port B */
#define IOEXP_PB_PULL_RES_MASK		IOEXP_P10_MASK
#define IOEXP_PB_PULL_RES_ENABLE	ioexp_get_low_active_mask(IOEXP_PB_PULL_RES_MASK)
#define IOEXP_PB_PULL_RES_DISABLE	ioexp_get_high_active_mask(IOEXP_PB_PULL_RES_MASK)
#define IOEXP_PB_PULL_UP_RES		ioexp_get_high_active_mask(IOEXP_PB_PULL_RES_MASK)
#define IOEXP_PB_PULL_DOWN_RES		ioexp_get_low_active_mask(IOEXP_PB_PULL_RES_MASK)
/* Port C */
#define IOEXP_PC_PULL_RES_MASK		IOEXP_P11_MASK
#define IOEXP_PC_PULL_RES_ENABLE	ioexp_get_low_active_mask(IOEXP_PC_PULL_RES_MASK)
#define IOEXP_PC_PULL_RES_DISABLE	ioexp_get_high_active_mask(IOEXP_PC_PULL_RES_MASK)
#define IOEXP_PC_PULL_UP_RES		ioexp_get_high_active_mask(IOEXP_PC_PULL_RES_MASK)
#define IOEXP_PC_PULL_DOWN_RES		ioexp_get_low_active_mask(IOEXP_PC_PULL_RES_MASK)
/* Port D */
#define IOEXP_PD_PULL_RES_MASK		IOEXP_P12_MASK
#define IOEXP_PD_PULL_RES_ENABLE	ioexp_get_low_active_mask(IOEXP_PD_PULL_RES_MASK)
#define IOEXP_PD_PULL_RES_DISABLE	ioexp_get_high_active_mask(IOEXP_PD_PULL_RES_MASK)
#define IOEXP_PD_PULL_UP_RES		ioexp_get_high_active_mask(IOEXP_PD_PULL_RES_MASK)
#define IOEXP_PD_PULL_DOWN_RES		ioexp_get_low_active_mask(IOEXP_PD_PULL_RES_MASK)
/* General */
#define IOEXP_PX_PULL_RES_MASK		(IOEXP_PA_PULL_RES_MASK		| IOEXP_PB_PULL_RES_MASK	| IOEXP_PC_PULL_RES_MASK	| IOEXP_PD_PULL_RES_MASK)
#define IOEXP_PX_PULL_RES_ENABLE	(IOEXP_PA_PULL_RES_ENABLE	| IOEXP_PB_PULL_RES_ENABLE	| IOEXP_PC_PULL_RES_ENABLE	| IOEXP_PD_PULL_RES_ENABLE)
#define IOEXP_PX_PULL_RES_DISABLE	(IOEXP_PA_PULL_RES_DISABLE	| IOEXP_PB_PULL_RES_DISABLE | IOEXP_PC_PULL_RES_DISABLE | IOEXP_PD_PULL_RES_DISABLE)
#define IOEXP_PX_PULL_UP_RES		(IOEXP_PA_PULL_UP_RES		| IOEXP_PB_PULL_UP_RES		| IOEXP_PC_PULL_UP_RES		| IOEXP_PD_PULL_UP_RES)
#define IOEXP_PX_PULL_DOWN_RES		(IOEXP_PA_PULL_DOWN_RES		| IOEXP_PB_PULL_DOWN_RES	| IOEXP_PC_PULL_DOWN_RES	| IOEXP_PD_PULL_DOWN_RES)



/* Direction of ports */

/* Port A */
#define IOEXP_PA_DIR_MASK			IOEXP_P17_MASK
#define IOEXP_PA_DIR_OUTPUT			ioexp_get_low_active_mask(IOEXP_PA_DIR_MASK)
#define IOEXP_PA_DIR_INPUT			ioexp_get_high_active_mask(IOEXP_PA_DIR_MASK)
/* Port B */
#define IOEXP_PB_DIR_MASK			IOEXP_P15_MASK
#define IOEXP_PB_DIR_OUTPUT			ioexp_get_low_active_mask(IOEXP_PB_DIR_MASK)
#define IOEXP_PB_DIR_INPUT			ioexp_get_high_active_mask(IOEXP_PB_DIR_MASK)
/* Port C */
#define IOEXP_PC_DIR_MASK			IOEXP_P14_MASK
#define IOEXP_PC_DIR_OUTPUT			ioexp_get_low_active_mask(IOEXP_PC_DIR_MASK)
#define IOEXP_PC_DIR_INPUT			ioexp_get_high_active_mask(IOEXP_PC_DIR_MASK)
/* Port D */
#define IOEXP_PD_DIR_MASK			IOEXP_P16_MASK
#define IOEXP_PD_DIR_OUTPUT			ioexp_get_low_active_mask(IOEXP_PD_DIR_MASK)
#define IOEXP_PD_DIR_INPUT			ioexp_get_high_active_mask(IOEXP_PD_DIR_MASK)
#define IOEXP_PX_DIR_MASK			(IOEXP_PA_DIR_MASK | IOEXP_PB_DIR_MASK | IOEXP_PC_DIR_MASK | IOEXP_PD_DIR_MASK)
/* General */
#define IOEXP_PX_DIR_OUTPUT			ioexp_get_low_active_mask(IOEXP_PX_DIR_MASK)
#define IOEXP_PX_DIR_INPUT			ioexp_get_high_active_mask(IOEXP_PX_DIR_MASK)


/* Port fault signals */

/* Port A - D */
#define IOEXP_PA_FAULT_MASK			IOEXP_P05_MASK
#define IOEXP_PB_FAULT_MASK			IOEXP_P03_MASK
#define IOEXP_PC_FAULT_MASK			IOEXP_P02_MASK
#define IOEXP_PD_FAULT_MASK			IOEXP_P04_MASK
/* General */
#define IOEXP_PX_FAULT_MASK			(IOEXP_PA_FAULT_MASK | IOEXP_PB_FAULT_MASK | IOEXP_PC_FAULT_MASK | IOEXP_PD_FAULT_MASK)
#define IOEXP_PX_FAULT_ACTIVE		ioexp_get_low_active_mask(IOEXP_PX_FAULT_MASK)

/* TWI configuration */

#define IOEXP_TWI_ADDR				((uint8_t )0x20)
#define IOEXP_TWI_CLOCK_HZ			(400000UL)
#define IOEXP_TWI_ID				ID_TWI0
#define IOEXP_TWI_BASE				TWI0	/* Instance of TWI */
#define IOEXP_TWI_DATA_GPIO			TWI0_DATA_GPIO
#define IOEXP_TWI_DATA_FLAGS		TWI0_DATA_FLAGS
#define IOEXP_TWI_CLK_GPIO			TWI0_CLK_GPIO
#define IOEXP_TWI_CLK_FLAGS			TWI0_CLK_FLAGS

/*-----------------------------------------------------------*/
/** Digital I/O Interface */

/* Port A */
#define DIO_PA0_GPIO				PIO_PC17_IDX	
#define DIO_PA1_GPIO				PIO_PC16_IDX
#define DIO_PA2_GPIO				PIO_PA2_IDX
#define DIO_PA3_GPIO				PIO_PC10_IDX
#define DIO_PA4_GPIO				PIO_PA30_IDX
#define DIO_PA5_GPIO				PIO_PA29_IDX
#define DIO_PA6_GPIO				PIO_PC9_IDX
#define DIO_PA7_GPIO				PIO_PA28_IDX
/* Port B */
#define DIO_PB0_GPIO				PIO_PA13_IDX
#define DIO_PB1_GPIO				PIO_PA14_IDX
#define DIO_PB2_GPIO				PIO_PA15_IDX
#define DIO_PB3_GPIO				PIO_PA16_IDX
#define DIO_PB4_GPIO				PIO_PC12_IDX
#define DIO_PB5_GPIO				PIO_PA23_IDX
#define DIO_PB6_GPIO				PIO_PC13_IDX
#define DIO_PB7_GPIO				PIO_PA22_IDX
/* Port C */
#define DIO_PC0_GPIO				PIO_PC15_IDX
#define DIO_PC1_GPIO				PIO_PA21_IDX
#define DIO_PC2_GPIO				PIO_PA17_IDX
#define DIO_PC3_GPIO				PIO_PB3_IDX
#define DIO_PC4_GPIO				PIO_PB2_IDX
#define DIO_PC5_GPIO				PIO_PB1_IDX
#define DIO_PC6_GPIO				PIO_PB0_IDX
#define DIO_PC7_GPIO				PIO_PB14_IDX
/* Port D */
#define DIO_PD0_GPIO				PIO_PA6_IDX
#define DIO_PD1_GPIO				PIO_PA27_IDX
#define DIO_PD2_GPIO				PIO_PA9_IDX
#define DIO_PD3_GPIO				PIO_PA11_IDX
#define DIO_PD4_GPIO				PIO_PA12_IDX
#define DIO_PD5_GPIO				PIO_PA26_IDX
#define DIO_PD6_GPIO				PIO_PA25_IDX
#define DIO_PD7_GPIO				PIO_PA24_IDX

#define DIO_FLAGS					(PIO_PULLUP)
#define DIO_PORT_A					0
#define DIO_PORT_B					1
#define DIO_PORT_C					2
#define DIO_PORT_D					3

/*-----------------------------------------------------------*/
/** SRAM memory */

/** Memory controls signals */

/** EBI NRD pin */
#define PIN_EBI_NRD                 PIO_PC11_IDX
#define PIN_EBI_NRD_FLAGS			(PIO_PERIPH_A | PIO_PULLUP)
#define PIN_EBI_NRD_MASK			(1 << 11)
#define PIN_EBI_NRD_PIO				PIOC
#define PIN_EBI_NRD_ID				ID_PIOC
#define PIN_EBI_NRD_TYPE			PIO_PERIPH_A
#define PIN_EBI_NRD_ATTR			PIO_PULLUP
/** EBI NWE pin */
#define PIN_EBI_NWE                 PIO_PC8_IDX
#define PIN_EBI_NWE_FLAGS			(PIO_PERIPH_A | PIO_PULLUP)
#define PIN_EBI_NWE_MASK			(1 << 8)
#define PIN_EBI_NWE_PIO				PIOC
#define PIN_EBI_NWE_ID				ID_PIOC
#define PIN_EBI_NWE_TYPE			PIO_PERIPH_A
#define PIN_EBI_NWE_ATTR			PIO_PULLUP
/** EBI NCS0 pin */
#ifndef CONF_BOARD_SMC_SRAM_FORCE_NCS		// NCS0 will be generate by SMC
	#define PIN_EBI_NCS0            PIO_PC14_IDX
	#define PIN_EBI_NCS0_FLAGS		(PIO_PERIPH_A | PIO_PULLUP)
	#define PIN_EBI_NCS0_MASK		(1 << 14)
	#define PIN_EBI_NCS0_PIO		PIOC
	#define PIN_EBI_NCS0_ID			ID_PIOC
	#define PIN_EBI_NCS0_TYPE		PIO_PERIPH_A
	#define PIN_EBI_NCS0_ATTR		PIO_PULLUP
#else										// force NCS0 to Low for select SRAM
	#define PIN_EBI_NCS0            PIO_PC14_IDX
	#define PIN_EBI_NCS0_FLAGS		(PIO_OUTPUT_0 | PIO_PULLUP)
	#define PIN_EBI_NCS0_MASK		(1 << 14)
	#define PIN_EBI_NCS0_PIO		PIOC
	#define PIN_EBI_NCS0_ID			ID_PIOC
	#define PIN_EBI_NCS0_TYPE		PIO_OUTPUT_0
	#define PIN_EBI_NCS0_ATTR		PIO_PULLUP
#endif

/** EBI Data Bus pins */

#define PIN_EBI_DATA_BUS_D0			PIO_PC0_IDX
#define PIN_EBI_DATA_BUS_D1			PIO_PC1_IDX
#define PIN_EBI_DATA_BUS_D2			PIO_PC2_IDX
#define PIN_EBI_DATA_BUS_D3			PIO_PC3_IDX
#define PIN_EBI_DATA_BUS_D4			PIO_PC4_IDX
#define PIN_EBI_DATA_BUS_D5			PIO_PC5_IDX
#define PIN_EBI_DATA_BUS_D6			PIO_PC6_IDX
#define PIN_EBI_DATA_BUS_D7			PIO_PC7_IDX
#define PIN_EBI_DATA_BUS_FLAGS      (PIO_PERIPH_A | PIO_PULLUP)
#define PIN_EBI_DATA_BUS_MASK		0xFF
#define PIN_EBI_DATA_BUS_PIO		PIOC
#define PIN_EBI_DATA_BUS_ID			ID_PIOC
#define PIN_EBI_DATA_BUS_TYPE		PIO_PERIPH_A
#define PIN_EBI_DATA_BUS_ATTR		PIO_PULLUP

/** EBI address bus pins  */

#define PIN_EBI_ADDR_BUS_A0			PIO_PC18_IDX
#define PIN_EBI_ADDR_BUS_A1			PIO_PC19_IDX
#define PIN_EBI_ADDR_BUS_A2			PIO_PC20_IDX
#define PIN_EBI_ADDR_BUS_A3			PIO_PC21_IDX
#define PIN_EBI_ADDR_BUS_A4			PIO_PC22_IDX
#define PIN_EBI_ADDR_BUS_A5			PIO_PC23_IDX
#define PIN_EBI_ADDR_BUS_A6			PIO_PC24_IDX
#define PIN_EBI_ADDR_BUS_A7			PIO_PC25_IDX
#define PIN_EBI_ADDR_BUS_A8			PIO_PC26_IDX
#define PIN_EBI_ADDR_BUS_A9			PIO_PC27_IDX
#define PIN_EBI_ADDR_BUS_A10		PIO_PC28_IDX
#define PIN_EBI_ADDR_BUS_A11		PIO_PC29_IDX
#define PIN_EBI_ADDR_BUS_A12		PIO_PC30_IDX
#define PIN_EBI_ADDR_BUS_A13		PIO_PC31_IDX
#define PIN_EBI_ADDR_BUS_FLAG1		(PIO_PERIPH_A | PIO_PULLUP)
#define PIN_EBI_ADDR_BUS_A14		PIO_PA18_IDX
#define PIN_EBI_ADDR_BUS_A15		PIO_PA19_IDX
#define PIN_EBI_ADDR_BUS_A16		PIO_PA20_IDX
#define PIN_EBI_ADDR_BUS_A17		PIO_PA0_IDX
#define PIN_EBI_ADDR_BUS_A18		PIO_PA1_IDX
/** Not used */
#define PIN_EBI_ADDR_BUS_A19		PIO_PA23_IDX
#define PIN_EBI_ADDR_BUS_A20		PIO_PA24_IDX
#define PIN_EBI_ADDR_BUS_FLAG2		(PIO_PERIPH_C | PIO_PULLUP)


#endif // USER_BOARD_H
