\chapter{Time to Digital Converters}
\label{chapter:tdcs}

\acfp{TDC} are a key part of the \ac{DToF} \ac{LIDAR} signal path. They do not only define the distance resolution and maximum measurable range. Just like \acp{ADC}, they exhibit non-linearity, noise or a non-zero conversion time. And because modern \ac{DToF} \ac{LIDAR} detectors contain hundreds to thousands of pixels, the chip does not contain only one \ac{TDC}, but commonly at least a few hundreds of them. Therefore, the \acp{TDC} represent a large part of the overall footprint and the power consumption. That is why the \ac{TDC} design deserves special attention and a chapter of its own.

In this chapter, firstly, general requirements for the \ac{TDC} will be discussed. Afterwards, three main types of \acp{TDC} will be presented. A section on \acp{DLL} will be included as well, as these circuits are a crucial part of many popular \ac{TDC} topologies today.

\section{General considerations}

In this section, general aspects of the \ac{TDC} will be discussed. First, its full scale and resolution specifications, important for the topology of the \ac{TDC}, will be described. A subsection detailing the overall architecture of the \ac{TDC} array will follow. Finally, two subsection about more power efficient or linearity improving timing schemes will close this section.

\subsection{Full scale and resolution}

The \autoref{fig:time_vs_dist} plots the linear relationship between the distance to the obstacle and the time the photon travels to the obstacle and back, i.e. the \ac{ToF} (see \autoref{eq:ToF_to_distance}).

\begin{figure}[htb]
	\centering
	\includegraphics[width=14.5cm]{grafy/time_vs_distance.pdf}
	\vspace{-0.5cm}
	\caption{Time of flight of a reflected photon as a function of distance to the obstacle} \label{fig:time_vs_dist}\vspace{-0.3cm}
\end{figure}

For automotive applications, the desired maximum range usually lies in the order of a few hundred meters. This is the range required to be able to measure to distance to other cars on the highway, or to be able to brake in time in case an obstacle appears on the road.

On the other hand, the desired minimum resolution is on the order of a few centimetres or even sub-centimetre. This is not only because such \ac{LIDAR} can be used as a parking assist, but also because modern \ac{ADAS} do not use \ac{LIDAR} data to measure the distance to obstacles or other cars only, but they can follow the time evolution of the 3D point cloud in order to gauge the velocity of the surrounding objects relative to the observer as well. For this velocity measuring ability, high resolution is beneficial.

Assuming the maximum range required is \SI{150}{\meter} with a resolution of \SI{1}{\centi\meter}, the full scale of the \ac{TDC} should correspond to \SI{1}{\micro\second} with a resolution of \SI{66}{\pico\second}. This is a dynamic range of \SI{83}{\deci\bel}, requiring a minimum of 14 bits. 

Such a \ac{TDC} is not trivial, and no single topology is capable of meeting such requirements in a power and area efficient manner. Instead, the problem is split into two smaller, more easily manageable parts: the so-called \ac{CTDC} and \ac{FTDC}. The \ac{CTDC} measures time coarsely (i.e. with a low resolution), and determines the full scale range. The \ac{FTDC} splits the \ac{LSB} of the \ac{CTDC} even more finely, achieving the required resolution of the overall \ac{TDC}. The bits coming from the \ac{CTDC} form the most significant bits of the overal \ac{TDC} output bus, while the \ac{FTDC} output bits are appended as the least significant bits. 

By splitting the \ac{TDC} into two distinct parts, optimal \ac{TDC} topologies can be chosen for the \ac{CTDC} and \ac{FTDC} separately.

\subsection{\acs{TDC} array architecture}

As was mentioned in the introduction to this chapter, due to the number of pixels in the detector array, having only one \ac{TDC} is not viable. It could be theoretically feasible if the level of illumination of the detector was extremely low and the rate of incoming photons would be smaller than the conversion rate of the \ac{TDC}, but for any daylight application, this is not the case.

There are two main approaches to the number of \acp{TDC} in the \ac{TDC} array. Either there could be one \ac{TDC} for each pixel of the detector array (so-called in-pixel \ac{TDC}), or there could be a smaller \ac{TDC} bank, which will be somehow allocated to the detector array dynamically.

For flash \ac{LIDAR}, it might seem that in-pixel \acp{TDC} is the optimal choice. While this approach makes sense, as there is a \ac{TDC} available for every pixel at any time, and has been demonstrated in practice by \cite{flash_inpixel} or \cite{flash_inpixel_ti}, it has its shortcomings, which are mainly the comparatively large power consumption of the large number of concurrently running \acp{TDC} and the decrease of \ac{SPAD} fill factor, as in-pixel \acp{TDC} take up pixel area. 

Flash \ac{LIDAR} using a \ac{TDC} bank has been presented in \cite{flash_example}, where 36288 pixels share a bank of 1728 \acp{TDC}. The dynamic allocation is done with a collision detection bus. This approach has allowed the authors to achieve a relatively high \ac{SPAD} fill factor (28 \%) on a single die, although they do not comment on the frame rate, the maximum allowable incoming photon rate and other related performance characteristics, which might potentially suffer, as the \ac{TDC} allocation takes time which decreases the effective conversion rate.

Scanning or sequential flash \ac{LIDAR} are more flexible. In-pixel \acp{TDC} can be implemented, but only small sections of the array can be activated at any given time time, corresponding to the section being illuminated by the laser scanner. This decreases the power consumption significantly.

The inherent trade-off between \ac{SPAD} fill factor and the in-pixel \ac{TDC} area can be also solved with 3D stacking technologies \cite[p.5]{chao_thesis}, which allow the use of one die for \acp{SPAD} only, while a second die includes all the readout and processing circuits. An advantage of this approach is not just the very high \ac{SPAD} fill factor (approaching \mbox{100 \%}) but the fact that the two dies can be fabricated in different process technologies, optimizing the optical characteristics of \acs{SPAD} and circuit characteristics for the digital \ac{CMOS} die separately.

\subsection{Reverse timing scheme}
\label{subsec:reverse_timing}

The START-STOP timing scheme described in \autoref{sec:lidar_overview}, where the START signal is produced by the laser trigger and the STOP signals are produced by the detector array, is intuitive and its implementation is straightforward.

However, let us suppose that there are 1000 \acp{TDC} in a \ac{TDC} bank, all of which start counting the moment the laser is fired. Let us also suppose that only 300 \acp{SPAD} detect a photon and stop their respective \ac{TDC} before the time runs out and another laser pulse is fired. Clearly, 700 out of the 1000 \acp{TDC} did not produce any meaningful conversion, while still consuming power.

A reverse timing scheme fixes this issue. Instead of the \acp{TDC} being started by the laser trigger, they are started individually at various time instants by photon detections. The STOP signal is then synchronized to the next laser pulse. The equation for \ac{ToF} for such a reversed timing scheme is no longer

\begin{equation}
\mathit{ToF} = t_\mathrm{STOP}-t_\mathrm{START}
\end{equation}

but instead

\begin{equation}
\mathit{ToF} = T_\mathrm{cycle}-(t_\mathrm{STOP}-t_\mathrm{START})
\end{equation}

where $T_\mathrm{cycle}$ is the period of the laser pulsing cycle.

This timing scheme is more energy efficient, as the \acp{TDC} spend most of the time in idle mode, waiting for the detection, and only consume significant power when producing valid conversions.

\subsection{Sliding scale technique}
\label{subsec:sliding}

If the reverse timing scheme (described in \autoref{subsec:reverse_timing}) is used, the START signal is a pulse produced by a \ac{SPAD} from the detector array, while the STOP signal is synchronized to the laser pulse trigger. Because the laser trigger is periodic, if the same \ac{ToF} is measured (the same distance to an obstacle), the same part of the \ac{TDC} range is exercised every single time. The measurements therefore have a systematic error due to the \ac{INL} at the given point of the transfer characteristic.

The sliding scale technique is a well known technique in \ac{ADC} design, invented by Cottini et al. in 1963 \cite{sliding_scale}. Its purpose is to improve linearity at the cost of noise. A random but known analog noise is added to the converted signal and then subtracted in the digital domain. Even if the magnitude of the converted signal does not change, due to the noise, different parts of the converter range are utilized during repeated conversions. Therefore, the non-linearity can be averaged out over time.

The same method can be applied to \acp{TDC}. Sliding scale \acp{TDC} do not measure the time interval between the START and STOP signals, but instead measure the time intervals between the START and the reference signal, and the STOP and the reference signal. Because the reference signal is asynchronous with respect to the periodic STOP signal, different portions of the \ac{TDC} range are utilized each measurement cycle and the non-linearity at various points of the transfer characteristic is converted into random noise of the resulting conversions.

An illustration of the sliding scale technique as applied to \acp{TDC} is depicted on \autoref{fig:sliding_scale}. 

\begin{figure}[htb]
	\centering
	\includegraphics[width=14.5cm]{obrazky/sliding_scale.pdf}
	\vspace{-0.3cm}
	\caption{Sliding scale \acs{TDC} illustration} \label{fig:sliding_scale}\vspace{-0.3cm}
\end{figure}

The illustration assumes that the \ac{TDC} consists of coarse and fine \acp{TDC}, where the \ac{CTDC} counts the number of reference clock periods from when START went high until STOP goes high. The depicted \ac{FTDC} slices the reference clock period into 8 smaller slices (i.e. it is a 3-bit \ac{FTDC}), and it counts the number of these slices since START went high until the first reference clock rising edge, and the same for the STOP signal. The final conversion result is therefore

\begin{equation}
T_\mathrm{result} = T_\mathrm{REF}\cdot{C_\mathrm{coarse}} + t_\mathrm{fine}\cdot(C_\mathrm{start}-C_\mathrm{stop})
\end{equation}

While this technique improves the linearity of the \ac{TDC}, it only does so if repeated conversions of the same time interval are performed and averaged in the \ac{DSP}. Moreover, the single shot precision is actually decreased, because there are two separate quantizing events, each contributing quantization noise. Finally, the technique also requires two \ac{FTDC} copies in each \ac{TDC} block. Although in the illustration on \autoref{fig:sliding_scale} it might appear as if one \ac{FTDC} is enough to count both $C_\mathrm{start}$ and $C_\mathrm{stop}$, it is possible for the STOP rising edge to occur very shortly after the START rising edge, possibly even before $C_\mathrm{start}$ count is finished. In such a case, one \ac{FTDC} would not be able to count both counts concurrently.

\section{Counter based TDCs}
\label{sec:ctdc}

Digital counters are the simplest \acp{TDC} imaginable and they are the implementation of choice for \acp{CTDC}. Their design is straightforward, they are power efficient and increasing their range is often as easy as adding another flip-flop. 

On the other hand, due to non-zero setup and hold times, there is a maximum operating frequency they can reliably count at. This depends on the topology of the counter (synchronous/asynchronous), the standard cells used and the \ac{CMOS} processing technology itself. In either case, operating frequencies over a \SI{}{\giga\hertz} and therefore resolution better than high hundreds of picoseconds are only possible in the most cutting edge processes.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{obrazky/ripple_async.pdf}
	\vspace{-0.3cm}
	\caption{Asynchronous ripple counter} \label{fig:ripple_async}\vspace{-0.3cm}
\end{figure}

A popular counter topology is the asynchronous ripple counter, depicted on \autoref{fig:ripple_async}. Its main advantages are high operating frequency, low power consumption and small size, as it contains no combinational logic and scales extremely well. On the other hand, the counting signals count asynchronously and can be in invalid or metastable states until the counter settles. A synchronizing circuit, which is necessary to interface the counter with synchronous logic, might sample incorrect data which has not settled yet. A conversion to Gray code can be performed to decrease the size of the possible error, as with Gray code, the binary representation changes from one state to the next by flipping only one bit at a time.

Another option is to use a synchronous counter which counts in Gray code directly, as in \cite[p.69]{ilo_thesis}. Its maximum operating frequency is lower and it requires extra combinational logic and therefore has larger area and power consumption, but it does not require synchronization circuits.

\section{Delay Locked Loops}
\label{sec:dll}

\acfp{DLL} are a common part of popular \ac{FTDC} topologies and it is necessary to provide a brief, qualitative description of their operation before proceeding.

\acp{DLL} share some commonalities with their better known counterparts, the \acp{PLL}. In comparison, \acp{DLL} are simpler, but also more limited in their application. They are mostly used for clock recovery, zero-delay clock buffers, multiphase clock generation or for \ac{PVT} immune biasing of controllable \acp{DLU}. The last two applications are of interest for the purpose of implementing \acp{FTDC}.

\begin{figure}[htb]
	\centering
	\includegraphics[width=12cm]{obrazky/dll.pdf}
	\vspace{-0.3cm}
	\caption{\acl{DLL} illustration} \label{fig:dll}\vspace{-0.3cm}
\end{figure}

The illustration on \autoref{fig:dll} shows an example of a \ac{DLL}. A clock signal is connected to a controllable delay line made up from four \acp{VCDLU}. Each \ac{VCDLU} delays its input signal by $t_\mathrm{d}$, which is variable. The output of the last \ac{VCDLU} and the original clock input are both connected to a phase detector, which compares the phase shift between the two signals and produces a digital pulse proportional to the size of the phase shift at its output. The output of the phase detector is low pass filtered and applied to the \acp{VCDLU} as the control input. The negative feedback loop adjusts the delay of the \acp{VCDLU}, until the phase shift between the clock signal at the input and at the output of the delay line is 360°, i.e. the phase detector detects no difference. Since the delay line on \autoref{fig:dll} consists of four elements, the intermediate signals of the delay line are phase shifted by $\frac{\SI{360}{\degree}}{4}=\SI{90}{\degree}$. This particular \ac{DLL} circuit therefore serves as a multiphase clock generator.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14.5cm]{obrazky/dll_bias.pdf}
	\vspace{-0.3cm}
	\caption{\acs{DLL}-assisted \acs{PVT} immune \acs{VCDLU} biasing} \label{fig:dll_biasing}\vspace{-0.3cm}
\end{figure}

Another common use of \acp{DLL} in \acp{FTDC} is \ac{PVT} immune \ac{DLU} biasing, as showcased on \autoref{fig:dll_biasing}. Assuming the loop is able to lock, the following equation can be written
\begin{equation}
t_\mathrm{d} = \frac{T_\mathrm{CLK}}{N} = \frac{1}{f_\mathrm{CLK}{\cdot}N}
\end{equation}

and this relationship will be followed regardless of temperature, supply voltage or process skew. This method however requires high quality clock source and does not account for mismatch between the \acp{DLU}.

\acp{DLL} have a limited locking range. The limitation is determined by all three parts of the \ac{DLL}: the delay line, the phase detector and the low pass filter. Firstly, for a \ac{DLL} to be able to lock, the delay line needs to be able to produce a $2\pi$ phase shift for the given input clock frequency. However, it would be undesirable if the delay line was able to produce a phase shift of $4\pi$ or more, as in that case, it would be possible for the \ac{DLL} to lock to the input signal delayed by two periods (instead of just one) by creating too large of a delay in the \acp{DLU}. This is called false locking and is problematic, as in such case, the \acp{DLU} present higher RC constants and attenuate the input clock, increasing jitter. More complex phase detector implementations or initialization of the \acp{DLU} at the lower end of their delay range can alleviate this \cite[p.16]{dll_overview}. Lastly, the bandwidth of the phase detector or the low pass filter can prevent locking to higher input clock frequencies, though that is something the designer should be able to avoid.

Contrary to a \ac{PLL}, a \ac{DLL} has only one pole, which is given by the filter (assuming first order approximation) \cite[p.10]{dll_thesis}. It is therefore unconditionally stable. The commonly used filter is an integrator, as it guarantees zero error at \acs{DC}. It also integrates well into the system. Phase detectors usually have two output bits: $\mathit{UP}$ and $\mathit{DWN}$, which go active depending on whether the delay line is supposed to delay the input clock less or more. Therefore, implementing an integrating filter can be done with a simple charge pump, as presented on \autoref{fig:charge_pump_dll}. 

\begin{figure}[htb]
	\centering
	\includegraphics[width=14.5cm]{obrazky/charge_pump.pdf}
	\vspace{-0.3cm}
	\caption{Simplified charge pump based \acl{DLL} control circuits} \label{fig:charge_pump_dll}\vspace{-0.3cm}
\end{figure}

This particular illustration of \ac{DLL} control circuits also depicts a V-to-I converter, used for driving \acp{CCDLU}. This implementation has its benefits, as replicating current with current mirrors and routing it to the point of use is simple and less sensitive to crosstalk, noise, \ac{VDD} variation or IR drops than routing voltage signals.

\subsection{Delay Line Unit circuits}
\label{subsec:dlu}

There are many types of \ac{DLU} implementations. \acp{DLU} can be voltage controlled (\acs{VCDLU}) or current controlled (\acs{CCDLU}) and the mechanism allowing the control of the propagation delay can be based on variable resistance, capacitance or current. A few typical \ac{DLU} implementations will be presented.

\begin{figure}[htb]
	\centering
	\includegraphics[width=5cm]{obrazky/current_starved_invertor.pdf}
	\vspace{-0.3cm}
	\caption{Current starved inverter} \label{fig:starved}\vspace{-0.3cm}
\end{figure}

A classic circuit called \enquote{the current starved inverter} is shown on \autoref{fig:starved}. The lowermost NMOS and the uppermost PMOS function as current sources, which can limit the current available to charge the output capacitance of the inverter. The biasing voltages determining the current are generated with current mirrors, which are not depicted.

\begin{figure}[htb]
	\centering
	\includegraphics[width=7cm]{obrazky/linear_vcdlu.pdf}
	\vspace{-0.3cm}
	\caption{High linearity \acl{VCDLU}} \label{fig:lin_vcdlu}\vspace{-0.3cm}
\end{figure}

A different approach is depicted on \autoref{fig:lin_vcdlu}. The control voltage adjusts the switching resistance of the NMOS connecting the lower PMOS diode to the output node. The PMOS diode diverts some of the current used to charge the output node capacitance to ground, therefore the higher the $V_\mathrm{ctrl}$, the higher the delay. This \ac{VCDLU} demonstrates high linearity of the $t_\mathrm{d} = f(V_\mathrm{ctrl})$ function (as long as $V_\mathrm{ctrl} > V_\mathrm{th,N}$), as proven by \cite{lin_vcdlu}, where it was used to construct a \SI{17}{\pico\second} resolution \ac{TDC}.

An alternative to the PMOS diode can be a MOS capacitor. In such implementations, increasing $V_\mathrm{ctrl}$ increases the effective capacitance at the output.

\begin{figure}[htb]
	\centering
	\includegraphics[width=8cm]{obrazky/ccdlu.pdf}
	\vspace{-0.3cm}
	\caption{Differential \acl{CCDLU}} \label{fig:diff_ccdlu}\vspace{-0.3cm}
\end{figure}

Differential delay lines or differential ring oscillators offer some advantageous properties to single ended solutions, mainly in the area of common mode noise or power supply rejection. There are many options of implementing a differential delay unit, an example of which is on \autoref{fig:diff_ccdlu} \cite{ilo_paper}. This cell consists of two inverters with additional positive feedback provided by the cross-connected PMOS transistors, which allows fast synchronized transitions. The delay of the cell is controlled by the current $I_\mathrm{ctrl}$, therefore the principle is similar to the current starved inverter from \autoref{fig:starved}. Routing biasing currents over larger distances is beneficial to routing biasing voltages, as current signals are in general less sensitive to \ac{VDD} disturbances, noise, IR drops and other sources of error.

It has to be noted that the presence of the current sources in the current branch of both single-ended and differential current starved \acp{DLU} limits the input voltage range and different solutions might suit low voltage applications better.

\section{Propagation delay based TDCs}
\label{sec:ftdc}

Propagation delay based \acp{TDC} are the next step after counter based \acp{CTDC}, providing higher resolution not limited by setup and hold times of flip flops but by propagation delay of simple logic gates or \acp{DLU}. While the resolution of counter based \acp{CTDC} can reach higher hundreds of picoseconds at best, propagation delay based \acp{FTDC} can offer a \ac{LSB} as small as tens of picoseconds.

The simplest propagation delay based \ac{TDC}, known as tapped delay line \ac{TDC} or flash \ac{TDC} (due to its similarity to flash \ac{ADC}), is shown on \autoref{fig:flash_tdc}.

\begin{figure}[htb]
	\centering
	\includegraphics[width=9.5cm]{obrazky/flash_tdc.pdf}
	\vspace{-0.3cm}
	\caption{Flash \acs{TDC} illustration} \label{fig:flash_tdc}\vspace{-0.3cm}
\end{figure}

The delay line, consisting of $k$ \acp{DLU}, is initialized to zero and a START step is connected to its input. The step signal forces the output of the \acp{DLU} high as it gradually propagates through the delay line. When the STOP signal activates, the latching register latches the current state of the delay line. The number of active \ac{DLU} outputs $k_\mathrm{on}$ corresponds to the time interval between the START and STOP signals $t_\mathrm{in}$ via $t_\mathrm{in} = k_\mathrm{on} \cdot t_\mathrm{d}$, i.e.  $t_\mathrm{out}$ is encoded in thermometric code, which can be decoded with a \ac{TB} converter. 

The resolution of a flash \ac{TDC} is equal to \acs{td}, and the dynamic range is given by $t_\mathrm{max} = k \cdot t_\mathrm{d}$. The number of equivalent (binary encoded) bits is $\log_2(k+1)$, i.e. to produce a 4-bit flash \ac{FTDC}, 15 \acp{DLU} are necessary.

The precision of this \ac{FTDC} is heavily dependent on \acs{td}, which is why a \ac{DLL} is commonly used to bias the \acp{DLU}, making their delays predictable and immune to \ac{PVT} variation, as shown on \autoref{fig:dll_biasing}. Nevertheless, mismatch between the individual \acp{DLU} is still present, contributing to the \ac{DNL}, respectively the \ac{INL} of the \ac{FTDC}.

Since the delay line outputs are asynchronous to the STOP signal, it is possible for the delay line transitions to not meet the setup and hold time conditions of the flip flops inside the latching register and cause a metastability at their output, which, once resolved, could settle into an incorrect state, producing a $\pm 1$ \ac{LSB} error. This would look like noise between consecutive measurements, whose noise power is related to the size of the setup and hold time interval. This is because the longer the setup and hold time, the higher the probability of the STOP signal violating them. It is therefore important to minimize the setup and hold time of the latching register, so that the noise contribution of metastability is comparable or smaller than the \enquote{naturally} present quantization noise.

A possible method of implementing the sliding scale technique (described in \autoref{subsec:sliding}) is shown on \autoref{fig:sliding_flash_tdc}.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14.5cm]{obrazky/sliding_flash_tdc.pdf}
	\vspace{-0.2cm}
	\caption{Sliding scale flash \acs{TDC} illustration} \label{fig:sliding_flash_tdc}\vspace{-0.3cm}
\end{figure}

Instead of the START pulse being the signal which propagates through the delay line, a reference clock asynchronous to the START and STOP pulses is chosen instead. Both START and STOP pulses latch the state of the delay line at the moment of their assertion. The time interval between the pulses $t_\mathrm{int}$ is then calculated as $t_\mathrm{int} = t_\mathrm{d}\cdot(N_\mathrm{STOP}-N_\mathrm{START})$. This way, even if $t_\mathrm{int}$ is the same in each consecutive conversion, the sampled state of the delay line is different each time due to the asynchronism between the control pulses and the reference clock. The mismatch between the \acp{DLU} is converted into noise between conversions, which can be averaged.

An implementation of flash \ac{TDC} integrating both \ac{CTDC} and \ac{FTDC} blocks is shown on \autoref{fig:ring_flash_tdc}.  

\begin{figure}[htb]
	\centering
	\includegraphics[width=14.5cm]{obrazky/ring_flash_tdc.pdf}
	\vspace{-0.3cm}
	\caption{Gated ring oscillator based flash \acs{FTDC} with a counter based \acs{CTDC}} \label{fig:ring_flash_tdc}\vspace{-0.3cm}
\end{figure}

The delay line has been transformed to a gated ring oscillator. When EN goes high, the ring oscillator starts oscillating and the coarse counter starts counting, clocked by one of the ring oscillator output phases. As soon as EN goes low, the ring oscillator stops oscillating, the coarse counter is disabled and the latching register latches the current state of all the ring oscillator phases. The state of the ring oscillator can be decoded with a phase decoder to provide fine temporal resolution. 

The problem with using a single ended ring oscillator as a \ac{FTDC} is that the number of unique states it can exist in during the oscillation period is $2k$, where $k$ is the number of stages, which is an odd integer. Therefore, it is impossible to achieve a number of states equal to a power of two, which would be ideal for utilizing the whole binary bus. This issue can be solved with a differential ring oscillator, which can have an even amount of stages. 

\section{Sub-gate delay based TDCs}

If the resolution provided by propagation delay based \acp{TDC} is not enough, so-called sub-gate delay based \acp{TDC}, also known as \acp{SFTDC}, can be employed. \acp{SFTDC} provide temporal resolution better than low tens of picoseconds, and \SI{1.2}{\pico\second} resolution was achieved by \cite{succesive_tdc}. There are multiple ways to implement a \ac{SFTDC}, all of them however rely on the difference between \ac{DLU} propagation delays.

A very popular \ac{SFTDC} architecture is called the Vernier line, which is depicted on \autoref{fig:vernier_line}. 

\begin{figure}[htb]
	\centering
	\includegraphics[width=14.5cm]{obrazky/vernier_line.pdf}
	\vspace{-0.3cm}
	\caption{Simplified Vernier line \acs{SFTDC} schematic} \label{fig:vernier_line}\vspace{-0.3cm}
\end{figure}

In the Vernier line topology, two delay lines made from identical \acp{DLU} are constructed. Each delay line is however biased by a different control signal, i.e. their delays differ so that $t_\mathrm{d1} > t_\mathrm{d2}$. To achieve stability over \ac{PVT} variation, the control signals are generated with \acp{DLL} (see \autoref{fig:dll_biasing}).
 
A START pulse propagates through the delay line with the longer delay $t_\mathrm{d1}$. Later, a STOP pulse is sent through the faster delay line. Because of the difference between the two delays, the STOP pulse catches up to the START pulse eventually. The flip flops in-between the delay lines serve as arbiters -- when the STOP pulse finally overtakes the START signal, the flip flop outputs of the following stages stay low. The bits $a_\mathrm{0}$ to $a_\mathrm{k-1}$ are encoded in thermometric code, where the \ac{LSB} corresponds to the temporal resolution of $t_\mathrm{dif} = t_\mathrm{d1} - t_\mathrm{d2}$. A \SI{30}{\pico\second} resolution was achieved with a Vernier line based \ac{TDC} by \cite{vernier_line}.

The dynamic range of the Vernier line \ac{SFTDC} depends on the number of stages $k$ via $t_\mathrm{max} = k\cdot t_\mathrm{dif}$, and the number of equivalent binary bits is $\log_2 (k+1)$. However, the number of \acp{DLU} used is $2k$. This is a shortcoming of the architecture: to achieve dynamic range of four bits or more, the amount of \acp{DLU} required is rather large, contributing to large area occupation and power consumption. 

A second issue of the Vernier line \ac{SFTDC} is mismatch. Because the difference of propagation delays is so small, any mismatch between the delay cells contributes strongly to overall non-linearity. It also limits the minimum practical size of the \ac{LSB} -- the difference between $t_\mathrm{d1}$ and $t_\mathrm{d2}$ should be large enough to guarantee that the relationship $t_\mathrm{d1} > t_\mathrm{d2}$ always holds even under statistical variation between all \ac{DLU} pairs.

A modified topology solving both of these issues is called the cyclic Vernier line, depicted on \autoref{fig:cyclic_vernier} and presented in  \cite{lin_vcdlu}, \cite{cyclic_vernier1} or \cite{cyclic_vernier3}.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{obrazky/cyclic_vernier.pdf}
	\vspace{-0.3cm}
	\caption{Simplified cyclic Vernier line \acs{SFTDC} schematic} \label{fig:cyclic_vernier}\vspace{-0.3cm}
\end{figure}

Instead of using two lines of \acp{DLU}, the cyclic Vernier line folds the delay lines into single stage delay loops, i.e. ring oscillators. When START goes high, the coarse phase of the measurement cycle begins. The slower ring oscillator starts oscillating, incrementing the coarse counter $N_\mathrm{S}$. As soon as STOP goes high, the fine measurement phase starts. The coarse counter is frozen, the slightly faster oscillator ($t_\mathrm{d1} > t_\mathrm{d2}$) starts oscillating and the fine counter $N_\mathrm{F}$ increments. A phase detector made up of the two flip flops and an AND gate activates as soon as the faster oscillator overtakes the slower oscillator -- at that point the fine counter stops counting as well and the conversion is complete.

The final conversion result is

\begin{equation}
t_\mathrm{out} = N_\mathrm{S}\cdot T_\mathrm{S} + N_\mathrm{F}\cdot (T_\mathrm{S} - T_\mathrm{F})
\end{equation}

where $T_\mathrm{S}$ is the period of the slower ring oscillator and $T_\mathrm{F}$ the period of the faster one \cite[p.1512]{cyclic_vernier3}.

The advantage of the cyclic Vernier line \ac{SFTDC} is that there is only one pair of \acp{DLU} which has to match. Any mismatch between the two does not translate to non-linearity, but a gain error instead, which can be calibrated \cite[p.563]{lin_vcdlu}. Increasing the dynamic range of the coarse and sub-fine measurements is simply done by extending the counters.

A drawback of this \ac{TDC} is that the fine measurement has a long conversion time. To resolve a time difference of $t_\mathrm{d1} - t_\mathrm{d2}$, one full period of the fast oscillator $T_\mathrm{F}$ needs to elapse. Moreover, the shorter the temporal resolution, the longer the conversion time of the fine measurement phase, as described by the following equation \cite[p.44]{cyclic_vernier2}:

\begin{equation}
t_\mathrm{conv, fine} = (t_\mathrm{STOP}-t_\mathrm{START}-t_\mathrm{coarse})\cdot\frac{T_\mathrm{S}}{t_\mathrm{d1} - t_\mathrm{d2}}
\end{equation}

where $t_\mathrm{coarse}$ is equivalent to $N_\mathrm{S}\cdot T_\mathrm{S}$. The longer the residual time between $t_\mathrm{coarse}$ and the START-STOP time interval, the longer the fine measurement phase takes, i.e. the conversion time is dependent on the input signal level. 

An implementation of a cyclic Vernier line \ac{TDC} in \SI{65}{\nano\meter} CMOS is presented in \cite{cyclic_vernier1}, where a resolution of \SI{5.5}{\pico\second} was achieved on die area as small as \SI{0.006}{\milli\meter\squared}. However, a lengthy (and therefore costly) calibration scheme had to be utilized.

There are other \ac{SFTDC} topologies, most of which share either the drawbacks of the classic Vernier line (large area) or the cyclic Vernier line (long conversion time). These are the cyclic pulse shrinking \ac{TDC} \cite{pulse_shrinking}, successive approximation \ac{TDC} \cite{succesive_tdc}, pipelined \ac{TDC} \cite{pipeline_tdc}, noise shaping \ac{TDC} \cite{noise_shaping_tdc} etc.

These drawbacks make these topologies unsuitable for \ac{DToF} \ac{LIDAR} applications requiring fast frame rates (short conversion time needed) and/or \ac{SPAD} array based flash or sequential flash \ac{LIDAR} (small area needed, as each \ac{SPAD} has its own \ac{TDC}). Picosecond level temporal resolution corresponds to millimetre or sub-millimetre distance resolution (see \autoref{fig:time_vs_dist}), which are too short distances to be of interest in automotive \ac{LIDAR}, and therefore for most applications, \acp{FTDC} are good enough.

\section{Clock distribution schemes}

It was already explained why \ac{DToF} \ac{LIDAR} systems contain multiple \acp{TDC} (hundreds or even low thousands), and why the \acp{TDC} consist of a \ac{CTDC} and a \ac{FTDC} (since \ac{SFTDC} disadvantages outweigh the advantages for large pixel arrays and/or fast frame rates). 

In \autoref{sec:ftdc}, two possible implementations of \acp{FTDC} were illustrated, both requiring $N$ accurately phase shifted clock phases, where $N = 2^{B}$, $B$ being the number of bits of the \ac{FTDC}.

The clock phases needed for both the \ac{CTDC} and \ac{FTDC} have to be generated somewhere, and subsequently routed to the \acp{TDC}. Because of the size of the \ac{TDC} array, the architecture of the clock distribution has big impact on the performance of the system, from power consumption to precision or uniformity. 

\subsection{Global counting}

The first type of clocking scheme is to create the clock phases in one place of the chip and distribute them to all the blocks which require them. These schemes are called global counting. Their main advantage is the fact, that the clock signals received by one \ac{TDC} should be in phase with the ones received by the others, as long as the routing is symmetrical.

The first, simplest example of a global counting scheme is shown on \autoref{fig:global_clock_single}, where all the clock phases are generated with a single \ac{DLL} and distributed via a single large clock buffer.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{obrazky/global_clock_single_stage.pdf}
	\vspace{-0.3cm}
	\caption{Global clock counting with single buffer} \label{fig:global_clock_single}\vspace{-0.3cm}
\end{figure}

The problem with this scheme are the parasitic capacitances and resistances. Firstly, assuming the \ac{TDC} array is large, the length of the metal interconnects can be substantial. Long metal interconnects lead to large parasitics, which in turn lead to large dynamic power consumption via the well known $CV^2f$ dependency. Since each interconnect is present $N$ times, this can be a substantial amount of power.

Secondly, the large parasitics act as a distributed RC low-pass filter, slowing down the edges of the clock phases. This, along with interference and crosstalk picked up by the long interconnects, increases the jitter and therefore decreases the precision of the system.

The signal integrity issue can be solved with the multiple stage clock tree approach, as shown on \autoref{fig:global_clock_multi}.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{obrazky/global_clock_multi_stage.pdf}
	\vspace{-0.3cm}
	\caption{Global clock counting with multiple stage clock tree} \label{fig:global_clock_multi}\vspace{-0.3cm}
\end{figure}

Instead of using a single clock buffer with high driving capability, a number of clock buffers is used, splitting the distribution path into segments. Each buffer restores the edge of the clock signal and decreases the loading of the previous buffer. The \autoref{fig:global_clock_multi} is just an illustration -- the clock tree can be made from a higher number of stages, the last stage driving more than just two \ac{TDC} etc. In practice, \acp{TDC} are often laid out in groups of four or eight.

On the other hand, this improvement is balanced by an additional increase of power consumption, since the number of clock buffers has increased significantly.

\subsection{Local counting}
\label{subsec:local_counting}

Opposite to global counting stands the local counting method. Instead of generating the clock phases only once and routing them all over the chip, with local counting, the clock phases are generated in multiple blocks located at various places of the chip, each block distributing the phases to the nearest \acp{TDC}.

There are multiple possible ways of implementing local counting, one of them is shown on \autoref{fig:local_clock_dlls}.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{obrazky/local_clock_dlls.pdf}
	\vspace{-0.3cm}
	\caption{Local clock counting with \acsp{DLL}} \label{fig:local_clock_dlls}\vspace{-0.3cm}
\end{figure}

This solution is only partly \enquote{local}, as each \ac{DLL} which is generating all the required clock phases has to be driven by the global clock. Therefore the same problems as with global counting appear -- the global clock needs to be distributed to the \acp{DLL} somehow. Since only one clock phase is routed this way, the parasitics are less of an issue than with global counting (especially for high $N$), but nevertheless, their contribution to the power consumption is not negligible. Furthermore, \acp{DLL} are not small blocks and take considerable amount of footprint, which is not ideal if there are a large number of them on the chip.

It has to be noted again that in practice, the size of the \ac{TDC} group sharing clock sources is usually four or eight, although the pictures show only two member \ac{TDC} groups for simplicity.

A truly local counting technique is shown on \autoref{fig:local_clock_ring_osc}.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{obrazky/local_clock_ring_oscillators.pdf}
	\vspace{-0.3cm}
	\caption{Local clock counting with ring oscillators} \label{fig:local_clock_ring_osc}\vspace{-0.3cm}
\end{figure}

In this scheme, the clock phases are generated in ring oscillators. A single, global \ac{DLL} is used to bias the \acp{CCDLU} in the ring oscillators, guaranteeing \ac{PVT} immune oscillation frequency. In order for this \ac{PVT} stabilization to work, the \ac{DLL} needs to be made from the same \acp{CCDLU} as the ring oscillators. The control signal routed to the \acsp{RO} is current, because it is more immune to IR drops, noise or crosstalk. The current is essentially DC, therefore no dynamic power losses are generated.

Both of the local counting methods consume less power than the global counting schemes, as the interconnect parasitics issues are diminished, which is especially the case for the \acs{RO} based local counting scheme. However, the local counting schemes also share the same problem with mismatch and phase asynchronism. While the \ac{PVT} stabilization can compensate for global (shared) variations in process, voltage or temperature, mismatch between the \acp{DLL} or \acsp{RO} can cause mismatch of the clock phases between the blocks, or even worse, as is the case with the \acs{RO} based scheme, the oscillation frequency can vary between the \acsp{RO} as well. The mismatch of the oscillation frequency can cause systematic error in the \ac{ToF} measurements with the affected \acp{TDC}, and the phase shift between the clock signals can cause fixed pattern noise in the final depth map.

\subsection{Summary}

In this section, examples of both global and local counting schemes were presented.

The main advantage of the global counting clock distribution schemes is their simplicity and the synchronism, as all the \acp{TDC} should receive the same clock signals at any given instant, as long as the routing is symmetric. The main drawback, on the other hand, is the power consumption, as the clock distribution interconnect networks can posses large parasitic capacitance and resistance. Symmetric routing also takes a lot of area.

The local counting schemes, on the other hand, improve the power consumption at the cost of higher mismatch sensitivity and loss of synchronised clock phase inputs across the \ac{TDC} array.

The ideal solution would be to implement the local counting scheme as shown on \autoref{fig:local_clock_ring_osc}, as it offers the best power efficiency, and add some power efficient mechanism capable of perfectly synchronising the oscillators. This can be achieved with the so-called injection locking technique, which will be described in the subsequent \autoref{chapter:ilo_theory}.