\chapter{Injection Locked Ring Oscillator Design}
\label{chapter:design}

In this chapter, the design of an \ac{ILRO} based \ac{FTDC} for application in \ac{LIDAR} systems will be presented. 

The aim of this thesis is to design and simulate an \ac{ILRO} meant to be used in a \ac{DToF} \ac{LIDAR} \ac{FTDC} along with its biasing circuits, which consist of a \ac{DLL}. The assignment of this thesis does not contain the design of the \ac{CTDC}, the \ac{PLL} which drives the clock tree nor the latches and digital logic used for decoding the \ac{ILRO} clock phases into a time stamp. These blocks will be however commented and key requirements for these blocks will be mentioned, as they operate in close conjunction with the circuits designed in this thesis.

Firstly, the manufacturing technology ONK65 will be briefly introduced. A few sections providing system level overview of the circuits to be designed as well as the way they could fit into an overarching architecture will follow and some high-level design decisions will be explained. The subsequent sections will delve deeper into device level circuitry of the \ac{ILRO} itself and its operation with the \ac{DLL}. Finally, the designed circuits will be simulated in conjunction to verify their performance.

\section{Technology overview}

The manufacturing technology ONK65, developed by Global Foundries, is a standard p-substrate based \SI{65}{\nano\meter} \ac{CMOS} process. The name of the technology library used in this project is \textit{CMOS10LPe}, which is a library focused on low power digital applications. The library contains somewhat limited options for analog designers especially as far as bipolar devices are considered, which is the standard for common digital oriented process nodes. Further options for high performance analog circuitry such as high-gain asymmetric \ac{MOS} devices, inductors etc.\ are included in the \ac{RF} design kit, which however requires additional masks and which will not be utilized in this thesis.

The name ONK65 does not actually come from the smallest gate length of the \SI{1.2}{\volt} \ac{MOS} devices (also known as thin oxide devices), as the minimum length is actually \SI{60}{\nano\meter}. There are also thick oxide devices available, which operate with \SI{1.8}{\volt}, \SI{2.5}{\volt} or \SI{3.3}{\volt} supplies and their minimum gate length is \SI{260}{\nano\meter}, \SI{280}{\nano\meter} or \SI{400}{\nano\meter} respectively.

The process offers three different \ac{Vth} options for thin oxide transistors (low, standard and high) and a native \ac{Vth} option for thick oxide devices. These variants can be useful for certain analog circuits where the voltage headroom is restricting.

There are four resistor types available. The N-well resistor \textit{nwres} does not require any additional lithographic masks, while the N+ diffusion resistor \textit{opndres}, P+ polysilicon resistor \textit{opppcres} and the high yield P+ polysilicon resistor \textit{oprppres} do. The two polysilicon resistors are of particular interest for analog designers due to their low \ac{TCR} and high sheet resistance. The high yield version offers smaller process variation than its counterpart at the cost of yet another mask and will not be used. The process offers a variety of metal interconnect based capacitors as well, but since this application does not require extremely linear and stable capacitors, standard MOScaps will be used instead.

This process features from 4 to 9  metal interconnect layers, filled with low-$k$ dielectric. All wiring levels are copper except for the final one, which is aluminium. The operating temperature range for devices made in this process is the standard automotive range of \SI{-40}{\degreeCelsius} to \SI{125}{\degreeCelsius}.

The \ac{PDK} is well equipped for analog simulation purposes with statistical variation support for Monte Carlo runs as well as a variety of pre-defined fixed process corners for faster simulations at the extremes of the variation space. The mixed \acs{MOS} corners FS and SF (corresponding to fast NMOS \& slow PMOS or vice-versa respectively) correspond to $3\upsigma$ variation, and the FFF and SSF corners (the last F stands for \textit{functional}) are available in $3\upsigma$, $4\upsigma$, $5\upsigma$ and $6\upsigma$ varieties. Resistor and capacitor process corners are only available in $3\upsigma$ varieties.

\section{Choice of \acs{ILRO} operating frequency}

The thesis assignment provides a single specification, the resolution of the \ac{TDC}, which is \SI{50}{\pico\second} (and which corresponds to \SI{7.5}{\milli\meter} via \autoref{eq:ToF_to_distance}). This is a demanding specification to reliably meet especially over \ac{PVT} variation, but should be ultimately achievable, possibly with some trimming.

The resolution specification directly translates to the ideal value of the propagation delay of a single \ac{ILRO} delay cell. Therefore, assuming the \ac{ILRO} will be implemented in a similar way to the example shown on \autoref{fig:ilro_flash}, by selecting the number of \ac{ILRO} stages, the frequency of the \ac{ILRO} can be defined. This in turn defines the frequency of the \ac{CTDC}, as the \ac{LSB} of the \ac{CTDC} is supposed to be \enquote{sliced} by the \ac{ILRO} clock phases and therefore the frequency of the \ac{ILRO} should match the clock frequency incrementing the counter. 

In practice, a double-counting \ac{CTDC} can be used for various reasons, one of which is the benefit of running at half the frequency of the \ac{ILRO} (this will be further explained in \autoref{sec:tdc_arch}), but either way, there is a direct relationship between the frequency of the \ac{CTDC} and the \ac{ILRO}.

Since the delay of a single \ac{ILRO} cell specified, the larger the amount of its stages, the lower the operating frequency of the \ac{ILRO} and the \ac{CTDC} and vice-versa. This can be formulated with the following equation 

\begin{equation}
f = \frac{1}{2Nt_\s{d}}
\label{eq:ro_freq_design}
\end{equation}

where $f$ is the frequency of the ring oscillator, $t_\s{d}$ is the propagation delay of a single oscillator stage and $N$ is the number of stages of the ring oscillator. This equation holds true for both single-ended and differential ring oscillator implementations, and was actually analytically derived back in \autoref{subsec:ilro_time_analysis}.

In order not to waste space, it is desirable to encode the resulting \ac{FTDC} time stamp in binary code without unused states. Therefore, $N$ should be a power of two, which is only possible for differential ring oscillators. 

The choice of $N$ is a very important one, as it bears implications not only for the \ac{ILRO} itself, but also for the preceding analog circuits and the \ac{CTDC} counter. A list of pros and cons of choosing a longer delay line for the ring oscillator (as opposed to a shorter one) is shown in \autoref{tab:ro_stage_number_pros_cons}.

\begin{table}[htb]
\vspace{-0.3cm}
\centering
\caption{Benefits and detriments of higher number of \acs{ILRO} stages}
\label{tab:ro_stage_number_pros_cons}
\vspace{-0.3cm}
\begin{tabular}{ll}  
\toprule
lower frequency 			&    more delay line units			\\
\midrule
{\color{ForestGreen} \ding{51}} relaxed \ac{CTDC} counter specs & {\color{Red} \ding{55}} larger area usage	\\
{\color{ForestGreen} \ding{51}} lower dynamic power losses & {\color{Red} \ding{55}} higher static power consumption	\\
{\color{ForestGreen} \ding{51}} simpler \ac{PLL} design & {\color{Red} \ding{55}} worse \ac{DNL} due to mismatch and gradients		\\
\bottomrule
\end{tabular}
\vspace{-0.15cm}
\end{table}%

Perhaps the most critical is the \ac{CTDC} consideration. Choosing a ring oscillator length which is too short might result in a frequency which the \ac{CTDC} is not able to reliably operate at (due to setup and hold time constraints). This is essentially a technology limitation, defining the shortest feasible ring oscillator length.

The second most important factor is the power consumption. While the longer delay lines consume more static power simply due to the larger amount of delay cells present (which all need to be biased with biasing currents etc.), it is reasonable to expect that the dynamic power losses will be dominant due to the large amount of \acp{ILRO} and their clock phases routed throughout the chip. Therefore, doubling the length of the delay line and halving the dynamic power consumption (via $P_\s{dyn}\propto CV^2f$) for an increase in area could be a reasonable trade-off.

The number of units should not get too large, however. The more the units, the more space they occupy, which means that not only more die area is used, but also that the processing gradients are going to have a larger effect on the units and an increase in mismatch and therefore \ac{DNL} is to be expected.

In this thesis, a decision has been made to design a 16-stage \ac{ILRO}, which would oscillate at \SI{625}{\mega\hertz} (as per \autoref{eq:ro_freq_design}). As mentioned previously, a double-counting \ac{CTDC} (discussed more in the following section) can run at half the rate, which is \SI{312.5}{\mega\hertz} in this case. This is a frequency the \ac{CTDC} in this \SI{65}{\nano\meter} technology can reliably run at, but high enough to not require unreasonably large number of delay cells, which would cost not only more area, but also hurt the linearity of the \ac{TDC}.

\section{\acs{TDC} architecture overview}
\label{sec:tdc_arch}

Although this thesis focuses on the design of the \ac{ILRO} and its biasing \ac{DLL}, it is important to keep the overarching architecture of the whole \ac{TDC} signal chain in mind. An example of such an architecture is shown on \autoref{fig:tdc_overview}.\footnote{This is a simplified diagram. For the sake of clarity, blocks such as clock buffers or synchronisers and such have been omitted.} Since there is no architecture definition in the thesis assignment, this is the architecture which the circuits will be designed for.

Since the diagram is quite complex, its description will be divided into several smaller sub-sections for clarity.

\afterpage{\begin{landscape}
\begin{figure}[p]
\begin{center}
\captionsetup{type=figure} 
    \includegraphics[width=23.65cm]{obrazky/tdc_overview_block_digi.pdf}
    \captionof{figure}{Overview of an \acs{ILRO}-based \acs{TDC} architecture}
    \label{fig:tdc_overview}
\end{center}
\end{figure}
\end{landscape}}

\subsection{\acs{SPAD} and \acs{TDC} array architecture}
\label{subsec:spad_tdc_array_design}

As discussed in \autoref{chapter:lidar_theory}, \ac{LIDAR} photodetectors commonly contain hundreds of pixels and therefore a large number of \acp{TDC} is needed. The architecture therefore needs to be designed in a scalable way.

The number of \acp{TDC} is given by the number of pixels active at any given time. This depends on the \ac{LIDAR} architecture as a whole, as discussed in \autoref{sec:lidar_overview}. If the whole pixel array is illuminated simultaneously (i.e. flash \ac{LIDAR}), the number of \acp{TDC} matches the number of pixels and the whole \ac{TDC} array has to be active at the same time, which means that only relatively small spatial resolution is feasible, as running a large \ac{TDC} array consumes high peak power and cooling becomes a serious issue. If only a part of the pixel array is illuminated at a time (i.e. sequential flash or scanning \ac{LIDAR}), the number of active \acp{TDC} can be much lower. 

Let us suppose sequential flash architecture is used and both the \ac{VCSEL} and \ac{SPAD} arrays have a resolution of $320{\times}240$ pixels, which is known as \ac{QVGA}. Let us also suppose that there are always four tiles of the \ac{VCSEL} array active at a time, each $10{\times}4$ pixels large. In other words, the \ac{VCSEL} array scans the \ac{FoV} with four laser beams concurrently. Column by column, row by row, these $10{\times}4$ tile scan their sections of the array, their respective sections being called \enquote{clusters}. Since $320\div 4 = 80$, each cluster is 80 pixels wide and 240 pixels tall. The scheme is shown on \autoref{fig:hqvga}.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{obrazky/hqvga.pdf}
	\vspace{-0.1cm}
	\caption{\acs{SPAD} \& \acs{TDC} array scanning and converting scheme} \label{fig:hqvga}\vspace{-0.4cm}
\end{figure} 

Upon reflection and arrival of the emitted photons, the photons should hit the corresponding area of the \ac{SPAD} array (due to identical optical lensing systems, as previously described in \autoref{sec:lidar_overview}). Therefore, in each cluster of the \ac{SPAD} array, only 40 \acp{SPAD} are receiving valid signal at any given time, and therefore each cluster requires only 40 active \acp{TDC}.

Routing the \acp{SPAD} to the \ac{TDC} is a complex floorplanning problem. A reasonable approach is to implement an addressing scheme similar to memories, where each \ac{SPAD} is addressable via column and row selecting buses. The detection signal from the \acp{SPAD} needs to be sent to the \acp{TDC} in such a way to ensure that the propagation delay from each \ac{SPAD} to each \ac{TDC} is the same. Otherwise, a fixed pattern noise would appear, as some \acp{SPAD} would always appear to trigger earlier/later than others, even if they absorbed photons concurrently. The routing and the logic along the way needs to be therefore perfectly symmetric.

Assuming the \ac{SPAD} array is on a separate chip along with some basic readout digital circuitry, connected to the signal processing chip via 3D connections (stacked dies connected by through-silicon-vias or micro-bumps are the state of the art in \ac{SPAD} imaging and signal processing systems \cite[p.5]{chao_thesis}), the only way to achieve balanced routing known to the author is by implementing multiple \ac{TDC} banks per cluster, each consisting of 40 \acp{TDC}, as routing all \acp{SPAD} to one bank of \acp{TDC} would lead to serious issues with balancing the routing between various sections of the \ac{SPAD} cluster. This is because \acp{SPAD} can be as wide as low tenths of micrometres and a 320 pixel wide array can be several millimetres wide. Techniques such as snaking to artificially lengthen the shorter paths would need to be employed, consuming area and most importantly increasing the potential for coupling of disturbances to the sensitive \ac{SPAD} detection signal paths, which is something which needs to be avoided at all costs.

This means that each cluster requires not 40, but $8\times$ as many \acp{TDC} in total, one 40 \ac{TDC} bank for each horizontal scanning step, as shown on \autoref{fig:hqvga}. Although this sounds like a high cost to preserve the propagation delay balance, the \acp{TDC} can be made rather small (they consist of only digital circuits, as will be discussed in the following sections) and only one bank per cluster is used at any given time, which means the others could be in power down mode to save power.

With regards to quantities like the refresh rate or the number of collected samples at each step of the scan, the following estimates can be calculated for the array shown on \autoref{fig:hqvga}. For example, let us assume that the target refresh rate is \SI{10}{\hertz}, which is reasonable for automotive applications. This means that the laser beams should be able to fully scan the pixel array in \SI{0.1}{\second}, and since there are $8\times 60=480$ scanning steps, each step can last up to \SI{208}{\micro\second}. The length of an individual \ac{TDC} conversion is defined by its maximum range -- let us assume that it is roughly \SI{1}{\micro\second}, which corresponds to about \SI{150}{\meter} maximum measurable distance (see \autoref{fig:time_vs_dist}). In that case, approximately 200 laser pulses can be fired at each step of the scanning mechanism in order to build a statistically significant \ac{TCSPC} histogram for each pixel of the array. If a larger histogram was desired, the refresh rate or the maximum measurable distance would have to be lowered.

\subsection{\acs{TDC} conversion timing scheme}
\label{subsec:tdc_scheme_design}

The architecture presented on \autoref{fig:tdc_overview} features standard START-STOP timing scheme, where the START signal will globally start the \ac{TDC} conversion and individual STOP signals coming from the pixel array will stop their corresponding \ac{TDC}, producing a timestamp. The reasons why the reversed timing scheme discussed in \autoref{subsec:reverse_timing} cannot be used are several. First of all, assuming each \ac{TDC} has its own \ac{ILRO}, enabling and locking each \ac{ILRO} only after the corresponding START signal has triggered is problematic, as it takes some time for the \ac{ILRO} to lock and taking a measurement of the \ac{ILRO} clock phases before it locks onto the injected frequency would corrupt the measurement. Additionally, implementing one \ac{ILRO} for each \ac{TDC} is very area and power intensive. Instead, each \ac{ILRO} will be used for several \acp{TDC} (as discussed in \autoref{subsec:ilro_tdc_theory}) and therefore needs to be running at all times. To save power, only the \acp{ILRO} driving the currently used \ac{TDC} bank can be enabled, as well as the ones which are going to drive the \ac{TDC} bank which will be used in the next horizontal scanning step (see \autoref{fig:hqvga}), since these \acp{ILRO} need to power up, settle and lock to target frequency in advance before their clock phases are used in the next step of the cycle.

While the reversed timing scheme from \autoref{subsec:reverse_timing} will not be considered in the proposed architecture, a certain modification of the sliding scale technique from \autoref{subsec:sliding} will be. The reasoning is as follows. If a standard global START signal was used to fire a laser pulse and to start the \ac{TDC} conversions at the same time, there would be a certain partly systematic, partly random error to the conversion. This is because there will always be a delay between the START signal triggering and the ideal \ac{TS0}. The ideal \ac{TS0} corresponds to the time instant the reflected laser pulse would be detected by the photodetector in case it was immediately reflected upon leaving the laser, i.e. when the distance from the \ac{LIDAR} device to the obstacle would be effectively zero. The delay between the two is caused by the propagation delay of the START signal on its way to the \acp{TDC} and the laser driver, the inherent delay of the laser driver, the laser itself, the delay between the absorption of the photon in the \ac{SPAD} and the activation of \ac{SPAD} detection signal and the propagation delay of the detection signal on its way to the \ac{TDC}. If the ideal value of \ac{TS0} was successfully acquired, it could be subtracted from all consequent \aclp{TS} produced by \acp{TDC} during normal operation to get a corrected timestamp, i.e. $\mathit{TS}_\s{final}=\mathit{TSN}-\mathit{TS0}$, where $\mathit{TSN}$ are the \aclp{TS} produced by the \acp{TDC} during normal operation. This implements a sliding scale, as the reading is contained within the difference of two independent time stamps.

A novel way to acquire \ac{TS0} has been discovered during the work on this thesis. A patent application has been made and as such the invention cannot be publicly described until the application is processed. In \autoref{fig:tdc_overview}, the block is named \enquote{laser sync} and its implementation will not be presented. For the purposes of this thesis, which focuses on a different part of the \ac{TDC} architecture anyway, it will be assumed that the START signal produced by this block is precisely the START signal needed to generate \ac{TS0}, which can be then used to correct future \aclp{TS} in the current measurement cycle as defined above. More details on the operation of the \acp{TDC} themselves and the timing scheme of the whole architecture will be presented in the following sections.

\subsection{Clock source, \acs{PLL} and \acs{DLL}}
\label{subsec:clock_pll_dll}

Before the description of the individual blocks in \autoref{fig:tdc_overview} can start, the choice of the voltage domain will be addressed. The choice is ultimately quite simple. Since the circuitry making up the whole \ac{TDC} signal chain needs to be as fast as possible and operates in a somewhat digital or mixed-signal regime, the \SI{1.2}{\volt} domain is clearly the best option and brings an additional benefit of lower area usage as well. The only classically analog circuit in the diagram is hidden inside the \ac{DLL} block, and as will be shown in \autoref{sec:dll_design}, its design is feasible in \SI{1.2}{\volt} domain as well.

The description will start from the beginning of the signal chain, which is the external clock source. This would be a crystal oscillator, which can provide a stable and spectrally clean clock signal, although at a relatively low frequency (higher tens or lower hundreds of \SI{}{\mega\hertz}). This is why the first important block in the clock distribution scheme on-chip is a \ac{PLL}. This \ac{PLL} multiplies the frequency coming from the crystal oscillator to the double of the desired \ac{ILRO} injection frequency (in this case \SI{1.25}{\giga\hertz}), so that it can be halved again, producing a symmetric, close to 50\% duty cycle clock.

This \SI{625}{\mega\hertz} clock is the signal used to lock the \acp{ILRO} and naturally also the \ac{DLL}. It is also used for the double-counting \ac{CTDC}, but only after its frequency is halved again to \SI{312.5}{\mega\hertz}. The coarse counters will be discussed later in \autoref{subsec:coarse_counters}.

The role of the \ac{DLL} is to produce a \ac{PVT} compensated biasing current $I_\s{BIAS}$ necessary to set the total delay of a 16-stage delay line to \SI{0.8}{\nano\second}, which is the period corresponding to the chosen frequency of \SI{625}{\mega\hertz} (not \SI{1.6}{\nano\second}, because there is a factor of 2 in \autoref{eq:ro_freq_design}). In other words, the \ac{DLL} produces a biasing current setting the propagation delay of each \ac{CCDLU} to \SI{50}{\pico\second}, which is the specified resolution. 

The design of the \ac{DLL} will be presented in \autoref{sec:dll_design}, but the general principle of the \ac{PVT} compensated biasing has been already explained in \autoref{sec:dll} in \autoref{chapter:tdcs}. It relies on the fact that the \ac{DLL} delay line is essentially the same circuit made from the same number of identical \acp{CCDLU} as the \ac{ILRO}. Therefore, the biasing current generated by the \ac{DLL} to lock itself to \SI{625}{\mega\hertz} is ideally the same as the current the \ac{ILRO} needs to set its \ac{f0} to \SI{625}{\mega\hertz} as well. 

In practice, this is obviously not the case. The primary reason is that the way the \ac{CCDLU} is connected in \ac{DLL} and \ac{ILRO} topologies differs fundamentally, the \ac{DLL} delay line being a pass-through circuit, while in the case of \ac{ILRO}, the delay line is connected in a feedback system. This discrepancy can be decreased in magnitude by dummy cells helping to simulate the \ac{ILRO} connection in the context of the \ac{DLL}, but it is impossible to remove this discrepancy altogether. The consequence is that the free-running frequency of the \ac{ILRO} biased by the same current which satisfied the \ac{DLL} lock condition will not be precisely \SI{625}{\mega\hertz}, but can actually differ by a few percent. Furthermore, even if this particular issue was somehow perfectly solved, there are more sources of error, such as the mismatch of the delay lines between the \ac{DLL} and the \acp{ILRO} themselves, the mismatch of the biasing current mirrors distributing the current from the \ac{DLL}, various error sources in the \ac{FPD} and \ac{V-to-I} converter circuits and so on. The bottom line is that the \ac{DLL} alone cannot set \ac{f0} precisely.

Nevertheless, the \ac{DLL} is still important in the context of the system, and that is because trimming needs to be included. There are two reasons for why trimming is necessary: first of all, trimming can eliminate the problems mentioned in the paragraph above and help the \ac{DLL} supply the correct biasing current to the \acp{ILRO}. Secondly, it solves the problem with propagation delay distribution in the \ac{ILRO}, which was already foreshadowed in \autoref{subsec:ilro_time_analysis}. If the \ac{ILRO} naturally oscillated at \SI{600}{\mega\hertz} (either because of skewed biasing current or skew in the \ac{ILRO} itself), its propagation delay would amount to \SI{52.1}{\pico\second} assuming perfect matching between the stages. When injection locked to \SI{625}{\mega\hertz}, the propagation delay of the injection stage would need to adjust to \SI{18.5}{\pico\second} in order for the propagation delays to amount to half of the injection clock period. This would cause significant \ac{DNL} of the \ac{FTDC}. If the \ac{ILRO} is somehow pre-trimmed to oscillate relatively close to the target frequency (for example within $2\%$), the \ac{DNL} issue would be suppressed and as an added benefit, the \ac{ILRO} would more easily lock to the target frequency, requiring less locking range and therefore less injected energy, conserving power.

Once trimming of individual \acp{ILRO} is somehow incorporated in the system (more discussion on trimming implementation will follow in \autoref{subsec:trimming}), the \ac{DLL} can fulfil its role of \ac{PVT} immune biasing. This is because the problems causing the \ac{DLL} to bias the \acp{ILRO} with wrong current are static in nature and can be trimmed out. After trimming, the \ac{DLL} can in principle correctly dynamically vary the biasing current depending on the current supply voltage or die temperature. This way the \ac{DLL} helps to keep the \acp{ILRO} locked even in extreme conditions. Simulations proving the usefulness of the \ac{DLL} will be presented later on in \autoref{sec:top_sims}.

\subsection{\acsp{ILRO} and clock phase latches}

Each 16-stage differential \ac{ILRO} outputs 32 clock phases, Ph[15:0] and PhB[15:0], where PhB are the negations of Ph. These clock phases can exist in 32 unique states, therefore they can be decoded into a 5-bit binary \ac{FTDC} \acl{TS} by the phase decoder, which is a piece of combinational logic in each \ac{TDC}. The clock phases are shown in \autoref{tab:clock_phases}\footnote{The time step corresponds to the propagation delay of a single \ac{CCDLU}. Negated phases PhB[15:0] are not shown.}.

\afterpage{\begin{landscape}
\begin{table}[htb]
\vspace{-2cm}
\caption{Clock phases of 16-stage differential \acs{ILRO}}
\label{tab:clock_phases}
\vspace{-0.25cm}
\fontsize{10}{11}\selectfont
\centering
\begin{tabular}{@{}ccccccccccccccccc@{}}
\toprule
Time step / Code & Ph[0] & Ph[1] & Ph[2] & Ph[3] & Ph[4] & Ph[5] & Ph[6] & Ph[7] & Ph[8] & Ph[9] & Ph[10] & Ph[11] & Ph[12] & Ph[13] & Ph[14] & Ph[15] \\ \midrule
0 & {\color[HTML]{C0C0C0} 0} & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        \\
1 & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        \\
2 & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        \\
3 & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        \\
4 & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        \\
5 & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        \\
6 & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        \\
7 & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        \\
8 & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        \\
9 & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        \\
10 & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & 1                        & 1                        & 1                        & 1                        & 1                        \\
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12 & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & 1                        & 1                        & 1                        \\
13 & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & 1                        & 1                        \\
14 & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & 1                        \\
15 & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} \\ 
16  & 1                        & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} \\
17  & 1                        & 1                        & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} \\
18  & 1                        & 1                        & 1                        & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} \\
19  & 1                        & 1                        & 1                        & 1                        & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} \\
20  & 1                        & 1                        & 1                        & 1                        & 1                        & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} \\
21  & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} \\
22  & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} \\
23  & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} \\
24  & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} \\
25  & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} \\
26 & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} \\
27 & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} \\
28 & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} & {\color[HTML]{C0C0C0} 0} \\
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30 & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & {\color[HTML]{C0C0C0} 0} \\
31 & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        & 1                        \\ \bottomrule
\end{tabular}
\end{table}
\end{landscape}}

Each \ac{ILRO} can be sampled by $N$ \acp{TDC}. The precise value of $N$ is mostly dependent on the layout. The goal is to route the clock phases only over short distances to minimize power loss and signal distortion. It is also necessary to distribute the phases via balanced interconnects so that they arrive at the destination at the same time. This is easier if there are less \acp{TDC} per each \ac{ILO}. On the other hand, having one \ac{ILO} for each \ac{TDC} takes a lot of area and power. A reasonable value for $N$ seems to be 8, which will be assumed in this thesis and has been depicted in \autoref{fig:tdc_overview}, where each \ac{TDC} group (TDCG) consists of 8 \acp{TDC} connected to the same \ac{ILRO}. This also enables easy construction of the 40 \ac{TDC} banks, as each bank would contain 5 such TDC groups. As a sidenote, this means that if the \ac{VCSEL} and \ac{SPAD} pixel arrays were implemented as described in the example from \autoref{subsec:spad_tdc_array_design}, the total amount of \acp{ILRO} would be $1280\div 8 = 160$.

The \ac{ILRO} clock phases pass through a series of buffers growing in strength and are finally connected to a latch in the \ac{TDC} block. An example of what the latches can look like is shown on \autoref{fig:latch}. The differential implementation allows the latch to take advantage of the differential operation of the \ac{ILRO} to improve the signal integrity and shorten the transition times. 

\begin{figure}[htb]
	\centering
	\includegraphics[width=11cm]{obrazky/latch_diff.pdf}
	\vspace{-0.1cm}
	\caption{Differential \acs{ILRO} clock phase latch example} \label{fig:latch}\vspace{-0.4cm}
\end{figure}

Since the STOP trigger is an asynchronous signal (in relation to the \ac{ILRO} clock phases), there are two main goals for the latch design: minimize the metastable window (the sum of its setup and hold times) to reduce errors as much as possible as was already discussed in \autoref{sec:ftdc}, and in the case of setup and/or hold time violation, ensure the digital output quickly settles to a defined digital value as soon as possible and does not stay in the middle of the rails for a prolonged period of time. The circuit above can fulfil the latter requirement, and the worst case metastable window of the latch in ONK65 has been simulated to be \SI{30}{\pico\second}. This value is sadly above the theoretical quantization noise level (approximated by the well-known formula $LSB/\sqrt{12}=\SI{50}{\pico\second}/\sqrt{12}=\SI{14}{\pico\second}$), but this is ultimately limited by the technology. However, since the occurrence of metastability is essentially random, it also acts as noise, so in principle, it can be filtered out in the digital domain by histogram building (see \autoref{sec:tcspc}), as long as a sufficiently large set of samples is taken. Either way, the design of the latch is out of the scope of the thesis assignment.

\subsection{Coarse \acs{TDC} counters and digital controller}
\label{subsec:coarse_counters}

The first design choice related to the \ac{CTDC} counters is their bit width, as this will ultimately define the maximum measurable \ac{ToF} and therefore the maximum distance. In practice, the maximum distance is defined by laser power, atmospheric conditions or obstacle reflectivity, so the coarse counters should be sized to ensure its size is not the limiting factor. In the architecture shown on \autoref{fig:tdc_overview}, a 9-bit \ac{CTDC} is considered, which, assuming it runs at \SI{625}{\mega\hertz}, corresponds to maximum measurable distance of \SI{123}{\meter} (as per \autoref{eq:ToF_to_distance}). If the limitations of the optical system allowed practical measurements of longer distances, more bits could be added to the counters and the relevant digital circuits. This however takes more area and increases the requirements for the throughput of the data buses, histogram building circuits etc.

The actual implementation of the coarse counters is not the subject of this thesis, but some possibilities were presented in \autoref{sec:ctdc}. In this thesis, it is assumed the counters are synchronous.

The counters shown in \autoref{fig:tdc_overview} implement a double-counting \ac{CTDC}, as they count at a \SI{180}{\degree} phase angle in relation to each other. The leading counter CNT0 is active on the falling edge of the clock, while the trailing counter CNT1 is active on the rising edge. Therefore, CNT1 preserves the previous value of CNT0 for half a clock period after the CNT0 updates. 

The main benefit of this scheme is the prevention of missing codes caused by the phase misalignment of the \ac{CTDC} and the \ac{ILRO} clock phases. While ideally the two blocks should be running in phase thanks to the injection locking mechanism, in reality, there always is some phase shift due to varying and possibly not-equal parasitic delays along the two diverging signal paths. When the double-counting scheme is used, a copy of the \SI{312.5}{\mega\hertz} clock delayed by \SI{90}{\degree} (easily implemented with two flip-flops and the \SI{625}{\mega\hertz} clock) can be used to decide which counter's value will be used for the final timestamp. In order to prevent the missing codes, the counter which has not updated in the last half of the clock period prior to the activation of the STOP signal has to be chosen. This will be shown on the timing diagram discussed in the following \autoref{subsec:timing_diagram}.

As the design of the digital circuitry controlling the \ac{TDC} is not the focus of this thesis, this technique will not be discussed further for the sake of brevity, but more details on the technique can be found in \cite[p.69]{ilo_thesis}.

The \ac{LSB} of the \ac{CTDC} still corresponds to the \ac{ILRO} frequency of \SI{625}{\mega\hertz}, even though it runs at half the rate. The \ac{LSB} reconstruction can be done by simply latching the state of the \SI{312.5}{\mega\hertz} clock the moment the STOP signal triggers. This logic would be included in each individual \ac{TDC} block, i.e. each \ac{TDC} block has to accept the \SI{312.5}{\mega\hertz} clock as well.

As depicted in \autoref{fig:tdc_overview}, a lot of functionality is offloaded to the digital controller. This is a block containing all the relevant digital logic necessary to produce the final timestamp, and its sequential circuits are running at \SI{325}{\mega\hertz}. It includes the logic controlling the laser firing cycle and the \ac{TDC} measurement cycle, as well as latches and logic registering and processing the values of the coarse counters. This digital controller then connects to more complex \ac{DSP} circuits used for \ac{TCSPC} histogram building. Some of its operation will be described in the following section.

\subsection{Timing diagram}
\label{subsec:timing_diagram}

In this section the timing diagram shown on \autoref{fig:tdc_timing} will be described. The diagram features the vast majority of signals depicted on \autoref{fig:tdc_overview} and features a typical measurement cycle. It is heavily simplified, does not account for combinational logic delays and some signals might be optimized differently by digital engineers, as \ac{LIDAR} systems are very complex systems and their digital timing controls are no exception. The point of the diagram is simply to show how the \acl{TS} could be produced in principle, utilizing the circuits which will be designed in this thesis.

\afterpage{\begin{landscape}
\begin{figure}[p]
\begin{center}
\captionsetup{type=figure} 
    \includegraphics[height=13.3cm]{obrazky/tdc_timing.pdf}
    \captionof{figure}{Timing diagram}
    \label{fig:tdc_timing}
\end{center}
\end{figure}
\end{landscape}}

The first signal which has to activate is actually ILO ENA, which is not depicted on \autoref{fig:tdc_timing}. This signal enables the \acp{ILRO} and the injections, and because starting the oscillator and locking it can take significant amount of time (simulations of the locking transient will be presented later in \autoref{sec:ilro_design}), it needs to be done well in advance. In practice, there is no single ILO ENA bit. Instead, its a bus enabling the \acp{ILRO} which are going to be needed in the next scanning cycle by the next \ac{TDC} bank. Therefore, there are always 2 \ac{TDC} banks (and therefore 10 \acp{ILRO}) active at a time per \ac{TDC} cluster -- one of them being actively used and the other starting up in preparation for the next cycle. All the other banks can be kept in power-down.

When RST signal goes low, coarse counters CNT0 and CNT1 are released from reset and can start incrementing at the corresponding edges of the \SI{312.5}{\mega\hertz} clock. At the same time, TDC ENA (also a bus enabling whole \ac{TDC} banks at a time) goes high, enabling the sequential and combinational logic of the \acp{TDC} to operate. The digital controller managing the measurement cycle also signals the laser driver to fire a pulse, so this time instant is essentially the beginning of the conversion.

The first event of interest is the activation of the START signal. This signal has been mentioned in \autoref{subsec:tdc_scheme_design} and is produced by the \enquote{laser sync} block. Ideally, the instant the START signal activates is also the instant the earliest reflected photons could be detected by a \ac{SPAD} in the pixel array, if they were reflected immediately upon leaving the optical system of the laser. Therefore, the START signal defines a true time zero and its timestamp TS0 is produced.

All timestamps consist of two main parts: the coarse part, i.e. the state of the coarse counter at the time of the START activation CNT[8:0], and the fine part Fine[4:0]. These are simply joined to form a timestamp TS[13:0], where the fine part is less significant than the coarse part.

In order to produce the coarse part, first, it needs to be determined whether to use the value stored in CNT0 or CNT1. This can be done by latching the state of CLK312p5d90 (the \SI{90}{\degree} shifted \SI{312.5}{\mega\hertz} clock) -- if it is low at the time of START activation, CNT0 is used, otherwise CNT1 is used\footnote{This is highlighted with the blue areas on \autoref{fig:tdc_timing}, which depict which counter's state would be used if the trigger triggered at the given time.}. This is done internally in the digital controller and is not depicted on \autoref{fig:tdc_overview}. In the case shown on \autoref{fig:tdc_timing}, CLK312p5d90 is low when START triggers, therefore the current state of CNT0 (1 in decimal) is used. This way the coarse counter bits CNT[8:1] have been determined, but the \ac{LSB} still needs to be reconstructed. This is done in each \ac{TDC} individually by latching the current state of the CLK312p5 clock. In the case shown on \autoref{fig:tdc_timing}, CNT[0] for the TS0 timestamp is zero. CNT[8:0] is therefore $000000010_\s{2}$ or 2 in decimal representation.

At the same time, the state of the Ph[15:0], PhB[15:0] is latched and decoded in the phase decoder. Using \autoref{tab:clock_phases}, it can be decoded that the phases depicted on \autoref{fig:tdc_timing} correspond to code $00001_\s{2}$. Finally, by joining the coarse and fine parts, the timestamp TS0 can be constructed, amounting to $00000001000001_\s{2}$ or $65_\s{10}$.

The same process is repeated for the timestamp TSN, which is produced later when the STOP[N] signal (corresponding to the Nth pixel of the pixel array) fires, hopefully due to an incoming reflected photon. The only two differences in the timestamp production this time are that the \ac{LSB} of the coarse counter happens to be high (as the state of the CLK312p5 clock is high when STOP[N] triggers), and CNT1 is chosen (as CLK312p5d90 is high at the moment of the trigger as well). The resulting timestamp TSN[13:0] is $173_\s{10}$.

As was described in \autoref{subsec:tdc_scheme_design}, the \ac{ToF} can be calculated by subtracting TS0 from TSN. For the case shown in \autoref{fig:tdc_timing}, the \ac{ToF} code is 173 - 65 = 108, which amounts to \SI{5.4}{\nano\second} or \SI{81}{\centi\meter}.

An important point that needs to be made is that since the sliding scale technique is used (subtracting TS0 from TSN), the measurement is immune to phase misalignment between coarse counters and \ac{ILRO} clock phases. If there is any misalignment, it will be present in both timestamps and subtracted out. This of course assumes that the phase misalignment does not change over time, which should be guaranteed by design, as thanks to injection locking, the frequency of the \acp{ILRO} should be exactly two times the frequency incrementing the counters.

\section{Simulation conditions}

In the following sections, simulation data from the Spectre circuit simulator will be shown. Unless otherwise specified, the \autoref{tab:sim_conditions} lists the simulation inputs used for these simulations. As is standard, the supply voltage is varied by $\pm 10\%$ (reflecting the limited accuracy of the voltage regulator) and the temperature corners exceed the operating range of the process by additional \SI{5}{\degreeCelsius}, which provides a safety margin in case of inaccurate models at the temperature extremes.

\begin{table}[htb]
\vspace{-0.3cm}
\centering
\caption{Default simulation conditions}
\label{tab:sim_conditions}
\vspace{-0.25cm}
\begin{tabular}{ccccc}  
\toprule
Quantity 				& Min.	& Typ. 	& Max.	& Unit	\\
\midrule
$V_\s{DDA1V2}$ 	& 1.08	& 1.2 	& 1.32	& \SI{}{\volt}	\\
$V_\s{BG}$ 		& 1.225	& 1.25 	& 1.275	& \SI{}{\volt}	\\
temperature				& -45	& 27 	& 130	& \SI{}{\degreeCelsius}	\\
\midrule
\acs{MOS} corners		& \multicolumn{4}{c}{SSF3, SF, typ, FS, FFF3}	\\
resistor corners		& \multicolumn{4}{c}{hi3s, typ, lo3s}		\\
\bottomrule
\end{tabular}
\vspace{-0.15cm}
\end{table}%

Capacitor corners will not be used as all capacitors used in the following design will be made out of \ac{MOS} transistors. Metal capacitors are not needed, as no designed circuits require highly linear low variance capacitors. Instead, the occupied area is the main concern and \ac{MOS} capacitors provide higher capacitance per area due to the thin oxide thickness.

A common occurrence in testbenches is the need for a biasing current. Unless otherwise specified, the circuit shown on \autoref{fig:vbg_cs} is used for creating a realistic biasing current source. 

\begin{figure}[htb]
	\centering
	\includegraphics[width=11cm]{obrazky/vbg_current_circuit.pdf}
	\vspace{-0.1cm}
	\caption{Realistic biasing current generator} \label{fig:vbg_cs}\vspace{-0.4cm}
\end{figure}

The circuit consists of a \ac{DC} voltage source providing $V_\s{BG}$ voltage (nominally \SI{1.25}{\volt}), which is applied to a P+ polysilicon resistor. This resistor's resistance is set in such a way to ensure the nominal current is precisely the current desired, i.e. $R=\SI{1.25}{\volt}/I$. In \ac{PVT} corner simulations, the value of $V_\s{BG}$ is varied by $\pm 2\%$, and $3\upsigma$ corners are used for the processing spread of the resistor, as listed in \autoref{tab:sim_conditions}. This circuit therefore essentially simulates a realistic biasing current generator made from a bandgap voltage reference of limited precision and a polysilicon resistor. The current flowing through the resistor is sensed and copied by \acp{CCCS}, which finally feed this biasing current into the current mirror input diodes of the designed circuits.

\section{Injection locked ring oscillator design}
\label{sec:ilro_design}

In this section, the \ac{ILRO} circuitry will be presented. In the first subsection, the design of a single ring oscillator cell will be discussed, afterwards the biasing mirror design will be explained and the third subsection will focus on the implementation of the injection action itself. The final subsection will present simulations of the locking transient.

Although the design has to be described linearly, the real process was iterative over many cycles and therefore some design decisions might not be listed in chronological order.

\subsection{Ring oscillator design}
\label{subsec:ccdlu_design}

The choice of 16 \ac{ILRO} stages requires the choice of a differential \ac{CCDLU} topology. Such a topology has been already presented in \autoref{subsec:dlu}, and the final version of it is shown on \autoref{fig:ccdlu_design}. Not depicted is the NMOS current mirror distributing $I_\s{BIAS}$ for all \acp{CCDLU} of a given \ac{ILRO}, which will be discussed later on in \autoref{subsec:bias_mirror}.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{obrazky/ccdlu_design_dc.pdf}
	\vspace{-0.1cm}
	\caption{Buffered differential \acs{CCDLU} topology} \label{fig:ccdlu_design}\vspace{-0.4cm}
\end{figure}

Since the target for the propagation delay $t_\s{d}$ is only \SI{50}{\pico\second}, which is a very short amount of time, it is important to be able to meet this specification with the lowest possible amount of current. Minimum-sized thin oxide MOS devices are the obvious candidate. 

Furthermore, low \ac{Vth} devices will be used for reasons illustrated on \autoref{fig:ccdlu_chart}\footnote{The center line is the nominal corner, while the filled area is bounded by worst $3\upsigma$ corners. The propagation delay has been measured between the inputs and the buffered outputs. Several \acp{CCDLU} have been connected in a delay line to simulate realistic driving and loading of each cell.}. Although the biasing current needed to reach $t_\s{d}=\SI{50}{\pico\second}$ is quite close for the typical corner of both \ac{MOS} device types (cca 11 to \SI{13}{\micro\ampere}), the problem is very visible for slow process corners (the upper bounds of the filled area). Not even $I_\s{BIAS}$ of \SI{50}{\micro\ampere} can lower the propagation delay of a \ac{CCDLU} made from normal \ac{Vth} devices to \SI{50}{\pico\second} in case of a $3\upsigma$ slow process skew. Using low \ac{Vth} devices is the only practical possibility in this use case for the given specification, and even then the specification is clearly at the limit of the technology.

\begin{figure}[htb]
	\centering
	\begin{minipage}[b][8cm][t]{.495\textwidth}
		\centering
    	\includegraphics[width=0.99\linewidth]{grafy/ccdlu.pdf}      
    	%\caption{Low \acs{Vth} \acs{CCDLU} chart}\label{fig:ccdlu}
    \end{minipage}   
     \hfill
	\begin{minipage}[b][8cm][t]{.495\textwidth}
		\centering
	    \includegraphics[width=0.99\linewidth]{grafy/ccdlu_normal.pdf}        
	    %\caption{Normal \acs{Vth} \acs{CCDLU} chart}\label{fig:ccdlu_normal}
	\end{minipage}
	\caption{Simulated propagation delay dependency on biasing current for low \acs{Vth} (left) and normal \acs{Vth} (right) minimum-sized \acs{CCDLU}}\label{fig:ccdlu_chart}
	\vspace{-0.5cm}
\end{figure}

A differential buffer stage is included each \ac{CCDLU}, as depicted on \autoref{fig:ccdlu_design}. The outputs of these buffers do not connect to the inputs of the next \ac{CCDLU} in line, but instead connect to a duty cycle correcting circuit. The duty cycle correcting circuit ensures that the duty cycle of a ring oscillator made from these \acp{CCDLU} is very close to 50\%, as if one of the phases was faster than the other, the cross connected passgates would help the slower phase to transition as soon as possible, equalizing the duty cycle.

The last inverter in the duty cycle corrector has increased driving capability (level 2 instead of level 1). The output of the last inverter will be connected to another chain of inverters, each one having larger driving capability than the previous one, ultimately connecting to the inputs of the \ac{TDC} latches, as depicted on \autoref{fig:tdc_overview}. Since there are multiple \ac{TDC}'s connected to each \ac{ILRO}'s outputs (as shown on \autoref{fig:tdc_overview}), the task of the buffers is to charge the non-negligible input capacitance of the \ac{TDC} latches and minimize the capacitance connected to the internal unbuffered output nodes. Increasing this capacitance needlessly would slow down the oscillator, increase the power consumption and reduce the slew rate.

The connection of the ring oscillator is illustrated on \autoref{fig:ilro_design}. Signals Ph[15:0], PhB[15:0] are the clock phases which ultimately connect to the \ac{TDC} latches via the aforementioned chain of buffers.

\begin{figure}[htb]
	\centering
	\includegraphics[width=12.5cm]{obrazky/ilro_design_2.pdf}
	\vspace{-0.1cm}
	\caption{\acs{ILRO} connection overview} \label{fig:ilro_design}\vspace{-0.3cm}
\end{figure}

The problem with the minimum sized \ac{MOS} devices within the \acp{CCDLU} is mismatch, which directly affects the \ac{DNL} of the \ac{FTDC}. It was simulated that when the \ac{CCDL} made from minimum sized MOS devices is connected as a free-running ring oscillator, the delay between the transitions of the neighbouring buffered clock phases varies by up to $\pm 90\%$ at $3\upsigma$, which is clearly unacceptable non-linearity. The usual rule-of-thumb is that the \ac{DNL} should be kept below $\pm 50\%$ of the \ac{LSB}.

In order to increase the precision of the \ac{LSB}, the devices within the \ac{CCDLU} need to be widened and/or lengthened. They cannot be, however, enlarged without consideration for the slowest \ac{PVT} corners, as in such corners, large \ac{MOS} devices within the \ac{CCDLU} could prevent the possibility of oscillation at the desired frequency of \SI{625}{\mega\hertz}, or only enable it for excessively large biasing currents. The iterative optimization process was difficult, as meeting both criteria with any safety margin at all is on the very limit of the chosen processing technology, and the sizing has to be optimized in conjunction with the biasing mirror (which will be discussed in \autoref{subsec:bias_mirror}), but eventually a satisfactory compromise has been found. 

\begin{table}[htb]
\vspace{-0.3cm}
\centering
\caption{\acs{CCDLU} device sizes}
\label{tab:ccdlu_sizes}
\vspace{-0.25cm}
\begin{tabular}{ccc}  
\toprule
Device 				& Width [\SI{}{\nano\meter}]	& Length [\SI{}{\nano\meter}]	\\
\midrule
$\s{M}_\s{1,2}$ 	& 120	& 60	\\
$\s{M}_\s{3,4}$ 	& 180	& 60	\\
$\s{M}_\s{5,6}$ 	& 150	& 60	\\
$\s{M}_\s{7,8}$ 	& 190	& 60	\\
$\s{M}_\s{9,10}$ 	& 180	& 90	\\
\bottomrule
\end{tabular}
\vspace{-0.15cm}
\end{table}%

The device sizes achieving this compromise are listed in \autoref{tab:ccdlu_sizes} (the device names match those depicted on \autoref{fig:ccdlu_design}), and they were optimized in conjunction with statistical sensitivity analysis, which highlighted the most and least sensitive devices with regards to their contribution to the propagation delay mismatch. As \autoref{tab:ccdlu_sizes} shows, the input NMOS pair $\s{M}_\s{1,2}$ kept its minimum width and length, as its contribution to the propagation delay mismatch is minimal, while the transistors in the buffer stage ($\s{M}_\s{7}$ to $\s{M}_\s{10}$) had to be enlarged considerably, because the sensitivity analysis revealed their statistical variation plays a comparatively larger role. The mismatch of the propagation delay has been simulated via Monte Carlo, and its value is around $17\%/\upsigma$, which for $3\upsigma$ is right on the edge of $50\%$.

\begin{figure}[!htb]
	\centering
	\includegraphics[width=14cm]{grafy/ccdlu_tran.pdf}
	\vspace{-0.3cm}
	\caption{Simulated \acs{CCDLU} typical transient signals} \label{fig:ccdlu_transient}\vspace{-0.3cm}
\end{figure}

The simulation depicted on \autoref{fig:ccdlu_transient} showcases \ac{CCDLU} transients. Naturally, the output of the buffered clock phases is delayed in relation to the unbuffered output which drives the next \ac{CCDLU} in line. 

Perhaps more interesting is the transient of the current drawn by the cell from the supply rail $I_\s{DD}$. The current quickly rises to around \SI{25}{\micro\ampere} when it starts charging the capacitances of the differential inverter delay cell itself. After the output voltage of the differential inverter reaches a threshold of roughly $V_\s{DD}/2$, the current stabilizes around \SI{13}{\micro\ampere} for a short while as it charges the buffer stage. The buffered clock phase transitions much more sharply than the unbuffered one, as its driving capability is stronger and the size of its capacitive load is smaller.

The most important takeaway here is that the biasing current behaves very dynamically, which is not surprising given that the whole transient takes roughly \SI{250}{\pico\second}. In this simulation, the \ac{CCDLU} was biased by \SI{11.5}{\micro\ampere}, which is the current required to reach \SI{50}{\pico\second} propagation delay as shown on \autoref{fig:ccdlu_chart}. However, on \autoref{fig:ccdlu_transient}, the current is clearly not limited by the value of the  biasing current. Therefore it is important to keep in mind that feeding the \ac{CCDLU} a certain biasing current does not mean the \acp{CCDLU} will be actually charged by this current. There is a relation between the biasing current fed into the input diode of the NMOS mirror distributing the current into each \ac{CCDLU} and the actual charging current (as proven by \autoref{fig:ccdlu_chart}, because if there was no relation, it would not be possible to control the propagation delay via the biasing current), but it is not a simple equality and parasitic capacitances charging and discharging play a significant role in the transient.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{grafy/f_vs_ibias.pdf}
	\vspace{-0.3cm}
	\caption{Free-running frequency \acs{f0} as a function of $I_\s{BIAS}$ for the designed \acs{ILRO}} \label{fig:ilro_f_vs_ibias}\vspace{-0.3cm}
\end{figure}

An important chart on \autoref{fig:ilro_f_vs_ibias} shows the free-running oscillation frequency of a ring oscillator made from the designed \acp{CCDLU} as a function of the biasing current. To achieve target $\ac{f0}=\SI{625}{\mega\hertz}$, a biasing current of roughly \SI{16.22}{\micro\ampere} is needed for the nominal corner. The filled area marks the boundaries of $3\upsigma$ \ac{PVT} corners again. 

The red line on \autoref{fig:ilro_f_vs_ibias} is the slowest worst case, which starts flattening out significantly just over \SI{500}{\mega\hertz}. The worst corner would not be as slow if minimum sized devices were used in the \ac{CCDLU}, but this is not possible due to maximum \ac{DNL} requirements. This suggests that \SI{625}{\mega\hertz} is at the practical limits of the technology, as faster oscillations would either require smaller devices with more mismatch, or much more biasing current for considerably less frequency gain, and due to the \ac{PVT} variation, a wide range of biasing currents would be required, which would put demanding requirements on the \ac{V-to-I} converter in the \ac{DLL}.

It was discovered that the most critical factor for the worst case slowest corner is the process and the supply voltage, while the temperature plays comparatively smaller role. Depending on the project requirements, tighter \ac{VDD} specification could be used (for example $\pm 5\%$ instead of $\pm 10\%$), which would require more precise and/or trimmed voltage regulator, but could bring added benefit of ensuring the slowest \ac{ILRO} corners are not as slow and many other analog circuits would pass \ac{PVT} validation more easily and/or with a larger safety margin.

It also should be acknowledged that the corners do not actually correspond to $3\upsigma$ probability ($0.27\%$), as when combined with the \ac{VDD} variation and extreme temperature, this combination has significantly lower probability of occurring.

\begin{figure}[!htb]
	\centering
	\includegraphics[width=14cm]{grafy/const_f0_ibias.pdf}
	\vspace{-0.3cm}
	\caption{\acs{ILRO} nominal biasing current for $\acs{f0}=\SI{625}{\mega\hertz}$} \label{fig:const_f0_ibias}\vspace{-0.4cm}
\end{figure}

The biasing current required to keep \ac{f0} equal to $\SI{625}{\mega\hertz}$ across the temperature range is shown on \autoref{fig:const_f0_ibias}. It is relatively linear and can be approximated by a slope of cca \SI[per-mode=symbol]{-15.4}{\nano\ampere\per\degreeCelsius}. This will be taken into account when designing the \ac{DLL} \ac{V-to-I} converter in \autoref{subsec:v-to-i}.

\subsection{Biasing mirror design}
\label{subsec:bias_mirror}

As already mentioned, each \ac{ILRO} cell has a single input biasing current terminal, and this current needs to be mirrored into each of the 16 \ac{CCDL} cells as shown on \autoref{fig:bias_mirror}. 

\begin{figure}[htb]
	\centering
	\includegraphics[width=8.5cm]{obrazky/ccdlu_bias_mirror.pdf}
	\vspace{-0.1cm}
	\caption{\acs{CCDL} NMOS biasing current mirror} \label{fig:bias_mirror}\vspace{-0.4cm}
\end{figure}

To preserve linearity, it would be desirable to achieve good matching in the current mirror so that each cell would produce the same propagation delay. This is, however, not very practical, because neither of the two main techniques for improving matching -- increasing device area and increasing overdrive -- are suitable for the circuit. 

Using large transistors is not suitable because of the need to minimize \ac{ILRO} footprint. The architecture contains a rather large amount of \acp{ILRO} which need to be routed in a particular way and the \acp{CCDLU} are otherwise quite small, as they are made out rather small thin oxide devices. 

Increasing the overdrive of the current mirror too much is problematic as well because the current source supplying the current to the mirror (the \ac{V-to-I} converter, which will be discussed in \autoref{subsec:v-to-i}) has limited compliance and especially in slow \ac{MOS}, low \ac{VDD} and/or cold corners, the \ac{VGS} of the \ac{ILRO} biasing mirror could make the PMOS current source step out of saturation, lowering the output impedance as well as accuracy of the supplied current, which is undesirable. The current source compliance constraint defines the minimum $W/L$ ratio for the NMOS biasing mirror devices, which was determined by simulation to be $5/8$, as longer and narrower devices were not able to meet the minimum $\SI{50}{\milli\volt}$ saturation margin (\texttt{vdsat{\_}marg} device parameter) over $3\upsigma$ \ac{PVT} corners.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{grafy/biasing_mirror_variation.pdf}
	\vspace{-0.3cm}
	\caption{\acs{ILRO} free-running frequency variation and mismatch for various biasing current mirror device sizes} \label{fig:bias_mirror_variation}\vspace{-0.4cm}
\end{figure}

A Monte Carlo statistical analysis was performed to find the optimum size of the current mirror devices. The goal was to find a relatively small device size which minimizes the free-running frequency variation as well as mismatch. The following dimensions (width/length) were analysed: \SI{0.2}{\micro\meter}/\SI{0.32}{\micro\meter}, \SI{0.3}{\micro\meter}/\SI{0.48}{\micro\meter}, \SI{0.4}{\micro\meter}/\SI{0.64}{\micro\meter}, \SI{0.5}{\micro\meter}/\SI{0.8}{\micro\meter} and \SI{0.6}{\micro\meter}/\SI{0.96}{\micro\meter}. The results of the analysis are shown on \autoref{fig:bias_mirror_variation}\footnote{The term \enquote{\ac{f0} variation} refers to the statistical variation of the free-running frequency of a single \ac{ILRO} instance, while the term \enquote{\ac{f0} mismatch} refers to the difference of free-running frequencies of two independent \acp{ILRO}.} (filled areas mark the span of the quantities across \ac{PVT} corners). 

Clearly, the optimum device size which minimizes both types of statistical variation is the third option, i.e. \SI{0.4}{\micro\meter}/\SI{0.64}{\micro\meter}. The reason for why larger devices than that actually worsen the matching is probably connected to the fact that the biasing mirror supplies current dynamically, and larger devices have larger parasitic capacitance, which can easily vary due to manufacturing variation.

%Additional statistical analysis is shown in \autoref{tab:bias_mirror_variation_analysis}. The goal of this analysis was to determine how much absolute variation as well as mismatch of the free-running frequency of the \acp{ILRO} can be attributed to the biasing mirror mismatch. This was done by enabling and/or disabling mismatch (local) and process (global) contributions to the overall statistical variations in the simulator, as well as by comparing the results with an \ac{ILRO} biased by an ideal, \ac{CCCS} based mirror circuit with no statistical variation at all.
%
%\begin{table}[htb]
%\catcode`\-=12	%% toto tu musí být kvůli češtině, která nějak divně používá pomlčky... jinak nefungují commandy jako cmidrule/cline
%\centering
%\caption{\acs{ILRO} statistical variation analysis}
%\label{tab:bias_mirror_variation_analysis}
%\vspace{-0.25cm}
%\begin{tabular}{cccccccc}  
%\toprule
%\multirow{2}[2]{*}{Current mirror} 	&    \multicolumn{2}{c}{Process \& mis} 	& \multicolumn{2}{c}{Mismatch} &	\multicolumn{2}{c}{Process} & \multirow{2}[2]{*}{Unit}	\\
%\cmidrule(lr){2-3}
%\cmidrule(lr){4-5}
%\cmidrule(lr){6-7}
% 	&   $f_\s{0}$ var  	& $f_\s{0}$ mis &	$f_\s{0}$ var  	& $f_\s{0}$ mis	& 	$f_\s{0}$ var  	& $f_\s{0}$ mis\\
%\midrule
%Realistic 	& 6.1 	& 7.0	& 5.2	& 7.0 	& 3.4	& 0 & \multirow{2}[0]{*}{\%/$\upsigma$}	\\
%Ideal 		& 4.0 	& 2.0	& 2.6	& 2.0	& 3.2	& 0 &	\\
%\bottomrule
%\end{tabular}
%\end{table}%
%
%The takeaway is that the biasing mirror mismatch causes the majority of both $f_\s{0}$ mismatch and variation. Unfortunately, there is not much more that can be done to improve this, as the mirror device size has been already optimized. This error source will simply have to be taken into account when determining the trimming range, and the mismatch of the mirror will affect the \ac{DNL} of the \ac{FTDC} heavily even after trimming.

The biasing current mirror shown on \autoref{fig:bias_mirror} features an RC low-pass filter between the input diode and the 16 current sources. The reason for its inclusion is that each of the 16 current sources only supply current dynamically during short transients, as shown on \autoref{fig:ccdlu_transient}. The charging and/or discharging of their capacitance produced significant periodic spikes in the voltage at their gates, which propagated backwards as far as into the \ac{V-to-I} converter which supplied the biasing current into the mirror (the \ac{V-to-I} converter will be described in \autoref{subsec:v-to-i}). The period of these spikes is \SI{50}{\pico\second}, as the \acp{CCDLU} are designed to transition one by one after this period of time. The equivalent frequency of these spikes is \SI{20}{\giga\hertz} and therefore a simple RC low-pass filter made from \SI{10}{\kilo\ohm} P+ polysilicon resistor and a \SI{500}{\femto\farad} NMOS capacitor is able to filter them significantly, as the cut-off frequency of such a filter is roughly \SI{32}{\mega\hertz}.

\subsection{Injection circuit design}
\label{subsec:inj_circuit_design}

A possible injection circuit has been shown in \autoref{chapter:ilo_theory} on \autoref{fig:injection_circuit}. This circuit has been published in \cite{ilo_paper} and was supposedly successfully used for locking an \ac{ILRO} with a resolution of \SI{52}{\pico\second}. This circuit injects charge through capacitors directly connected to an internal \ac{ILRO} node. 

The authors of \cite{ilo_paper} do not specify the size of this capacitance. If small capacitance is used, the maximum charge which can be injected is limited and the locking range suffers. If high capacitance is used, large area is taken. In both cases, however, the extra capacitance connected to the injection node imbalances the symmetry of the oscillator and the propagation delay from one cell to the other can differ extremely even in free-running state, worsening the linearity of the \ac{FTDC} significantly. Therefore, identical dummy capacitance must be connected to each internal node of the oscillator just to equalize the propagation delays again. However, this not only takes significant area (depending on the size of the capacitance), but it also necessitates the use of a larger biasing current, as the \acp{CCDLU} now have to charge larger total capacitance. Therefore, power consumption is increased as well.

\begin{figure}[!htb]
	\centering
	\includegraphics[width=13cm]{obrazky/injection_methods_design.pdf}
	\vspace{-0.1cm}
	\caption{Alternative injection methods} \label{fig:injection_methods}\vspace{-0.4cm}
\end{figure}

The injection circuit from \autoref{fig:injection_circuit} has been thoroughly simulated, but it has been decided that its implications for the performance of the \ac{ILRO} are too disadvantageous and a better solution has been sought after. Such a solution does not need to necessarily add zero capacitance to the injection node, as that is clearly impossible. It should, however, provide a better trade-off between parasitic capacitance, area and locking range, as well as perhaps better \ac{PVT} stability. Four such proposals are shown on \autoref{fig:injection_methods}.

All of these methods share the same devices which are directly connected to the injection stage -- minimum sized \ac{MOS} switches. The switches represent relatively low capacitance (as low as realistically possible in a given technology) and also relatively low impedance to the flow of current in their \enquote{on} state. The minimum size of the switches also helps minimize charge injection and clock feed-through, as these effects could degrade the phase noise performance of the oscillator.

The four methods shown on \autoref{fig:injection_methods} were all simulated and compared according to various values such as power consumption, area, injected charge etc. It turned out that the simplest possible mechanism (switches only) is the best on paper, as it offers the largest possible locking range and the smallest area. Every other method such as injection through resistors, \ac{MOS} current sources or switched capacitors is more area intensive and only lowers the locking range as it ultimately limits the maximum possible charge transferred.

\begin{figure}[!htb]
	\centering
	\includegraphics[width=11cm]{obrazky/ilro_design_injection.pdf}
	\vspace{-0.1cm}
	\caption{Designed injection circuit} \label{fig:injection_circuit_design}\vspace{-0.4cm}
\end{figure}

In the end, however, the resistor option has been chosen anyway and is depicted on \autoref{fig:injection_circuit_design}. There are two reasons for this choice. First of all, \ac{MOS} switches on their own are quite sensitive to \ac{PVT} variation, which could change the behaviour of the injection circuit significantly. Adding the resistors should in principle make the circuit more predictable. Secondly, in fast \ac{MOS} corners where the drain-source on resistance $R_\s{DS,on}$ is unusually low, adding the resistors should reduce the harsh spikes experienced by the \SI{1.2}{\volt} rail when the injection switches switch. These spikes could negatively affect the stability of the supply rail.

\begin{figure}[!htb]
	\centering
	\includegraphics[width=14cm]{grafy/locking_range.pdf}
	\vspace{-0.1cm}
	\caption{Locking range of the designed \acs{ILRO} for various sizes of $R_\s{inj}$} \label{fig:locking_range_design}\vspace{-0.4cm}
\end{figure}

The precise value of the resistance of \SI{1}{\kilo\ohm} has been chosen as it is the highest amount of resistance which does not affect the locking range of the \ac{ILRO} significantly, as shown on \autoref{fig:locking_range_design}\footnote{This chart is similar to \autoref{fig:ilro_locking_range} and indeed the size of the resistance is inversely proportional to injection ratio introduced in \autoref{chapter:ilo_theory}. The injection ratio is not evaluated in practical transistor level design because it varies significantly over \ac{PVT} corners and because the non-linear behaviour of transistors produces irregular dynamic waveforms, which reduces the usefulness of the concept in this context.}. The standard P+ polysilicon resistor device has been selected to implement the resistance.

As \autoref{fig:injection_circuit_design} shows, the injection circuit is designed so that it injects energy after a rising edge of the injection clock. It does not, however, inject energy after a falling edge. This decision has several consequences. First of all, injecting only on one edge of the clock naturally lowers the locking range, as less energy is injected on average. However, this should not be an issue because the \acp{ILRO} will be pre-trimmed quite close to target frequency, as was discussed in \autoref{subsec:clock_pll_dll}. Injecting on one edge only should therefore save some power. Second reason is the area saving -- injecting on one edge saves second instance of the switches, resistors and pulse shaping circuits, as well as additional dummy switches which would be required to balance the delay line. This leads us to the third reason, which is additional power saving -- the additional dummies would increase the biasing current requirement of the \ac{ILRO}, as the added capacitance would slow down the oscillations. The final reason is phase noise. If the duty cycle of the injection clock at the point of use is not very close to 50\%, the \ac{ILRO} would lock to only a single edge of the clock anyway. This was demonstrated in \autoref{subsec:ilo_modelling_duty}. The edge which the \ac{ILRO} would not lock onto will burn power needlessly and could potentially decrease the spectral purity of the clock phases with its out-of-phase energy injections.

There is also a reason for why the resistors on \autoref{fig:injection_circuit_design} connect to the supply rails and the switches connect them to the rest of the \ac{ILRO} and not the other way around. While the \ac{MOS} switches could drive the resistors better if they were connected to the supply rails instead, as the voltage drop on the resistors during the transient would not subtract from their \ac{VGS}, the resistors have some parasitic capacitance which differs from the parasitic capacitance of the minimum sized \ac{MOS} switches. As the goal is to match the capacitive load of each \ac{ILRO} stage in order to ensure that each stage has the same amount of propagation delay, dummy injection circuits need to be added to all stages. If the order of the resistor and the switch was reversed, identical resistors and switches would need to be added to each stage, as the resistor and switch combination acts as a $\Pi$ RC circuit. This would take a lot of area due to the resistors. Instead, if the resistor is connected to the rails and the switches to the \ac{ILRO}, only the dummy switches need to be added to all other nodes, excluding the resistor. This is because the resistor capacitance of the injection circuit is somewhat shielded from the \ac{ILRO} by the switch. It has been simulated that this way the propagation delays match quite well as shown on \autoref{fig:ilro_delay_distribution}. For perfect matching, resistors would need to be added to the dummy injection circuits anyway, but the improvement in matching would be less than a picosecond, which is well below the size of the \ac{LSB} and is simply not worth it.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{grafy/ilro_delay_distribution.pdf}
	\vspace{-0.1cm}
	\caption{Propagation delay distribution within the \acs{ILRO} with and without dummy switches, when free-running at $\acs{f0}=\SI{625}{\mega\hertz}$} \label{fig:ilro_delay_distribution}\vspace{-0.4cm}
\end{figure}

The circuit which shapes the injection pulses themselves is simply a rising edge detector with a pulse width set by the propagation delay of the standard cell buffers, which are followed by an inverter, so that logic inversion is achieved. The circuits produce a pulse of roughly \SI{80}{\pico\second} length in typical case. This pulse width has been chosen so that the time roughly matches the length of the transition at the injection node, so that the \enquote{sensitive window} of the \ac{ILRO} is covered (see \autoref{subsec:ilro_limitations}). The pulse width produced by the circuit varies over \ac{PVT}, but thankfully the \ac{ILRO} is quite insensitive to the variation of the pulse width. This is because the \ac{ILRO}, once locked, always aligns its phase in such a way to accept the exact amount of energy it needs. Varying the pulse width affects this phase alignment between the injection clock and its injection stage, but the phase of the clock phases does not matter as much, because thanks to the sliding scale operation inbuilt into the architecture, the \acp{FTDC} only depends on the frequency of the output clock phases, which is unaffected (this benefit of the sliding scale technique was discussed in \autoref{subsec:timing_diagram}).

\subsection{Locking simulations}
\label{subsec:ilro_design_sims}

Since the \acp{ILRO} will be biased by the \ac{DLL}, in this section, only a few simulations will be discussed. A more thorough evaluation will be presented in \autoref{sec:top_sims}.

\begin{figure}[!htb]
	\centering
	\includegraphics[width=14cm]{grafy/injection_wvfs.pdf}
	\vspace{-0.3cm}
	\caption{Typical waveforms of the injection stage voltage, the injection pulse and the injected current for a locked \acs{ILRO} of $\acs{f0}=\SI{590}{\mega\hertz}$} \label{fig:injection_wvfs}\vspace{-0.4cm}
\end{figure}

Typical transients of the unbuffered output voltage of the 15th stage (the node which is injected into), the injection switch signal SYNC and the injection current are shown on \autoref{fig:injection_wvfs}. Unsurprisingly, the injection current is rather dynamic similarly to the \ac{CCDLU} charging current from \autoref{fig:ccdlu_transient}. The width of the SYNC pulse roughly matches the length of the transition of the voltage at the injection node.

\begin{figure}[!htb]
	\centering
	\includegraphics[width=14cm]{grafy/iinj_wvfs.pdf}
	\vspace{-0.3cm}
	\caption{Various waveforms of injected current into \acsp{ILRO} of various $\acs{f0}$ when locked to \SI{625}{\mega\hertz}} \label{fig:iinj_wvfs}\vspace{-0.4cm}
\end{figure}

The shape of the injection current waveform varies dramatically depending on the \ac{f0} of the \ac{ILRO}. In some cases, the \ac{ILRO}'s \ac{f0} is quite close to the target, not a lot of charge is needed to lock it and the injected current is relatively flat. In other cases, however, the \ac{f0} is on the edge of the locking range and the injection current waveform has to be relatively large and long in order to deliver the charge required to lock the oscillator. Several picked shapes of these injection waveforms are depicted on \autoref{fig:iinj_wvfs}.

The charge injected into the circuit for various sizes of the injection resistor as a function of the free-running frequency is shown on \autoref{fig:qinj}. The dataset in the chart is limited to free-running frequencies the oscillator was able to lock onto (the locking range was already shown on \autoref{fig:locking_range_design}). An interesting takeaway is that for a given free-running frequency, the charge injected by the circuit with higher injection resistance is less. This seems to suggest that the injection circuits with less resistance inject energy needlessly, as less injected charge would have been sufficient. On the other hand, the higher the injection resistance, the narrower the locking range, which is the more important concern.

\begin{figure}[!htb]
	\centering
	\includegraphics[width=14cm]{grafy/qinj.pdf}
	\vspace{-0.3cm}
	\caption{Charge injected by the injection circuit into an \acs{ILRO} per cycle once locked to \SI{625}{\mega\hertz} as a function of initial free-running frequency} \label{fig:qinj}\vspace{-0.4cm}
\end{figure}

The second takeaway is the asymmetry between the right and left half of the chart. While for $\ac{f0}>\SI{625}{\mega\hertz}$ the injected charge grows quite linearly, for $\ac{f0}<\SI{625}{\mega\hertz}$, the situation is very different. The source for this asymmetry has not been definitively identified, but it is most likely caused by the interaction of the asymmetry of the rise and fall times of the unbuffered \ac{CCDLU} output (listed in \autoref{tab:ilro_perf}) as well as the asymmetry of the injection circuit (the PMOS side and the NMOS side of injections do not necessarily operate exactly the same way).

The instantaneous frequency of \acp{ILRO} of various free-running frequencies under locking is shown on \autoref{fig:locking_wvfs}. In the chart, injection starts at $t=\SI{22}{\nano\second}$, which is why there is an abrupt change of instantaneous frequency, often caused by the injection pulse deforming the shape of the measured clock phase. This can even cause the frequency measurement function (\texttt{freq} from Cadence ADE) to erroneously return extremely high frequencies, which can be seen on \autoref{fig:locking_wvfs}. The free-running frequency of the waveforms can be seen at roughly $t=\SI{15}{\nano\second}$, before the injections start.

\afterpage{\begin{landscape}
\begin{figure}[p]
\begin{center}
\vspace{-1cm}
\captionsetup{type=figure} 
    \includegraphics[width=22.15cm]{grafy/locking_wvfs.pdf}
    \captionof{figure}{Instantaneous frequency of \acsp{ILRO} with various \acs{f0} during locking}
    \label{fig:locking_wvfs}
\end{center}
\end{figure}
\end{landscape}
\clearpage}

As a side note, the transient simulation shown on \autoref{fig:locking_wvfs} is precisely how locking range is actually determined. There is no other reliable way other than trying to lock the \ac{ILRO} in transient simulation, letting it run for several hundreds of oscillatory cycles and seeing if the instantaneous frequency matches the injected one by the end of the simulation. This is a very time intensive simulation, which is why this simulation cannot be practically performed in Monte Carlo runs or for \ac{PVT} corners in conjunction with \ac{f0} variation. The locking range shown on \autoref{fig:locking_range_design} has been therefore only determined for the nominal case (and the concept of locking range, when \ac{PVT} corners are taken into account, is not as useful of a design tool any more anyway).

As \autoref{fig:locking_wvfs} shows, in all the depicted simulation runs, the \acp{ILRO} are able to lock to the injected frequency eventually. The locking transient itself is very abrupt, but there can be a big difference in the time it takes for the \ac{ILRO} to lock. In some runs, the \ac{ILRO} was able to lock as soon as the injections start, while for others, it can take hundreds of oscillatory cycles to lock.

Upon closer inspection, there seems to be an inverse relationship between $\ac{f0}-\ac{finj}$ and the time it takes for the \ac{ILRO} to lock. In other words, the closer the \ac{ILRO}'s natural oscillations are to the target frequency, the longer it actually takes to lock to it. This might appear counter-intuitive at first, but it can be explained in a simple manner, and the mechanism is shown on an idealized diagram on \autoref{fig:inj_phase_shift}. 

\begin{figure}[!htb]
	\centering
	\includegraphics[width=12cm]{obrazky/inj_phase_shift.pdf}
	\vspace{-0.1cm}
	\caption{Injection locking process} \label{fig:inj_phase_shift}\vspace{-0.4cm}
\end{figure}

When the injections start, the phase shift between the injection pulse and the transition of the voltage at the injection stage it needs to synchronise with (the \enquote{sensitive window}) in order to lock is random. If the \ac{f0} is several percent off the \ac{finj}, this difference in frequency will ensure that the phase shift between the two waveforms will vary quickly and the injection pulse will line up with the sensitive window soon. Once the two waveforms line up correctly in time, the frequency of the \ac{ILRO} locks to the injected frequency immediately and abruptly (as long as the frequency is within the locking range of the oscillator), as proven by \autoref{fig:locking_wvfs}. If, however, the \ac{f0} is very close to target frequency, the difference in frequencies is so small that it can take hundreds or even thousands of cycles before the phase shift between the injection pulse and the sensitive window adjusts properly. 

Theoretically, if \ac{f0} was equal to \ac{finj}, the phase shift between the two waveforms would stay constant forever and the \ac{ILRO} would actually never lock. In reality, this will not occur due to noise, temperature variations etc. but the locking process in these cases could take longer than usual.

Finally, some scalar quantities of interest related to the designed \ac{CCDLU} or \ac{ILRO} are listed in \autoref{tab:ilro_perf}. 

\begin{table}[htb]
\vspace{-0.3cm}
\centering
\caption{\acs{ILRO} performance}
\label{tab:ilro_perf}
\vspace{-0.25cm}
\begin{tabular}{ccccc}  
\toprule
Quantity 				& Min.	& Typ. 	& Max.	& Unit	\\
\midrule
\acs{CCDLU} area 		& 	& 14.7 	& 	& \SI{}{\micro\meter\squared}	\\
\acs{ILRO} area			& 	& 342 	& 	& \SI{}{\micro\meter\squared}	\\
Supply current			& 	& 502.4 	& 	& \SI{}{\micro\ampere}	\\
Power consumption		& 	& 602.9 	& 	& \SI{}{\micro\watt}	\\
$t_\s{d}$ mismatch		& 	& 17 	& 	& $\%/\upsigma$	\\
Duty cycle variation	& 	& 0.83 	& 	& $\%/\upsigma$	\\
$V_\s{O}$ rise time		& 75.9	& 87.1	& 102.8	& \SI{}{\pico\second}	\\
$V_\s{O}$ fall time		& 40.6	& 48.6	& 54.6	& \SI{}{\pico\second}	\\
$V_\s{BO}$ rise time	& 12.1	& 16.0	& 22.2	& \SI{}{\pico\second}	\\
$V_\s{BO}$ fall time	& 12.1	& 16.0	& 22.2	& \SI{}{\pico\second}	\\
SYNC pulse width		& 59.8	& 78.7	& 86.6	& \SI{}{\pico\second}	\\
\bottomrule
\end{tabular}
\vspace{-0.15cm}
\end{table}%

With regards to the listed areas, it has to be noted that they refer to the total device area of the designed circuits. After layout, the total area would be likely $50{-}100\%$ larger, depending on the circuit, any special routing needs as well as the experience of the layout engineer.

The supply current and power consumption figures listed in \autoref{tab:ilro_perf} are related to the nominal corner under locking. Minimum and maximum values are not provided for these quantities because the values depend too much on the way the \ac{ILRO} is biased, which has not been discussed yet.

\section{Delay Locked Loop design}
\label{sec:dll_design}

In this section, the design of the \ac{DLL} will be presented. First, the overview of the loop will be given. Afterwards, the \ac{FPD} and charge pump cell will be designed, followed by the \ac{V-to-I} converter. In the final subsection, the implementation of trimming will be thoroughly discussed.

\subsection{Overview}

A simplified overview of the designed \ac{DLL} is shown on \autoref{fig:dll_overview}. It consists of three larger blocks: the delay line, the \ac{FPD} \& charge pump block, and the \ac{V-to-I} converter.

\afterpage{\begin{landscape}
\begin{figure}[p]
\begin{center}
\captionsetup{type=figure} 
    \includegraphics[width=23.65cm]{obrazky/dll_design_overview.pdf}
    \captionof{figure}{Simplified overview of the \acs{DLL}}
    \label{fig:dll_overview}
\end{center}
\end{figure}
\end{landscape}}

The role of the \ac{DLL} is to provide a \ac{PVT} compensated biasing current for the \acp{ILRO}. Fortunately, much like the \acp{ILRO}, the \ac{DLL} will only ever be locked to \SI{625}{\mega\hertz} and therefore many issues regarding its locking range, behaviour at various frequencies etc. are not relevant, which greatly simplifies the design process.

A key consideration for the design of the \ac{DLL} is the need to connect the delay line in a way as similar as possible to the connection of the \ac{ILRO} in order to ensure that the biasing current which satisfies the \ac{DLL} lock condition is as close to the current needed to set the free-running frequency of the \acp{ILRO} to \SI{625}{\mega\hertz} as possible. There are only two things that can be done to achieve this, both of which are depicted on \autoref{fig:dll_overview}: driving the delay line by a preceding delay line and loading the delay line by a dummy delay line as well. This is because the delay line in the \acp{ILRO} is connected in a ring connection, driving and loading itself.

Other than that, there are no critical requirements for the \ac{DLL}. Since the \ac{DLL} is a block which will be only instantiated once, minimizing area is not as important as with other blocks like the \ac{ILRO}. The speed of the start-up and the feedback loop of the \ac{DLL} is also not as important, as the \ac{DLL} has to be active at all times during the \ac{TDC} conversion and will not be switched on and off dynamically during conversions. A few things which should be kept in mind, however, is prevention of false locking, good filtering of the charge pump, adequate speed of the \ac{V-to-I} converter opamp loop that is able to follow the \ac{DLL} and some attention should be also paid to power supply rejection (it is expected that the \SI{1.2}{\volt} supply might be rather polluted with high frequency switching noise).

The design of the \ac{DLL} blocks will be discussed in the following sections.

\subsection{Frequency Phase Detector and Charge Pump}
\label{subsec:fpd_cp}

The role of the \ac{FPD} and the charge pump, which form a single cell together, is to convert the phase difference between the clock input and its delayed counterpart into a corresponding change in voltage at the charge pump output. A variation of a common topology has been chosen as shown on \autoref{fig:fpd_cp}. The \ac{FPD} consisting of two D-type flip-flops and a resetting NAND gate is shown in the upper left, while the rest of the schematic shows the charge pump along with its biasing current mirrors and pre-charge circuit.

\afterpage{\begin{landscape}
\begin{figure}[p]
\begin{center}
\captionsetup{type=figure} 
    \includegraphics[width=23.65cm]{obrazky/fpd2.pdf}
    \captionof{figure}{Simplified schematic of the designed \acs{FPD} and charge pump block}
    \label{fig:fpd_cp}
\end{center}
\end{figure}
\end{landscape}}

%\begin{figure}[htb]
%	\centering
%	\includegraphics[width=12cm]{obrazky/fpd.pdf}
%	\vspace{-0.1cm}
%	\caption{\acs{FPD} and charge pump simplified schematic} \label{fig:fpd_cp}\vspace{-0.3cm}
%\end{figure}

If enabling signal EN is low, the circuit is disabled and does not react to the clocked inputs. As long as EN is high, the \ac{FPD} operates as normal, and the sequence of the signals can be seen on \autoref{fig:fpd_signals}.

\begin{figure}[htb]
	\centering
	\includegraphics[width=6cm]{obrazky/fpd_signals.pdf}
	\vspace{-0.1cm}
	\caption{\acs{FPD} signal sequence} \label{fig:fpd_signals}\vspace{-0.4cm}
\end{figure}

An important feature of the operation of the \ac{FPD} is the delay between the moment when the second flip-flop activates and the moment the flip-flops are actually reset. This delay, on \autoref{fig:fpd_signals} marked as $t_\s{error}$, is caused by finite speed of the digital gates. 

There is a consequence to this error. First of all, the finite speed of the reset path means that there is a time period where the signals UP and DWN overlap. This could cause the charge pump to pull in both directions. Theoretically, if the charge pump current source and the current sink matched perfectly, this would have no effect on \ac{VCPO}, but in reality, any mismatch can cause an erroneous change in \ac{VCPO} during this short period of time. Gating the signals to shorten the overlap would be possible, but gates have limited speed and do not match perfectly either.

The consequence of this erroneous change of \ac{VCPO} is that while the \ac{DLL} will settle, the phase difference between the reference and delayed clock signals at the input of the \ac{FPD} will not be zero. This is because the \ac{DLL} tries to stabilize \ac{VCPO} by any means necessary, and if there is an error current $I_\s{error}$ flowing into the charge pump capacitor due to mismatch, the loop will compensate it by inducing a non-zero phase shift at the input of the \ac{FPD}. Other than increasing the size of the charge pump current mirror devices to improve matching, there is not much more that can be done to prevent this issue. Trimming, which will be discussed in \autoref{subsec:trimming}, can alleviate it though.

Simulating the exact relationship between the error current $I_\s{error}$ and the phase shift seen at the input of the \ac{FPD} is not straightforward. The following simulation has been devised to provide a reasonable approximation. An ideal \ac{DC} current source representing the error current has been connected in parallel to the charge pump output capacitor, and its current has been swept. A transient simulation simulating the whole \ac{DLL} operation has been performed for each swept point, and the input phase shift at the \ac{FPD} has been saved. This phase shift then has to be re-evaluated, as the ideal \ac{DC} current source provides current at all times, while the real error current only flows when both $\s{\overline{UP}}$ and DWN signals are active. The length of these signals when the input phase shift is zero is around \SI{90}{\pico\second}, while the period of the \ac{DLL} input signal is \SI{1.6}{\nano\second}, i.e. the duty cycle of the error current is around 5.6\%. Therefore the simulated phase shift is scaled accordingly by this factor to produce an estimate of phase shift seen at the input of the \ac{FPD} based on the size of the error current $I_\s{error}$ in relation to $I_\s{CP}$, as depicted on \autoref{fig:fpd_mismatch}.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{grafy/fpd_mismatch.pdf}
	\vspace{-0.1cm}
	\caption{\acs{FPD} input phase shift as a function of charge pump current source mismatch when connected in a \acs{DLL}} \label{fig:fpd_mismatch}\vspace{-0.4cm}
\end{figure}

The error current has been swept from $-20\%$ to $20\%$ as a Monte Carlo simulation has shown that the designed charge pump current sources match to $6.4\%/\upsigma$, which is nearly $20\%$ for $3\upsigma$. The worst case phase shift at the input of the \ac{FPD} caused by this mismatch is around \SI{12}{\pico\second}. This is about $1.5\%$ of the target delay of \SI{800}{\pico\second}, which corresponds to a similar error of \ac{f0} in an \ac{ILRO} biased by this \ac{DLL}, which is an error small enough to not matter significantly (this will be proven in \autoref{subsec:trimming}). Mismatch caused by fabrication is static and produces a static error that can be trimmed out, but it does not endanger the capability of the \ac{DLL} to track \ac{VT} variation.

There is actually a benefit to the limited speed of the digital gates. If the phase error at the input of the \ac{FPD} was rather small, extremely fast digital gates could produce extremely short digital pulses which would be reset much sooner than the charge pump could react to them. This would lead to a dead-zone of the \ac{FPD} \& charge pump transfer characteristic in the vicinity of zero input phase error. The consequence would be that within the dead-zone, the delay of the \ac{DLL} delay line and therefore the free-running frequency of the \acp{ILRO} biased by this \ac{DLL} could vary very slightly without any correction of the \ac{DLL} loop, as the dead-zone would make this small variation essentially invisible. This would naturally result in degraded phase noise performance. As long as $t_\s{error}$ is larger or similar to the bandwidth of the charge pump switches, the dead-zone is not present and the \ac{FPD} \& charge pump system can in principle react to very small phase errors at its input properly.

The values of $t_\s{error}$ and some other scalar quantities of interest are listed in \autoref{tab:fpd_perf}. The quantities were evaluated for zero input phase error, which is the state the \ac{FPD} is expected to work in most of the time when \ac{DLL} settles.

\begin{table}[htb]
\vspace{-0.3cm}
\centering
\caption{\acs{FPD} performance}
\label{tab:fpd_perf}
\vspace{-0.25cm}
\begin{tabular}{ccccc}  
\toprule
Quantity 				& Min.	& Typ. 	& Max.	& Unit	\\
\midrule
Device area 			& 	& 228 	& 	& \SI{}{\micro\meter\squared}	\\
Supply current 			& 55.7	& 77.3 	& 103.9	& \SI{}{\micro\watt}	\\
Power consumption 		& 60.1	& 92.7 	& 137.2	& \SI{}{\micro\watt}	\\
$t_\s{RSTB}$ 			& 51.9	& 85.6 	& 164.5	& \SI{}{\pico\second}	\\
$t_\s{error}$			& 62.1	& 102.2 & 194.5	& \SI{}{\pico\second}	\\
$I_\s{error}/I_\s{CP}$	& 		& 6.4 	& 		& $\%/\upsigma$	\\
\bottomrule
\end{tabular}
\vspace{-0.15cm}
\end{table}%

The size of the charge pump current has to be selected in conjunction with the output capacitor. The goal is to choose a capacitor large enough to sufficiently smooth out the transitions at the output, but not too large either, as that would increase the footprint. Luckily there is only one \ac{DLL} in the system (another advantage over the architecture shown on \autoref{fig:local_clock_dlls}) and therefore a rather large NMOS capacitor can be used. In this design, the values \SI{1}{\pico\farad} and \SI{4}{\micro\ampere} were chosen for the capacitor and the current sources respectively.

The start-up time of the circuit has been improved with a circuit shown on \autoref{fig:fpd_cp}. When EN is low, the circuit pre-charges the capacitor to a voltage one \ac{VGS} drop below the supply rail, which should be (very roughly) $0.5{\times}V_\s{DD}$. This hastens the locking of the \ac{DLL}, as such a voltage should, after being converted to a biasing current by the \ac{V-to-I} converter, produce a reasonable starting delay in the delay line.

The schematic on \autoref{fig:fpd_cp} features twice the amount of current mirrors needed. The motivation for their inclusion is to stop transient disturbances from travelling backwards from the charge pump output switches to the biasing circuits. On the other hand, the additional mirrors increase the overall current mismatch. The current mirror devices were therefore scaled accordingly to minimize it.

There are two switches connected to each \ac{MOS} transistor sourcing/sinking current to/from the charge pump capacitor. The additional switches (the PMOS switch connected to UP signal, and the NMOS switch connected to $\s{\overline{DWN}}$ signal) are not necessary for correct operation of the \ac{FPD}, but they serve a purpose nonetheless. Their purpose is to keep the current sources supplying current at all times (when the \ac{FPD} is enabled). If they were not included, the other switches would turn off the current paths completely and no current would flow. While this would save power, it would also slow down the operation, as some time would have to be spent on charging various parasitic capacitances before the current sourcing \ac{MOS} transistors would supply current to the output capacitor again.

The transfer characteristic of the \ac{FPD} \& charge pump cell is shown on \autoref{fig:fpd_current}. The input frequency was \SI{625}{\mega\hertz}, which corresponds to a period of \SI{1.6}{\nano\second}.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{grafy/fpd_current.pdf}
	\vspace{-0.3cm}
	\caption{\acs{RMS} charge pump output current as a function of \acs{FPD} input phase shift} \label{fig:fpd_current}\vspace{-0.4cm}
\end{figure}

As the span of the filled area shows, the transfer characteristic is somewhat \ac{PVT} sensitive (which ultimately does not matter from a \ac{DC} standpoint, as it only really affects how quickly the \ac{DLL} reacts to changes in input phase), but it also features an abrupt change as the input phase shift gets closer to $\pm T_\s{in}$. This sharp edge is caused by the finite speed of the digital cells (when the phase shift approaches $\pm T_\s{in}$, the reset pulse can overlap with incoming input signal edges and prevent the \ac{FPD} from reacting to them) and is unavoidable in the given topology. It could in principle cause false-locking of the \ac{DLL}, which is why pre-charging the charge pump capacitor is important, as it ensures that the default state of the charge pump output creates a phase shift not too far from the target. Trimming of the \ac{DLL}, which will be discussed in \autoref{subsec:trimming}, also helps prevent harmonic false locking.

The chart on \autoref{fig:fpd_iout_vout} shows how the \ac{VCPO} affects the charge pump output current. In this simulation, both $\s{\overline{UP}}$ and DWN signals were made active, and the desired value of output current is therefore zero, as the current supplied by the upper current source should be consumed by the lower current sink. The \ac{DC} value of \ac{VCPO}, however, imbalances these current sources due to their finite output impedance and an error current flows out of the charge pump.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{grafy/fpd_iout_vout.pdf}
	\vspace{-0.3cm}
	\caption{\acs{RMS} charge pump output current as a function of \acs{VCPO} when UP and DWN signals are both active} \label{fig:fpd_iout_vout}\vspace{-0.4cm}
\end{figure}

The chart shows that in order to minimize this error current, \ac{VCPO} should be kept somewhere in-between \SI{0.5}{\volt} and \SI{0.8}{\volt}, as in this region, both current sources are saturated and their output impedance is at its maximum. This is important for the design of the \ac{V-to-I} converter (which ultimately defines the \ac{VCPO} the \ac{DLL} will settle at) as well as trimming.

\subsection{Voltage to Current converter}
\label{subsec:v-to-i}

The task of this \ac{V-to-I} circuit is to convert the \ac{VCPO} to a current, which is in turn used to bias the \acp{CCDL} and set their propagation delay correctly.

The obvious choice of converting voltage to current is the well-known opamp and resistor circuit shown on \autoref{fig:classic_v2i}. The primary problem of this circuit, the resistor's process variation, is not a critical issue thanks to the \ac{DLL} locking mechanism. As long as the circuit is capable of producing the required current (which is a function of the resistor's resistance, opamp gain, \ac{V-to-I} converter's current mirror mismatch etc), the \ac{VCPO} will adjust to accommodate it. Therefore, the resistor's process variation is transferred to charge pump output variation. As was already discussed in the previous section, though, this is a problem as well, as it is desired to keep \ac{VCPO} reliably in a certain region to maximize charge pump output impedance.

\begin{figure}[htb]
	\centering
	\includegraphics[width=7cm]{obrazky/classic_v2i.pdf}
	\vspace{-0.1cm}
	\caption{Standard \acs{V-to-I} converter} \label{fig:classic_v2i}\vspace{-0.4cm}
\end{figure}

The first important design choice is the choice of the voltage domain. While all the other cells of the \ac{TDC} signal chain have to be designed with thin oxide \SI{1.2}{\volt} devices due to the frequencies they operate at, the operation of the \ac{V-to-I} circuit is fundamentally analog and could potentially benefit from thick oxide \SI{2.5}{\volt} devices with regards to quantities like \ac{PSRR}, current mirror output impedance etc. Furthermore, in the settled state, the circuit should be effectively \ac{DC} and speed is not critical. On the other hand, \SI{1.2}{\volt} devices take up less area and offer faster reactions to voltage or temperature variation as well as faster start-up for a given biasing current. Additionally, keeping everything in a single voltage domain prevents lots of issues with voltage domain separation, guarding (saving even more area), \ac{SOA} violations etc. This is why the \SI{1.2}{\volt} domain was chosen as well for the designed \ac{V-to-I} converter.

Finding a topology suitable for \SI{1.2}{\volt} domain which would pass \ac{PVT} corners, especially with regards to sufficient ($>\SI{50}{\milli\volt}$) saturation margin of each \ac{MOS} device, is not obvious. The classic topology shown on \autoref{fig:classic_v2i} is not suitable, as the voltage across the resistor should be close to $V_\s{DD}/2$ (which is the ideal operating point of the charge pump output) and the $V_\s{GS}$ of the NMOS therefore pushes the opamp output voltage extremely close to $V_\s{DD}$ where it loses gain regardless of the topology.

Driving a PMOS device instead of an NMOS one leads to voltage headroom issues with regards to the topmost PMOS current mirror. Assuming the opamp output voltage is reasonably low (cca 0.25$\times V_\s{DD}$), the source of the PMOS is one $V_\s{GS}$ higher, and the remaining voltage needs to accommodate the PMOS mirror. It has been simulated that this is not feasible due to \ac{PVT} variation.

A suitable topology is depicted on \autoref{fig:dll_v2i}, where the opamp is driving the topmost PMOS mirror directly.

\begin{figure}[htb]
	\centering
	\includegraphics[width=9.5cm]{obrazky/dll_v2i_circuit.pdf}
	\vspace{-0.1cm}
	\caption{Designed \acs{DLL} \acs{V-to-I} converter} \label{fig:dll_v2i}\vspace{-0.4cm}
\end{figure}

The opamp output is a $V_\s{GS}$ below $V_\s{DD}$, which for normal \ac{Vth} thin oxide PMOS devices amounts to roughly middle of the rail. This enables the use of a folded cascode topology, which brings many benefits such as high gain, decent input and output voltage range and output dominant pole stabilization. This is especially beneficial as the opamp drives a lot of PMOS mirror devices, which all contribute with their gate capacitance to the compensation capacitance stabilizing the opamp loop. In order to improve the input voltage range even further, low \ac{Vth} NMOS devices have been used for the input differential pair of the opamp.

In the case of this diploma thesis, only one \ac{ILRO} current branch was implemented in the \ac{V-to-I} converter' current mirror for simplicity. In reality, there would be tens or hundreds of \ac{ILRO} current branches, each supplying biasing current to its \ac{ILRO}. These extra current branches would act as extra opamp output capacitance, as mentioned previously, so in this particular design, the compensation capacitor had to be increased proportionally to stabilize the loop. The capacitance used for stabilizing the loop across \ac{PVT} corners was about \SI{2}{\pico\farad}. Once the full amount of \ac{ILRO} branches would be included, the capacitor's size could be decreased dramatically.

The sizing of the PMOS current mirror devices is very important, as they will be trimmed, which will be discussed in \autoref{subsec:trimming}. The goal was to ensure that the \ac{VGS} of the devices in nominal case is roughly \SI{0.6}{\volt}, so that the opamp output voltage is also around \SI{0.6}{\volt} and its output cascodes are therefore safely in saturation. Mismatch is also a concern and minimum length was therefore not viable -- less than $10\%$ mismatch at $3\upsigma$ was sought after. The $W/L$ size which satisfied both conditions is \SI{9}{\micro\meter}/\SI{0.75}{\micro\meter}. This is a rather wide and short transistor, which is not ideal for a current mirror (matching current mirrors is more area efficient for larger \ac{VGS}), but due to the low voltage supply, such a compromise needs to be made. The actual sizes of the PMOS transistors will be discussed in \autoref{subsec:trimming}.

The resistor which effectively converts the charge pump voltage to current is actually made up of two separate devices. The reason is the optimization of the \ac{TCR}. As was shown on \autoref{fig:const_f0_ibias}, the amount of biasing current necessary to set the \ac{ILRO} free-running frequency to \SI{625}
{\mega\hertz} decreases with temperature at a rate of cca \SI[per-mode=symbol]{-15.4}{\nano\ampere\per\degreeCelsius}. As a constant \ac{VCPO} is desired, this requires the resistor to have a positive \ac{TCR}. An approximation for the desired \ac{TCR} can be calculated as follows. First, the ratio of the ideal resistance value at hot (\SI{135}{\degreeCelsius}) and cold (\SI{-45}{\degreeCelsius}) will be evaluated, utilizing the values of the required current from \autoref{fig:const_f0_ibias}.

\begin{equation}
\frac{R_\s{hot}}{R_\s{cold}}=\frac{V_\s{CPO}}{I_\s{hot}}\cdot\frac{I_\s{cold}}{V_\s{CPO}}=\frac{I_\s{cold}}{I_\s{hot}}=\frac{\SI{17.5}{\micro\ampere}}{\SI{14.8}{\micro\ampere}}\approx 118.2\%
\end{equation}

The result means that the resistor must grow by 18.2\% over the temperature range. The desired \ac{TCR} can be estimated by the following equation.

\begin{equation}
\mathit{TCR}\approx\frac{18.2\%}{\SI{130}{\degreeCelsius}-(\SI{-45}{\degreeCelsius})}\approx\SI{1040}{\ppm\per\kelvin}
\end{equation}

In ONK65, the P+ polysilicon resistor has a \ac{TCR} of \SI{-154}{\ppm\per\kelvin}, while the N diffusion resistor has a \ac{TCR} of \SI{1400}{\ppm\per\kelvin}. The desired \ac{TCR} can be implemented by combining the two resistors in series in a certain ratio $r$, which can be calculated using the following equations.
\begin{gather}
\mathit{TCR}=r\cdot \mathit{TCR}_\s{Ndif} + (1-r)\cdot \mathit{TCR}_\s{Ppoly}\\
r=\frac{\mathit{TCR}-\mathit{TCR}_\s{Ppoly}}{\mathit{TCR}_\s{Ndif}-\mathit{TCR}_\s{Ppoly}}=\frac{1040-(-154)}{1400-(-154)}=0.768
\end{gather}
The value of $r$ was then optimized by simulation to $0.8$ as this ratio seemed to produce more stable \ac{VCPO} when \ac{VDD} variation was taken into account as well.

The total resistance of the combination was calculated as follows
\begin{equation}
R_\s{total}=\frac{V_\s{CPO}}{I_\s{BIAS}}=\frac{\SI{0.6}{\volt}}{\SI{16.22}{\micro\ampere}}=\SI{37}{\kilo\ohm}
\end{equation}

and this value was optimized by simulation to \SI{34}{\kilo\ohm}. The reason for the difference is the previously discussed fundamental discrepancy between the way the \ac{CCDL} is connected in an \ac{ILRO} and in the \ac{DLL}. The \ac{DLL} delay line actually requires more current to produce the desired \SI{800}{\pico\second} delay than the \ac{ILRO} requires to produce the desired \SI{625}{\mega\hertz} oscillations. 

There is a problem that needs to be considered when a combination of two resistors manufactured by different processing steps is utilized -- these resistors are uncorrelated. It is perfectly possible for the P+ polysilicon resistor to skew towards higher resistance, while the N diffusion resistors skews towards lower resistance and vice versa. These \enquote{cross} corners (the resistors skew in opposite directions) will affect the overall \ac{TCR} and it is necessary to validate that the system operates correctly in these corners as well.

The problem with validating these cross corners is that the resistor corner model files only define two corners: hi3s and lo3s, which vary the resistors in the same direction as if they were perfectly correlated. Correct simulation of the uncorrelated variation can be done via Monte Carlo simulations, but because simulating the whole \ac{DLL} is very time intensive and Monte Carlo simulations require hundreds of runs, it is not practical.

Instead, a separate short Monte Carlo simulation was run to determine the variation of these resistors on their own. It was simulated that the P+ polysilicon resistor varies by $5\%/\upsigma$, while the N diffusion resistor varies by $6.7\%/\upsigma$. For $3\upsigma$, this corresponds to $15\%$ and $20\%$ variation respectively.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{grafy/dll_freq_vt_r.pdf}
	\vspace{-0.3cm}
	\caption{Charge pump output voltage stability over temperature for nominal and cross resistor corners} \label{fig:dll_cvo_vt}\vspace{-0.4cm}
\end{figure}

In order to validate the cross corners, the resistors were manually skewed by the aforementioned $15\%$ and $20\%$ in opposite directions, and the resulting value of the \ac{VCPO} is shown on \autoref{fig:dll_cvo_vt}. This simulation considers only VT variation, \ac{MOS} process corners were not applied as \ac{MOS} process variation would skew the mean \ac{VCPO} value heavily and trimming will trim out this static source of variation anyway (as will be discussed in \autoref{subsec:trimming}).

While the mean value of the \ac{VCPO} varies in these cross corners as the total resistance of the series combination changes, this will not be an issue due to trimming (which will be discussed in the following \autoref{subsec:trimming}). The important takeaway here is that thanks to \ac{TCR} compensation, \ac{VCPO} is remarkably stable over temperature even in the cross resistor corners. Furthermore, as these resistors are uncorrelated, skewing both resistors by $3\upsigma$ actually corresponds to much lower probability. In this particular case, since the probability of a skew larger than $3\upsigma$ in either direction is around $0.27\%$, the probability of two such skews happening independently and concurrently is $0.0027^2=0.000729\%$, which actually corresponds to nearly $4.5\upsigma$. The cross corner cases depicted on \autoref{fig:dll_cvo_vt} are therefore overly pessimistic.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{grafy/v2i_psrr.pdf}
	\vspace{-0.3cm}
	\caption{Transconductance from \acs{VDD} to output current of \acs{V-to-I} converter's current mirror} \label{fig:v2i_psrr}\vspace{-0.4cm}
\end{figure}

The \ac{gm} from \acs{VDD} to output current of \acs{V-to-I} converter's current mirror is shown on \autoref{fig:v2i_psrr} (this is similar to \ac{PSRR}, but for an output current quantity and not relative, in this case). The transconductance starts rising once the opamp loop starts loosing its gain and grows to rather large values at high frequencies. The special frequencies of interest are the harmonics of \SI{625}{\mega\hertz}, where the transconductance is obviously far from ideal. The problem is that with only \SI{1.2}{\volt} supply voltage, better power supply rejection is difficult to implement. At hundreds of megahertz, in this processing technology, it is unrealistic to expect that disturbances this fast can be effectively blocked. The designers and layouters should be focused instead on preventing the coupling of high frequency disturbances to sensitive parts of the supply rail in the first place. This can be achieved with proper layout techniques such as increasing distances between noisy and sensitive nodes or by implementing RC low pass filters for the \ac{VDD} on chip to filter both external and internal noise.

A list of scalar quantities related to the designed \ac{V-to-I} converter is shown in \autoref{tab:vtoi_perf}. 

\begin{table}[htb]
\vspace{-0.3cm}
\centering
\caption{\acs{V-to-I} converter performance}
\label{tab:vtoi_perf}
\vspace{-0.25cm}
\begin{tabular}{cccccc}  
\toprule
Analysis & Quantity 	& Min.	& Typ. 	& Max.	& Unit	\\
\midrule
\multirow{2}[0]{*}{PMOS current mirror} & Random mismatch & 	& 2.8	& 	& {\%}/$\upsigma$	\\
& Systematic offset & -4.2	& 0	& 3.3	& \%	\\
\midrule
\multirow{6}[0]{*}{Opamp}& Device area 		& 	& 219 	& 	& \SI{}{\micro\meter\squared}	\\
& Supply current 		& 10.7	& 13.8 	& 17.9	& \SI{}{\micro\ampere}	\\
& Power consumption 		& 11.5	& 16.6 	& 23.6	& \SI{}{\micro\watt}	\\
& Input voltage range 	& 0.25	&  	& 0.95	& \SI{}{\volt}	\\
& Systematic offset		& -2.7	& 0	& 0.75	& \SI{}{\milli\volt}	\\
& Random offset			& 	& 2	& 	& \SI{}{\milli\volt}/$\upsigma$	\\
\midrule
\multirow{4}[0]{*}{Feedback loop} & Open loop gain		& 55.1	& 69.2	& 74.7	& \SI{}{\decibel}	\\
& \acs{GBW}			& 4.2	& 8.9	& 15.7	& \SI{}{\mega\hertz}	\\
& Phase margin		& 60.5	& 82	& 96.8	& \SI{}{\degree}	\\
& Gain margin		& 18.5	& 24.7	& 32.2	& \SI{}{\decibel}	\\
\bottomrule
\end{tabular}
\vspace{-0.15cm}
\end{table}%

The input voltage range of the opamp was defined as the range of input voltages for which the systematic offset does not exceed $\pm$\SI{3}{\milli\volt}. This was set empirically, as outside this range, the systematic offset increases rapidly due to loss of gain.

The offset of the opamp (and therefore the open loop gain as well) is not critical in this application, as the only consequence of it will be the offset of \ac{VCPO}. While \ac{VCPO} should be kept around middle of the rail in order to balance the charge pump current sources, it is not so sensitive that a few millivolts would make any significant difference.

The saturation margins and stability were investigated for extreme input voltages of \SI{0.4}{\volt}, \SI{0.6}{\volt} and \SI{0.8}{\volt}, as well as for extreme trim code combinations (trimming will be discussed in the following \autoref{subsec:trimming}). The results listed in \autoref{tab:vtoi_perf} are therefore overly pessimistic, but still satisfactory, which proves the robustness of the design.

The \ac{GBW} of the feedback loop is important for the settling time, and it should not be slower than the charge pump output -- otherwise, the \ac{DLL} could actually ring for a long time. In this design, there is no ringing of \ac{VCPO}, which will be shown later in \autoref{sec:top_sims}, and if there was, either the charge pump capacitor could be increased or the charge pump current sources could be made to supply less current. This would slow down the charge pump output in relation to the opamp loop, so that it is not the bottleneck any more.

\subsection{Trimming}
\label{subsec:trimming}

As was discussed previously in \autoref{subsec:clock_pll_dll}, trimming is a necessary addition to the system. 

The first reason for this is the inability of the \ac{DLL} to bias the \acp{ILRO} accurately on its own. As was already discussed in previous sections, this is because the delay line in the two circuits, while identical, is connected in a different manner. Furthermore, mismatch between the \ac{DLL} and \ac{ILRO} delay lines, \ac{FPD} non-idealities, mismatch in the \ac{V-to-I} converter current mirror and many other sources of error contribute to the discrepancy. Trimming each \ac{ILRO} individually is necessary to bring their free-running frequencies closer to target \SI{625}{\mega\hertz} so that they can be reliably locked in all conditions. An equally important benefit of the \ac{ILRO} trimming is the reduction of systematic \ac{DNL} error, as was also discussed in \autoref{subsec:clock_pll_dll}.

The second reason is the need for trimming the \ac{DLL} itself. In some process corners, the output of the charge pump could settle to a voltage that is close to the ground or the supply voltage. As was foreshadowed in \autoref{subsec:fpd_cp}, in such cases, the charge pump current sources would be heavily imbalanced and the charge pump would therefore integrate some error current, which would lead to the \ac{DLL} not producing the correct amount of delay in the delay line and therefore the supplied biasing current to the \ac{ILRO} would not be (close to) the current needed to achieve the desired free-running frequency. Furthermore, even if the charge pump were to be ideal and perfectly balanced, a charge pump output voltage too close to the rails could be problematic due to limited \ac{V-to-I} converter input voltage range.

An added benefit of trimming the \ac{DLL} is the prevention of false harmonic locking of the \ac{DLL}. The harmonic locking can occur easily for example when the process variation sets the \ac{V-to-I} converter's resistor's resistance rather high and/or makes the \ac{MOS} transistors (and therefore the delay lines) rather slow. In such a case, the \ac{DLL} could by-default generate smaller than usual biasing current because of the unusually high resistance, and the resulting unusually low current would produce a very long delay in the unusually slow delay line. In such case, it is possible for the \ac{DLL} to settle incorrectly, producing not one clock period worth of delay in the delay line, but two clock period delay instead. Consequently, the biasing current produced by the falsely-locked \ac{DLL} would, when biasing the \acp{ILRO}, produce very slow oscillations. These oscillations would be too slow to enable the \acp{ILRO} to be locked to the target frequency. Trimming the \ac{DLL} itself can prevent this by trimming out this process skew and steering the \ac{DLL} to the desired operating point, i.e. when the charge pump output is roughly in the middle of the supply rails, as was discussed previously in \autoref{subsec:fpd_cp}. During the trimming process correct locking can be verified by also measuring the signals entering the \ac{FPD}, as long as these signals are made accessible to the tester.

Since all the aforementioned problems are caused by fabrication variation (mismatch and process), these errors are static, i.e. they are set at the point of fabrication and should not change significantly over time. Therefore they can be in principle trimmed out and trimming is a valid option.

A decision has been made to trim the circuits in two steps: first, the \ac{DLL} will be trimmed to set the operating point of the charge pump close to the ideal middle of the supply rail. Then the \acp{ILRO} will be trimmed individually to set their \ac{f0} as close to target (\SI{625}{\mega\hertz}) as possible. 

Trimming will be performed in a controlled environment at a specified temperature and with an accurate power supply. In practical applications, the temperature and the supply voltage will vary, but this variance should be compensated by the \ac{DLL} to ensure that the \acp{ILRO} still lock properly, which will be verified by simulation.

The implementation of both trimming steps is shown on \autoref{fig:dll_v2i_trim}.- Both steps are implemented by trimming the PMOS transistors in the \ac{V-to-I} converter's current mirror.

\begin{figure}[htb]
	\centering
	\includegraphics[width=9.5cm]{obrazky/dll_v2i_circuit_trim.pdf}
	\vspace{-0.1cm}
	\caption{Designed \acs{DLL} \acs{V-to-I} converter with trimmed devices highlighted} \label{fig:dll_v2i_trim}\vspace{-0.4cm}
\end{figure}

The \ac{DLL} trimming is done by trimming the width of the PMOS transistor in the resistor branch. By trimming the width of this transistor, the current gain of the mirror from this reference current branch to all the other branches (both the ones supplying current to the \ac{DLL} delay line as well as the numerous branches supplying the \acp{ILRO}) can be adjusted. This can be therefore thought of as a kind of global trimming, as it affects both the \ac{DLL} as well as all the \acp{ILRO}, and therefore it clearly needs to occur first. The goal here is to adjust the width of the trimmed PMOS transistor so that the output voltage of the charge pump settles at \SI{0.6}{\volt}, which is the ideal default operating point of the \ac{DLL}.

This could also be achieved by trimming the \ac{V-to-I} converter's resistors, but that would be a more problematic way to implement this trimming step, as the switches in the resistor trimming network would need to be relatively wide, and since there are two independent resistors which should be weighed in a certain ratio in order to implement target \ac{TCR}, the network would be large and complex. Connecting or disconnecting PMOS units to the opamp output node is a simpler method in comparison. Both trimming methods are non-linear though (both the resistor and the PMOS transistor in the resistor branch are in the denominator of the equation defining the current in the \ac{DLL} or \ac{ILRO} branch).

The individual \ac{ILRO} trimming also occurs in the PMOS current mirror and is also done by trimming the width of the PMOS transistor supplying current to the trimmed \ac{ILRO} instance, but the trimming could have been also done within the \ac{ILRO} cell itself, for example in its NMOS biasing mirror. There are a few reasons why trimming the \ac{ILRO} biasing mirror was not chosen. First of all, the NMOS biasing mirror has sixteen branches, one for each \ac{CCDLU} of the delay line, so trimming each of them would take a lot of area. Trimming the current mirror input diode would be possible, but it would also be non-linear. More importantly, however, this would mean that more routing would need to be connected to each \ac{ILRO}. It is critical that the routing of the clock phases generated by the \acp{ILRO} to the \acp{TDC} is as balanced as possible, and having more routing in this area could complicate it needlessly. Furthermore, more routing next to the \acp{ILRO} would lead to more noise coupled into the \acp{ILRO}, which should be prevented. Therefore the \acp{ILRO} biasing current will be trimmed in the \ac{V-to-I} converter PMOS mirror as well. The goal of this trimming is to individually adjust the width of the PMOS transistors supplying the biasing current to the \acp{ILRO} in order to get the free-running frequency of the unlocked \acp{ILRO} as close to \SI{625}{\mega\hertz} as possible.

A problem with this trimming technique is that the stability of the \ac{V-to-I} opamp feedback loop is now trimming code dependent. This is because when the \ac{DLL} trimming code is high, the width of the PMOS transistor feeding the resistors is increased, therefore its \ac{gm} is high and the loop has higher gain. Higher gain means the loop's \ac{GBW} is higher and its phase margin at the \ac{GBW} frequency can be worse than desired. Widening the PMOS transistor increases the total capacitance connected and therefore slightly decreases the frequency of the dominant pole, but not enough to offset the stability reduced by the higher gain. The loop is also dependent on the \ac{ILRO} trimming codes, as each transistor connected via a switched-on passagate represents an RC load, adding additional pole and zero into the transfer function of the loop.

A solution is to add extra capacitance to \ac{CComp} in proportion to the trimming codes, and therefore the compensation capacitance is also trimmed and made up of binary weighted units. This is represented on \autoref{fig:dll_v2i}. The goal was to make the stability of the loop independent on the code (it is not desirable to overcompensate the loop either), which was successfully achieved as proven by \autoref{tab:vtoi_perf}.

There is a second issue related to \ac{DLL} trimming in particular -- adjusting the width of the PMOS transistor supplying the \ac{V-to-I} converter's resistors also adjusts their \ac{VGS}, as the total current flowing through the PMOS parallel combination is constant. This means that for low trimming codes, the \ac{VGS} can be very high, pushing the output voltage of the opamp low and vice versa. This can make the output cascodes of the opamp step out of saturation. In this particular design, all the opamp devices are kept safely in saturation over all \ac{PVT} corners with a minimum \SI{50}{\milli\volt} margin, but if a wider trimming range was desired, this could be an issue.

In order to not make the layout of the PMOS mirror too complex, it was decided that no more than 5 bits will be used for the trimming. More bits would require splitting the PMOS transistors into a larger number of narrower pieces, which would increase the routing overhead, reduce matching, increase noise coupling etc. Binary weighing the segments is an obvious decision for the aforementioned reasons.

Determining the necessary range of the trimming circuits is not simple, as there are a lot of error sources that need to be trimmed out at once with this trimming and the trimming range should be able to correct all of them once combined. The \ac{DLL} trimming range should primarily cover \ac{MOS} process corners (as they heavily affect the delay lines), \ac{V-to-I} converter resistor variation, \ac{V-to-I} converter PMOS mirror mismatch, the mismatch of the NMOS mirror in the \ac{DLL} delay line, the mismatch of the \acp{CCDLU} inside the \ac{DLL} delay line, \ac{V-to-I} converter opamp offset and \ac{FPD} \& charge pump mismatch. The individual \ac{ILRO} should then trim out the \ac{V-to-I} converter PMOS mirror mismatch as well as the \ac{ILRO} NMOS mirror mismatch and the mismatch of the \acp{CCDLU} themselves (process variation of the delay line is shared by the delay line in the \ac{DLL} and should be theoretically trimmed out by the \ac{DLL} trimming). The trimming range was therefore adjusted by simulation in such a way to ensure that the ideal trimming codes for the nominal corners are roughly in the middle of the range and that the trimming circuits can correct both $3\upsigma$ process and mismatch variation, ideally with a margin of a few codes left to spare.

\begin{figure}[!htb]
	\centering
	\includegraphics[width=11cm]{obrazky/pmos_trim.pdf}
	\vspace{-0.1cm}
	\caption{Trimmed PMOS current mirror devices} \label{fig:pmos_trim}\vspace{-0.4cm}
\end{figure}

Both the \ac{DLL} trimming and \ac{ILRO} trimming PMOS transistors are made from a parallel combination of binary weighted \SI{175}{\nano\meter}/\SI{750}{\nano\meter} units which are either switched to the supply rail or the opamp output node by minimum sized passgates, as shown on \autoref{fig:pmos_trim}.

The number of parallel units connected by each binary weighted bit is listed in \autoref{tab:trim_overview}. It can be seen that the \ac{DLL} trimming PMOS transistor is trimmed more coarsely, as its \ac{LSB} consists of two parallel \SI{175}{\nano\meter}/\SI{750}{\nano\meter} units, while the \ac{ILRO} trimming step is made from a single \SI{175}{\nano\meter}/\SI{750}{\nano\meter} unit. 

\begin{table}[!htb]
\vspace{-0.3cm}
\centering
\caption{Overview of \acs{V-to-I} converter's current mirror trimmed PMOS units}
\label{tab:trim_overview}
\vspace{-0.25cm}
\begin{tabular}{cccccccc}  
\toprule
Current branch 	& $N_\s{0}$ & $N_\s{1}$ & $N_\s{2}$	& $N_\s{3}$ & $N_\s{4}$ & $N_\s{5}$ & Range\\
\midrule
Resistors 		& 32 & 2 & 4	& 8 & 16 & 32 & 32-94\\
\acs{DLL} 		& 32 &  & 	&  &  &  & 62\\
\acs{ILRO} 		& 44 & 1 & 2& 4 & 8 & 16 & 44-75\\
\bottomrule
\end{tabular}
\vspace{-0.15cm}
\end{table}%

This makes sense because \ac{DLL} trimming is global, occurs first, needs to trim out process variation and the trimming does not have to be very precise (as \autoref{fig:fpd_iout_vout} proves, the charge pump operates well in a relatively wide range of \ac{VCPO} voltages). On the other hand, \ac{ILRO} trimming is finer and the target is to trim the \ac{f0} within only a few percent of target frequency.

The reason for that was foreshadowed in \autoref{subsec:ilro_inj_theory} and discussed in \autoref{subsec:clock_pll_dll}. If a perfectly balanced \ac{ILRO} oscillates at \ac{f0}, the propagation delay of each individual cell is exactly

\begin{equation}
t_\s{d,0}=\frac{1}{2N\ac{f0}}
\end{equation}

where $N$ is the number of stages, and when this \ac{ILRO} is locked to $f_\s{inj}\neq \ac{f0}$, the average propagation delay $\overline{t_\s{d}}$ needs to fit the following equation.

\begin{equation}
\overline{t_\s{d}}=\frac{1}{2Nf_\s{inj}}
\end{equation}

In order to accommodate this requirement, the propagation delay of the injection stage adjusts. If there is only one injection stage like in this case, the average propagation delay can be written as follows.

\begin{equation}
\overline{t_\s{d}}=\frac{(N-1)\cdot t_\s{d,0} + t_\s{d,inj}}{N}
\end{equation}

where $t_\s{d,inj}$ is the propagation delay of the injection stage. After rearranging, the following equation can be written for $t_\s{d,inj}$.

\begin{equation}
t_\s{d,inj}=\frac{1}{2f_\s{inj}}-\frac{N-1}{2N\ac{f0}}
\end{equation}

Since in our case both \ac{finj} and $N$ are known, we can plot the relationship between the relative error of \ac{f0} (its ideal value is equal to $f_\s{inj}=\SI{625}{\mega\hertz}$) and $t_\s{d,inj}$ (the ideal value being \SI{50}{\pico\second}), as shown on \autoref{fig:f0_inj_stage_error}.

\begin{figure}[!htb]
	\centering
	\includegraphics[width=14cm]{grafy/f0_inj_stage_error.pdf}
	\vspace{-0.3cm}
	\caption{Error of the injection stage propagation delay as a function of the free-running frequency error} \label{fig:f0_inj_stage_error}\vspace{-0.4cm}
\end{figure}

Since the goal is to keep the \ac{DNL} of the \ac{FTDC} timestamp below $50\%$, \ac{f0} needs to be trimmed within $3\%$ of target. To get some safety margin when the \ac{CCDLU} mismatch is unfavourable or the VT conditions cause the \ac{f0} to skew, it would be better to trim \ac{f0} within $1\%$. On the other hand, this can be difficult to achieve with only 5-bit trimming.

\begin{figure}[!htb]
	\centering
	\begin{minipage}[b][8cm][t]{.495\textwidth}
		\centering
    	\includegraphics[width=0.99\linewidth]{grafy/ilro_trim_hist.pdf}      
    	%\caption{Low \acs{Vth} \acs{CCDLU} chart}\label{fig:ccdlu}
    \end{minipage}   
     \hfill
	\begin{minipage}[b][8cm][t]{.495\textwidth}
		\centering
	    \includegraphics[width=0.99\linewidth]{grafy/ilro_trim_hist_error.pdf}        
	    %\caption{Normal \acs{Vth} \acs{CCDLU} chart}\label{fig:ccdlu_normal}
	\end{minipage}
	\vspace{-0.3cm}
	\caption{\acs{ILRO} trimming trim code and residual error histograms}\label{fig:trim_histograms}
	\vspace{-0.5cm}
\end{figure}

The results of a Monte Carlo simulation simulating the ILRO trimming process on its own (without the \ac{DLL} biasing) are shown on \autoref{fig:trim_histograms}. On the left chart it can be seen that all the trim codes are well within the limits with a trim code standard deviation of $3.9$ codes. The residual \ac{f0} error after trimming is shown on the right. The standard deviation is $0.51\%$, i.e. roughly 95\% ($2\upsigma$) units are within $\pm 1\%$ of \ac{f0} error.

There is no straightforward way to define the specification for \ac{DLL} trimming, so its trimming circuit was designed iteratively based on simulations in order to guarantee that the trimming range is wide enough to ensure that all \ac{PVT} corners could be trimmed successfully. The \acs{DLL} trimming simulations will be shown in the following \autoref{sec:top_sims}.

\section{Top-level simulations}
\label{sec:top_sims}

In this section, a few top level simulations will be shown in order to prove that the designed circuits function properly not only when separated into individual blocks, but also at fully connected top-level.

Because simulating the \ac{DLL} takes a long amount of time (because of the need to simulate picosecond-level time steps along with microsecond-level time spans), Monte Carlo simulations have not been performed on the top-level. Instead, \ac{PVT} corners were utilized. As long as mismatch can be neglected (or is taken into account by separate simulations), this should prove the robustness of the design successfully, as the \ac{PVT} corners are very pessimistic (unlikely) combinations of extreme values.

The start-up of the \ac{DLL} (nominal corner) is depicted on \autoref{fig:dll_wvfs}. 

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{grafy/dll_wvfs.pdf}
	\vspace{-0.3cm}
	\caption{\acs{DLL} start-up waveforms} \label{fig:dll_wvfs}\vspace{-0.4cm}
\end{figure}

At $t=0$, the charge pump voltage \ac{VCPO} is pre-charged to roughly \ac{VDD}/2 (\SI{0.562}{\volt} to be precise) via the circuit shown on \autoref{fig:fpd_cp}. This biases the \ac{DLL} delay line quite close to the ideal point, as the \ac{FPD} input phase shift $t_\s{in}$ shows. The \ac{DLL} then adjusts the input phase shift close to roughly \SI{-1}{\pico\second}. This is not exactly zero due to various \ac{FPD} related errors discussed in \autoref{subsec:fpd_cp}, but its close enough. The free-running frequency of an \ac{ILRO} biased by the current produced by this \ac{DLL} is shown on the lower half of the chart. It stabilizes around \SI{620}{\mega\hertz}, which is close enough to the target frequency to ensure locking (typical locking range was depicted on \autoref{fig:locking_range_design}).

A comparison between \ac{CC} biasing and \ac{DLL} biasing of an \ac{ILRO} is shown on \autoref{fig:dll_vt_f0}. This simulation does not include process variation.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{grafy/dll_vt_f0.pdf}
	\vspace{-0.3cm}
	\caption{\acs{ILRO} free-running frequency over VT variation when biased by a constant current versus a \acs{DLL}} \label{fig:dll_vt_f0}\vspace{-0.4cm}
\end{figure}

The \ac{CC} biasing approximates band gap reference \& P+ polysilicon resistor biasing, which would be a much less complex alternative to the \ac{DLL}. As the chart proves, such biasing would be not only much more temperature sensitive, but \ac{VDD} sensitive as well. This chart therefore justifies the added complexity of the \ac{DLL}, as its operation stabilizes the free-running frequency of the \ac{ILRO} significantly.

A full trimming simulation has been run for \acs{PVT} corners. The simulation plan was as follows:

\begin{enumerate}
	\item Set a \ac{MOS} and resistor process corner, keep \ac{VDD} and temperature nominal
		\begin{itemize}
			\item VT can be kept nominal as trimming in production would be performed in controlled VT conditions
		\end{itemize}
	\item Run a transient simulation for each \ac{DLL} trimming code
		\begin{itemize}
			\item Each transient run has to be long enough for the \ac{DLL} to settle (cca \SI{500}{\nano\second})
		\end{itemize}
	\item Evaluate \ac{VCPO} at the end of each run
	\item Save the \ac{DLL} trim code which minimizes $\vert {V_\s{CPO}-\SI{0.6}{\volt}}\vert$
	\item Run a transient simulation for each \ac{ILRO} trimming code, utilizing the saved \ac{DLL} trim code
	\begin{itemize}
			\item Each transient run has to be long enough for the \ac{ILRO} to settle (cca \SI{500}{\nano\second} as well)
			\item The \ac{ILRO} is free-running in this simulation (injections disabled)
		\end{itemize}
	\item Evaluate \ac{ILRO} instantaneous frequency at the end of each run
	\item Save the \ac{ILRO} trim code which minimizes $\vert \ac{f0}-\SI{625}{\mega\hertz}\vert$
	\item Run a transient simulation of the whole \ac{DLL} + \ac{ILRO} system, utilizing both saved trim codes, for each \ac{VDD} and temperature corner
		\begin{itemize}
			\item VT corners are swept now, because trimming has been completed at this point and this simulation should verify functionality for all possible operating conditions
		\end{itemize}
	\item Evaluate instantaneous frequency of the \ac{ILRO} and verify it locks, evaluate propagation delay between each \ac{ILRO} stage
	\item Repeat for all process corners
\end{enumerate}

The \ac{DLL} trimming sweeps are shown on \autoref{fig:dll_sweep}. All corners are trimmed within \SI{8}{\milli\volt} of target. While the span of the trim codes is rather wide (from code 5 to code 29), it has to be acknowledged once again that these process corners are quite pessimistic and each line actually represents a combined $4.5\upsigma$ corner. 

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{grafy/dll_trim_sweep.pdf}
	\vspace{-0.3cm}
	\caption{\acs{DLL} trim code sweep across process corners} \label{fig:dll_sweep}\vspace{-0.4cm}
\end{figure}

Nevertheless, it is possible that the \ac{DLL} trimming range could be insufficient once mismatch of the \ac{DLL} delay line is considered. A mismatch-only Monte Carlo simulation has been run to identify what range of biasing currents is necessary to keep the propagation delay through the whole delay line equal to \SI{800}{\pico\second}, which is what the \ac{DLL} feedback tries to achieve. It has been evaluated that the current can vary by up to $6.5\%/\upsigma$ to satisfy this condition. For $3\upsigma$ (i.e. $20\%$) biasing current variation, the trimming code of the \ac{DLL} trimming circuit has to change by up to 8 codes (this can be calculated based on the ratios of trimmed PMOS units from \autoref{tab:trim_overview}). 

If the process corners can require codes as high as 29 and mismatch can require up to 8 codes to compensate, it is definitely possible for a process \& mismatch combination to be so skewed that the \ac{DLL} trimming circuit's trimming range could be insufficient to bring \ac{VCPO} close enough to target value. Increasing the \ac{DLL} trimming circuit's range has been attempted, but this led to problems with the opamp operating point, which is an issue discussed in the previous \autoref{subsec:trimming}. Solving this would probably require \SI{2.5}{\volt} supply voltage domain for the \ac{V-to-I} converter, as it is essentially a voltage headroom problem, which depending on the project specifications might or might not be possible.

It has to be noted once more, however, that the probability of a $4.5\upsigma$ process corner along with $3\upsigma$ delay line mismatch is very low and is definitely much lower than the inverse of yield of the manufacturing process itself, which is usually around 90\% for mature processes, so it is not a critical issue which would require a redesign automatically.

\begin{figure}[!htb]
	\centering
	\includegraphics[width=14cm]{grafy/ilro_trim.pdf}
	\vspace{-0.3cm}
	\caption{\acs{ILRO} trim code sweep across process corners} \label{fig:ilro_sweep}\vspace{-0.4cm}
\end{figure}

The \ac{ILRO} trimming sweeps are shown on \autoref{fig:ilro_sweep}. The span of required codes over process corners is much narrower and when combined with the span of codes required to compensate mismatch, as simulated on \autoref{fig:trim_histograms}, there should be no problems trimming the \ac{ILRO}. The worst case residual \ac{f0} error in this simulation is \SI{5.1}{\mega\hertz}.

Two corners from \autoref{fig:ilro_sweep} stand out, however -- they are less linear and require lower trim codes than the rest. These are the slow \ac{MOS} corners. This process corner has been highlighted on \autoref{fig:ilro_f_vs_ibias} and its curvature is related to the fact that the \ac{CCDLU} transistor devices could not have been kept minimum sized because of mismatch requirements. This is a compromise that needed to be made in order to meet the \SI{50}{\pico\second} specification as well as realistically possible in the given processing technology.

The instantaneous frequency of trimmed \acp{ILRO} over selected \ac{PVT} corners is shown on \autoref{fig:locking_wvfs_trim}. In this simulation, the \acp{ILRO} are left free-running until $t=\SI{0.3}{\micro\second}$, when injections start. It can be seen right away that a single corner does not lock at all and shows a typical periodic frequency pattern which occurs in such cases.

\afterpage{
\begin{landscape}
\begin{figure}[p]
\begin{center}
\vspace{-1cm}
\captionsetup{type=figure} 
    \includegraphics[width=22.15cm]{grafy/locking_wvfs_trim.pdf}
    \captionof{figure}{Instantaneous frequency of \acs{ILRO} across selected \acs{PVT} corners during locking after trimming}
    \label{fig:locking_wvfs_trim}
\end{center}
\end{figure}
\end{landscape}
%\clearpage}

%\afterpage{
\begin{figure}[p!]
\centering
	\includegraphics[width=14cm]{grafy/trim_sim_corners.pdf}
	\vspace{-0.3cm}
	\caption{\acs{PVT} corner overview of free-running trimmed \acs{ILRO} biased by a trimmed \acs{DLL}} \label{fig:trim_corners}\vspace{-0.4cm}
\end{figure}
\clearpage}

This problem was analysed further. The charts on \autoref{fig:trim_corners} show a \acs{PVT} corner overview of a simulation, where a trimmed \ac{ILRO} biased by a trimmed \ac{DLL} is free-running. It is essentially the same simulation as before, but without injections. This allows us to inspect the free-running frequency \ac{f0} better. The top chart focuses on the \ac{ILRO}, while the other three charts focus on the operation of the \ac{DLL} itself.

As \autoref{fig:trim_corners} shows, nominal, FF and FS corners operate very well, as the \ac{f0} is close to target, so is \ac{VCPO}, the biasing currents are within expected range and the input phase shift seen by the \ac{FPD} is close to zero. The situation is slightly worse for SF corners, but not by much. The problems are however clearly visible for SS corners. The \ac{f0} spreads widely, \ac{VCPO} can be off target by up to \SI{0.3}{\volt}, the biasing currents produced by the \ac{DLL} can be very large and the \ac{FPD} input phase shift is not close to zero any more for some SS corners.

There are actually two different groups of problem SS corners, denoted SSa and SSb and shown on \autoref{fig:trim_corners} with a different mark shape. The group SSa are corners where the \ac{DLL} itself does not operate properly. It appears that the \ac{DLL} delay line in these corners requires a lot of current to produce the desired delay, which causes the feedback to increase \ac{VCPO} significantly. This, in turn, squeezes the voltage headroom of the upper charge pump current source, which produces a mismatch between the upper and lower charge pump current sources, causing the loop to correct it with non-zero \ac{FPD} input phase shift, which can be as much as \SI{25}{\pico\second}. This means that the delay produced by the \ac{DLL} delay line is not very close to \SI{800}{\pico\second} any more, which worsens the \ac{VT} tracking capability of the \ac{DLL}, causing the \ac{f0} to skew away from \SI{625}{\mega\hertz}. These corners are able to lock to \SI{625}{\mega\hertz} nevertheless.

The reason for why these corners require so much current is shown on \autoref{fig:ilro_f_vs_ibias}, as these are the slow corners for which the $\ac{f0}=f(I_\s{BIAS})$ function is flatter than usual, requiring a wider range of currents to meet the target \ac{f0}. The flatness of these corners is caused by the increased size of the \ac{CCDLU} transistors, which was required in order to lower the mismatch so as to meet the \ac{DNL} criteria. Fixing this corner would therefore lead to a different, statistically more likely issue.

The corner group SSb is the more problematic one. As the lower three charts show, the \ac{DLL} operates perfectly fine in these three corners and none of the three lower charts suggest there should be any issue at all. However, the \ac{f0} of the \ac{ILRO} in these corners is so low that it is outside the locking range and these corners are not able to lock to \SI{625}{\mega\hertz}. The explanation is that the fundamental discrepancy between the \ac{DLL} and \ac{ILRO} is exacerbated in these corners, preventing a perfectly functioning \ac{DLL} from biasing \ac{ILRO} correctly.

Another point of view on the situation is shown on \autoref{fig:trim_corners_vdda}. This compares the sensitivity of \ac{f0} to \ac{VDD} for SS corners versus all the other corners.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{grafy/trim_sim_slow_corners_vdd.pdf}
	\vspace{-0.3cm}
	\caption{Free-running frequency of trimmed \acs{ILRO} biased by a trimmed \acs{DLL} as a function of \acs{VDD}} \label{fig:trim_corners_vdda}\vspace{-0.4cm}
\end{figure}

It can be seen that while in all the other corners the \ac{DLL} is able to compensate the effect of \ac{VDD} very well, stabilizing the \ac{f0}, the situation is different for SS corners, which are much more sensitive. When \ac{VDD} skews high, the \ac{f0} decreases. In these slow \ac{MOS} corners, the \ac{gm} of the transistors is low and/or their \ac{Vth} is high. When \ac{VDD} is high, output capacitance of the \ac{CCDLU} stage have to charge up to a higher voltage in order to trigger the following buffer stage, which occurs more slowly. A possible solution would be to counteract this by increasing the $W/L$ ratio of the transistors, but this would increase the parasitic capacitances and slow down the delay line, requiring more biasing current for a given oscillation frequency. As was discussed in \autoref{subsec:ccdlu_design} and also a few paragraphs earlier, increasing the size of the transistors in the \ac{CCDLU} also flattens the $\ac{f0}=f(I_\s{BIAS})$ function of the slow corners, which would exacerbate the issue seen in the corner group SSa. None of these problems were seen when minimum sized transistors were used in a test-version of the \ac{CCDLU}, but due to \ac{DNL} specifications, this is not a viable option. In this processing technology, it appears that possibilities for further improvement of this particular architecture are very limited. A completely different way to approach the \ac{ILRO} biasing scheme might solve the issue, though, and it will be briefly discussed in \autoref{sec:lessons}. 

That being said, all corners but the SSb group are able to lock to \SI{625}{\mega\hertz} correctly anyway. As was discussed previously, this would not affect the yield enough to be a serious issue requiring a complete redesign, as the probability of such variation is significantly lower than the inverse of the yield of the manufacturing process itself (cca 90\%). It is however something that would have to be kept in mind in future designs.

With regards to the propagation delay distribution across the 16 \ac{ILRO} stages, the delays range from \SI{44.4}{\pico\second} to \SI{103.3}{\pico\second} for the stages adjacent to the injection point and from \SI{48.2}{\pico\second} to \SI{52.1}{\pico\second} for the remaining stages. Only 2 out of 33 corners exceed \SI{75}{\pico\second} though, and these outlier corners are the slowest ones from corner group SSb mentioned above. These results are expected and apart from the two overly slow \ac{f0} corners, the propagation delay is within bounds.

The final simulation which will be discussed in this thesis is a transient noise simulation analysing the jitter of an unlocked and locked \ac{ILRO}. To be specific, transient noise modelling was enabled and the clock jitter was measured at the buffered output of the last stage, which performs the worst due to jitter accumulation (as discussed in \autoref{subsec:phase_noise_model}). The histogram of jitter is shown on \autoref{fig:jitter_hist}. The standard deviation of unlocked \ac{ILRO} jitter is \SI{1.94}{\pico\second}, while the standard deviation of a locked \ac{ILRO} jitter is \SI{0.82}{\pico\second}. This is basically an alternative way of looking at the spectral purity of the oscillator, proving the theory discussed in \autoref{subsec:paradox_pnoise} and the validity of the \textsc{Matlab} model output shown on \autoref{fig:psd}. In other words, injection locking significantly improves the phase noise of an oscillator and reduces the clock jitter by half on average.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{grafy/jitter_hist.pdf}
	\vspace{-0.3cm}
	\caption{Jitter histogram of a locked and unlocked \acs{ILRO}} \label{fig:jitter_hist}\vspace{-0.4cm}
\end{figure}

Further simulations would need to be run post layout on schematics including extracted parasitics, possibly with Spectre RF or equivalent high-frequency oriented simulators in order to analyse the phase noise performance of the \acp{ILRO} properly. Because of the speed of the designed circuits and the required small time resolution, the circuits will be very sensitive to parasitics and optimizations to the design post-layout are to be expected. For the purposes this thesis, however, layout and post-layout simulations are not a part of the assignment.

\section{Alternative solutions}
\label{sec:lessons}

During the design, a few ideas about alternative solutions to the encountered problems were discovered and they will be listed in this short section.

One of the problems of the designed system which was mentioned numerous times is the inherent problem in \ac{DLL} based \ac{ILRO} biasing, which is caused by the discrepancy between the connection of a delay line as a pass-through delay element and as a ring oscillator. This issue can contribute to the unsatisfactory \ac{DLL} biasing performance seen in some \ac{PVT} corners discussed in the previous \autoref{sec:top_sims}.

An obvious solution to this problem is \ac{PLL}-based biasing, as shown on \autoref{fig:pll_ilro}, where all delay lines are connected as ring oscillators.

\begin{figure}[htb]
	\centering
	\includegraphics[width=14cm]{obrazky/pll_ilro.pdf}
	\vspace{-0.1cm}
	\caption{\acs{PLL} based \acs{ILRO} biasing} \label{fig:pll_ilro}\vspace{-0.3cm}
\end{figure}

The \ac{PLL} based approach has some shortcomings though. First of all, \ac{PLL} design in general is much more difficult. This is primarily because \acp{PLL} are not conditionally stable unlike \acp{DLL}. While a \ac{DLL} has a single pole at zero frequency due to the integration action at the charge pump output, a \ac{PLL} actually integrates twice, because when a phase detector is utilized to control \ac{VCO} frequency, it means that its frequency is integrated (because phase is a time integral of frequency).

This means that the whole stabilization scheme has to be much more robust, commonly requiring second or third order passive filters. The issue is not only the design complexity, but also the area: the sizes of capacitances required by \ac{PLL} compensation circuits are significantly higher (tenfold or even more). Because of the need to not spend area needlessly, even compensated \ac{PLL} settling waveforms often overshoot and ring for a comparatively long time, lengthening settling time and prolonging start-up.

On the other hand, it is expected that the \ac{PLL} will bias \acp{ILRO} more accurately over \ac{PVT} conditions, as the connection of a ring oscillator within the \ac{PLL} and within the \ac{ILRO} blocks is absolutely identical. This would likely help to prevent the issues seen in some corners which were discussed in the previous \autoref{sec:top_sims}. Using a \ac{PLL} to bias \ac{ILRO} is a legitimate technique, but as always, its benefits and disadvantages need to be weighed carefully with regards to the particular project specifications.

The second area of design where an alternative approach could have been taken is the interface between the charge pump and the \ac{V-to-I} converter. As was discussed previously, due to limited output impedance of the charge pump (caused by voltage headroom issues in the \SI{1.2}{\volt} supply domain), it is important to keep \ac{VCPO} close to the middle of the supply rail to keep both charge pump current sources well within the saturation region. In the design, this was accounted for by trimming. Trimming is, however, a costly operation which takes time during testing, requires measuring equipment etc, so if there are any alternatives, they should be explored.

\begin{figure}[htb]
	\centering
	\includegraphics[width=9cm]{obrazky/dll_adc_trim.pdf}
	\vspace{-0.1cm}
	\caption{Alternative dynamic \acs{ADC}-based \acs{DLL} trimming method} \label{fig:dll_adc_trim}\vspace{-0.3cm}
\end{figure}

Two alternative methods will be proposed. The first method is shown on \autoref{fig:dll_adc_trim}. This proposal takes advantage of the fact that the target \ac{VCPO} does not have to be very precise and that its value is roughly $\ac{VDD}/2$, which can be easily made on-chip. A 5-bit \ac{ADC} can be designed to trim \ac{VCPO} dynamically across all operating conditions. The added complexity of an \ac{ADC} can outweigh the costs of the trimming operation while also bringing the benefit of preventing \ac{VCPO} skewing away from target in some specific conditions.

On the other hand, this is an additional feedback loop implemented inside another feedback loop and such a circuit needs to be approached carefully. The \ac{ADC} does not have to be very precise or fast, but it has to be strictly monotonic. Furthermore, it should not compromise the signal integrity of the nearby circuits because of switching noise coupling etc.

The circuit could also be designed in such a way that the resistor is trimmed instead of the PMOS transistor. This is because when this dynamic trimming is employed, the \ac{TCR} of the resistor is not important any more and this could have an added benefit of keeping the output voltage of the opamp stable across trim codes. It might not be as area efficient, though.

\begin{figure}[htb]
	\centering
	\includegraphics[width=9cm]{obrazky/dll_dynR_trim.pdf}
	\vspace{-0.1cm}
	\caption{Alternative dynamic \acs{VCR}-based \acs{VCPO} stabilizing method} \label{fig:dll_dynR_trim}\vspace{-0.3cm}
\end{figure}

An alternative solution to the same problem is depicted on \autoref{fig:dll_dynR_trim}. In this proposal, the resistor is replaced by a \ac{VCR} (implemented with \ac{MOS} transistors). The \ac{VCR} is controlled by an opamp feedback loop in such a way to ensure that \ac{VCPO} is stabilized around $\ac{VDD}/2$. This is probably a more difficult solution to stabilize, as it is a fully analog feedback loop, but it could be the most area efficient method as well as simpler than designing an \ac{ADC}.
