---------------------------------------------------------------------------
-- File           : ea_pattern_gen.vhd
-- Author(s)      : Nikola Avramovic
-- Created        : March 11th, 2019
---------------------------------------------------------------------------
-- Description    : Generator pattern top
---------------------------------------------------------------------------

---------------------------------------------------------------------------
library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;
   use work.p_interfaces.all;
   --use work.p_addresses.all;
   use work.p_generator_interface.all;
   use work.p_patt_gen_interface.all;

entity ea_pattern_gen is
   generic(
      G_PATTERN_GEN_NO : natural  := 0
   );
   port  (
      clk              : in  std_logic;
      reset            : in  std_logic;
      -- to/from input command module
      cmd_decoderi     : in  TYPE_CMD_DECODER_TO_PATTERN_GEN;
      cmd_decodero     : out TYPE_PATTERN_GEN_TO_CMD_DECODER;
      -- to/from port generator
      port_geno        : out TYPE_AVALON_ST_SOURCE_TO_SINK;
      port_geni        : in  TYPE_AVALON_ST_SINK_TO_SOURCE;
      -- status interface
      statuso          : out  TYPE_PATTERN_GEN_TO_STATUS
   );
end entity ea_pattern_gen;

architecture rtl of ea_pattern_gen is

   -- intercontect signals
   signal lfsr_to_control_patt    : TYPE_LFSR_TO_CTRL_PATTERN;
   signal control_patt_to_lfsr    : TYPE_CTRL_PATTERN_TO_LFSR;
   signal linear_to_control_patt  : TYPE_LINEAR_TO_CTRL_PATTERN;
   signal control_patt_to_linear  : TYPE_CTRL_PATTERN_TO_LINEAR;
   signal patt_mux_to_control_patt: TYPE_PATTERN_MUX_TO_CTRL_PATTERN;
   signal control_patt_to_patt_mux: TYPE_CTRL_PATTERN_TO_PATTERN_MUX;
   signal fifo_avalon_to_lfsr     : TYPE_FIFO_AVALON_TO_LFSR;
   signal lfsr_to_patt_mux        : TYPE_LFSR_GEN_TO_PATTERN_MUX;
   signal fifo_avalon_to_linear   : TYPE_FIFO_AVALON_TO_LINEAR;
   signal linear_to_patt_mux      : TYPE_LINEAR_GEN_TO_PATTERN_MUX;
   signal patt_mux_to_fifo_avalon : TYPE_PATT_MUX_TO_FIFO_AVALON;
begin

   -- random generator
   lfsr_gen_i : entity work.ea_lfsr_gen
   port map (
      clk              => clk,
      reset            => reset,
      control_patti    => control_patt_to_lfsr,
      control_patto    => lfsr_to_control_patt,
      fifo_avaloni     => fifo_avalon_to_lfsr,
      patt_muxo        => lfsr_to_patt_mux
   );

   -- non random generator
   linear_gen_i: entity work.ea_linear_gen 
   port map ( 
      clk              => clk,
      reset            => reset,
      control_patti    => control_patt_to_linear,
      control_patto    => linear_to_control_patt,
      fifo_avaloni     => fifo_avalon_to_linear,
      patt_muxo        => linear_to_patt_mux
   );

   -- control pattern
   ctrl_patt_i: entity work.ea_control_patt_gen
   generic map (
      G_PATTERN_GEN_NO   => G_PATTERN_GEN_NO
   ) port map (
      clk              => clk,
      reset            => reset,
      cmd_decoderi     => cmd_decoderi,
      cmd_decodero     => cmd_decodero,
      lfsri            => lfsr_to_control_patt,
      lfsro            => control_patt_to_lfsr,
      lineari          => linear_to_control_patt,
      linearo          => control_patt_to_linear,
      patt_muxi        => patt_mux_to_control_patt,
      patt_muxo        => control_patt_to_patt_mux,
      statuso          => statuso
   );

   pattern_mux_i: entity work.ea_patt_gen_mux
   port map ( 
      clk              => clk,
      reset            => reset,
      control_patti    => control_patt_to_patt_mux,
      control_patto    => patt_mux_to_control_patt,
      lfsri            => lfsr_to_patt_mux,
      lineari          => linear_to_patt_mux,
      fifo_avalon_sto  => patt_mux_to_fifo_avalon
   );
   
   avalon_fifo_i: entity work.ea_fifo_avalon_st 
   port map (
      clk              => clk,
      reset            => reset,
      patt_muxi        => patt_mux_to_fifo_avalon,
      lfsro            => fifo_avalon_to_lfsr,
      linearo          => fifo_avalon_to_linear,
      port_geni        => port_geni,
      port_geno        => port_geno
   );

end architecture rtl;