---------------------------------------------------------------------------
-- File           : ea_top_generator.vhd
-- Author(s)      : Nikola Avramovic
-- Created        : March 11th, 2019
---------------------------------------------------------------------------
-- Description    : Generator object top module
---------------------------------------------------------------------------

---------------------------------------------------------------------------
library ieee, work;
   use ieee.std_logic_1164.all;
   use work.p_parameters_and_constants.all;
   use work.p_interfaces.all;
   use work.p_addresses.all;
   use work.p_generator_interface.all;

entity ea_top_generator is
   generic (
      G_NO_OF_PATT_GEN    : natural  := 2;
      G_PORT_GEN_NO       : natural  := 1
   );
   port  (
      clk                 : in  std_logic;
      reset               : in  std_logic;
      -- to/from NIOS II processor
      masteri             : in  TYPE_AVALON_MM_MASTER_TO_SLAVE;
      mastero             : out TYPE_AVALON_MM_SLAVE_TO_MASTER;
      -- to/from device under test
      duti                : in  TYPE_AVALON_ST_SINK_TO_SOURCE;
      duto                : out TYPE_AVALON_ST_SOURCE_TO_SINK
   );
end entity ea_top_generator;

architecture rtl of ea_top_generator is
   
   -- to/from avalon mm interface
   signal pattern_gen_to_cmd_decoder : TYPE_PATTERN_GEN_TO_CMD_DECODER_ARRAY(G_NO_OF_PATT_GEN downto 1);
   signal cmd_decoder_to_pattern_gen : TYPE_CMD_DECODER_TO_PATTERN_GEN_ARRAY(G_NO_OF_PATT_GEN downto 1);
   signal port_gen_to_cmd_decoder    : TYPE_PORT_GEN_TO_CMD_DECODER;
   signal cmd_decoder_to_port_gen    : TYPE_CMD_DECODER_TO_PORT_GEN;
   -- to/from pattern generator
   signal pattern_gen_to_port_gen    : TYPE_AVALON_ST_SOURCE_TO_SINK_ARRAY(G_NO_OF_PATT_GEN downto 1);
   signal port_gen_to_pattern_gen    : TYPE_AVALON_ST_SINK_TO_SOURCE_ARRAY(G_NO_OF_PATT_GEN downto 1);
   -- status signals
   signal pattern_gen_to_status      : TYPE_PATTERN_GEN_TO_STATUS_ARRAY(G_NO_OF_PATT_GEN downto 1);
   signal port_gen_to_status         : TYPE_PORT_GEN_TO_STATUS;
begin
   
   ----------------------------------------------------------------
   -- Avalon memory map interface is used for storing data into FIFO,
   -- decode cmd, and send into proper module (pattern generators, port generator)
   -- and to store errors which occured inside of moduls 
   -- (pattern generators, port generator, FIFO, command decoder)
   ----------------------------------------------------------------
   input_gen_i: entity work.ea_avalon_mm_interface_gen
      generic map (
         G_NO_OF_PATT_GEN  => G_NO_OF_PATT_GEN
      ) port map (
         clk               => clk,
         reset             => reset,
         masteri           => masteri,
         mastero           => mastero,
         pattern_geni      => pattern_gen_to_cmd_decoder,
         pattern_geno      => cmd_decoder_to_pattern_gen,
         port_geni         => port_gen_to_cmd_decoder,
         port_geno         => cmd_decoder_to_port_gen,
         pattern_statusi   => pattern_gen_to_status,
         port_statusi      => port_gen_to_status
      );

   ----------------------------------------------------------------
   -- Pattern generators
   ----------------------------------------------------------------
   g: for i in 1 to G_NO_OF_PATT_GEN generate
   begin
      pattern_gen_i: entity work.ea_pattern_gen
         generic map (
            G_PATTERN_GEN_NO   => i
         ) port map (
            clk                => clk,
            reset              => reset,
            cmd_decoderi       => cmd_decoder_to_pattern_gen(i),
            cmd_decodero       => pattern_gen_to_cmd_decoder(i),
            port_geni          => port_gen_to_pattern_gen(i),
            port_geno          => pattern_gen_to_port_gen(i),
            statuso            => pattern_gen_to_status(i)
         );
   end generate;

   ----------------------------------------------------------------
   -- Port generator
   ----------------------------------------------------------------
   port_gen_i: entity work.ea_port_gen
      generic map (
         G_NO_OF_PATT_GEN  => G_NO_OF_PATT_GEN,
         G_PORT_GEN_NO     => G_PORT_GEN_NO
      ) port map (
         clk               => clk,
         reset             => reset,
         cmd_decoderi      => cmd_decoder_to_port_gen,
         cmd_decodero      => port_gen_to_cmd_decoder,
         pattern_geni      => pattern_gen_to_port_gen,
         pattern_geno      => port_gen_to_pattern_gen,
         duti              => duti,
         duto              => duto,
         statuso           => port_gen_to_status
      );
   
end architecture rtl;       



