:: -------------------------------------------------------------------------
::  Copyright (c) 2013, TTTech Computertechnik AG
::  Project        : zFAS
:: -------------------------------------------------------------------------
::  File           : setup_env.bat
::  Author(s)      : Petr Kobiersky
::  Created        : October 9th, 2013
:: -------------------------------------------------------------------------
::  Description    : Windows Project Setup File
:: 
:: -------------------------------------------------------------------------
::  $Id: setup_env.bat 63604 2014-01-26 20:48:14Z kobiersky $
:: -------------------------------------------------------------------------

@echo off
:: ------------------------------------------------------------------------
::                                Project Name
echo ----------------------------------------------------------------------
echo TTSL Protocol Aware hardware test
echo ----------------------------------------------------------------------
:: ------------------------------------------------------------------------


:: ------------------------------------------------------------------------
::                                Tool Setup
echo Performing CAD tools initialization...
:: ------------------------------------------------------------------------
:: Select Altera Version
set PATH=C:\intelFPGA\18.0\sopc_builder\bin;%PATH%
set PATH=C:\intelFPGA\18.0\bin64;%PATH%
:: Select ModelSim Version
:: modelsim_pe is 32 bite version, sometimes it has problem with memory
::set PATH=C:\Modeltech_pe_edu_10.4a\win32pe_edu;%PATH%
:: modelsim_10.5e is 64 bite verison, it has problem with licence
set PATH=C:\modelsim\modeltech64_10.5e\win64;%PATH%

:: Required for sim_review script (script prints vhdl 
:: files to ps and then convert to pdf)
:: http://www.ghostscript.com/download/gsdnld.html
:: http://gnuwin32.sourceforge.net/packages/a2ps.htm
set PATH=C:\Program Files (x86)\A2PS\bin;%PATH%
set PATH=C:\Program Files\gs\gs9.05\bin;%PATH%
set PATH=C:\Python27;%PATH%
:: ------------------------------------------------------------------------
::                 Generate Altera Simulation Libraries 
:: ------------------------------------------------------------------------
::IF NOT EXIST altera_libs (
::echo Generating Altera Simulation Libraries...
::quartus_sh --simlib_comp -tool modelsim -language vhdl -directory . -rtl_only
::quartus_sh --simlib_comp -tool modelsim -language vhdl -family cyclonev -directory . -no_rtl
::del transcript
::del modelsim.ini
::rename vhdl_libs altera_libs
::)

:: Setup environment variables for CAD tools used on the project. Setting
:: of the tools is work station dependent.
:: Specify path to project modelsim.ini file
set MODELSIM=%CD%\scripts\modelsim.ini
 
:: ------------------------------------------------------------------------
::                            TTSL Library Setup
echo Performing TTTech Script Library initialization...
:: ------------------------------------------------------------------------
:: Setup the environment variables needed by TTSL library.
set WORK=%CD%\verification
set TTSLPATH=%WORK%\scripts\_ext_ttsl
set TTSLINIPATH=%WORK%\scripts\
set PATH=%TTSLPATH%\bin;%PATH%;
set PYTHONPATH=%TTSLPATH%\lib

:: ------------------------------------------------------------------------
::                            TB and DUT Version
:: ------------------------------------------------------------------------
get_svn_id.py -d design  > design_ver
get_svn_id.py -d impl > impl_ver
get_svn_id.py -d . > tp_ver
set /p DESIGN_REV=< design_ver
set /p IMPL_REV=< impl_ver
set /p TTSL_VER_REV=< tp_ver
set    TTSL_DUT_REV=%DESIGN_REV%;%IMPL_REV%
del design_ver
del impl_ver
del tp_ver
echo    DESIGN Source Code Version:
echo    %DESIGN_REV%
echo    DESIGN Implementation Version:
echo    %IMPL_REV%
echo    VERIFICATION Testbench and Test Procedures Version:
echo    %TTSL_VER_REV%

:: ------------------------------------------------------------------------
::                       Generate Design Packages
:: ------------------------------------------------------------------------
::cd %WORK%\dut\design\src
::vsim -c -do "source common/create_svn_revision_package.tcl; quit;" 1>NUL
::cd %WORK%
