---------------------------------------------------------------------------
-- File           : ea_port_gen.vhd
-- Author(s)      : Nikola Avramovic
-- Created        : March 11th, 2019
---------------------------------------------------------------------------
-- Description    :  Port generator top module
---------------------------------------------------------------------------

---------------------------------------------------------------------------
library ieee, work;
   use ieee.std_logic_1164.all;
   use work.p_interfaces.all;
   use work.p_addresses.all;
   use work.p_generator_interface.all;
   use work.p_port_gen_interface.all;

entity ea_port_gen is
   generic(
      G_NO_OF_PATT_GEN: natural;
      G_PORT_GEN_NO   : natural
      );
   port (
      clk             : in  std_logic;
      reset           : in  std_logic;
      -- to/from input control module
      cmd_decoderi    : in  TYPE_CMD_DECODER_TO_PORT_GEN;
      cmd_decodero    : out TYPE_PORT_GEN_TO_CMD_DECODER;
      -- to/from pattern generator
      pattern_geni    : in  TYPE_AVALON_ST_SOURCE_TO_SINK_ARRAY(G_NO_OF_PATT_GEN downto 1);
      pattern_geno    : out TYPE_AVALON_ST_SINK_TO_SOURCE_ARRAY(G_NO_OF_PATT_GEN downto 1);
      -- to/from device under test
      duto            : out TYPE_AVALON_ST_SOURCE_TO_SINK;
      duti            : in  TYPE_AVALON_ST_SINK_TO_SOURCE;
      -- status interface
      statuso         : out  TYPE_PORT_GEN_TO_STATUS
   );
end entity ea_port_gen;

architecture rtl of ea_port_gen is

   -- intercontect signals
   ----------------------------------------------------------------
   signal input_mux_to_control_port  : TYPE_INPUT_MUX_TO_CONTROL_PORT;
   signal control_port_to_input_mux  : TYPE_CONTROL_PORT_TO_INPUT_MUX;
   signal input_mux_to_eth_output    : TYPE_INPUT_MUX_TO_ETH_OUTPUT;
   signal eth_output_to_input_mux    : TYPE_ETH_OUTPUT_TO_INPUT_MUX;
   signal control_port_to_eth_output : TYPE_CONTROL_PORT_TO_ETH_OUTPUT;
   signal eth_output_to_control_port : TYPE_ETH_OUTPUT_TO_CONTROL_PORT;

begin
   
   ----------------------------------------------------------------
   -- 
   ----------------------------------------------------------------

   control_port_i: entity work.ea_control_port
   generic map (
      G_PORT_GEN_NO    => G_PORT_GEN_NO
   ) port map (
      clk              => clk,
      reset            => reset,
      cmd_decoderi     => cmd_decoderi,
      cmd_decodero     => cmd_decodero,
      input_muxi       => input_mux_to_control_port,
      input_muxo       => control_port_to_input_mux,
      eth_outputi      => eth_output_to_control_port,
      eth_outputo      => control_port_to_eth_output,
      statuso          => statuso
   );

   input_mux_i: entity work.ea_input_mux
   generic map (
      G_NO_OF_PATT_GEN => G_NO_OF_PATT_GEN
   ) port map (
      clk              => clk,
      reset            => reset,
      patt_geni        => pattern_geni,
      patt_geno        => pattern_geno,
      control_porti    => control_port_to_input_mux,
      control_porto    => input_mux_to_control_port,
      eth_outputi      => eth_output_to_input_mux,
      eth_outputo      => input_mux_to_eth_output
   );

   eth_output_i:entity work.ea_ethernet_output
   port map (
      clk              => clk,
      reset            => reset,
      control_porti    => control_port_to_eth_output,
      control_porto    => eth_output_to_control_port,
      input_muxi       => input_mux_to_eth_output,
      input_muxo       => eth_output_to_input_mux,
      duti             => duti,
      duto             => duto
   );

end architecture rtl;