---------------------------------------------------------------------------
-- File           : p_patt_gen_interface.vhd
-- Author(s)      : Nikola Avramovic
-- Created        : March 30th, 2019
---------------------------------------------------------------------------
-- Description    : Pattern generator internal interfaces
---------------------------------------------------------------------------

---------------------------------------------------------------------------

library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;
   use work.p_parameters_and_constants.all;
   use work.p_interfaces.all;

package p_patt_gen_interface is
   
   ----------------------------------------------------------------
   -- Command and status interfaces
   ----------------------------------------------------------------

   type TYPE_MUX_SELECT is (LFSR_DATA,  INCREMENT_DATA, CRC32_DATA, NONE);

   type TYPE_LFSR_TO_CTRL_PATTERN is record
      busy              : boolean;
      first_byte        : boolean;
      last_byte         : boolean;
   end record;

   type TYPE_CTRL_PATTERN_TO_LFSR is record
      frame_length      : natural;
      seed              : natural;
      seed_en           : boolean;
      lfsr_en           : boolean;
   end record;

   type TYPE_LINEAR_TO_CTRL_PATTERN is record
      last_byte         : boolean;
      busy              : boolean;
   end record;

   type TYPE_CTRL_PATTERN_TO_LINEAR is record
      frame_length      : natural;
      start_seqence     : natural;
      linear_en         : boolean;
   end record;

   type TYPE_CTRL_PATTERN_TO_CRC32 is record
      crc32_en          : boolean;
   end record;

   type TYPE_PATTERN_MUX_TO_CTRL_PATTERN is record
      busy              : boolean;
   end record;

   type TYPE_CTRL_PATTERN_TO_PATTERN_MUX is record
      mux_sel           : TYPE_MUX_SELECT;
   end record;

   type TYPE_PATT_MUX_TO_FIFO_AVALON is record
      req                 : boolean;
      end_of_packet       : boolean;
      start_of_packet     : boolean;
      data                : std_logic_vector(C_AVALON_ST_DATA_WIDTH - 1 downto 0);
   end record;

   type TYPE_CRC32_TO_PATTERN_MUX is record
      crc_data            : std_logic_vector(C_CRC32_DATA_WIDTH - 1 downto 0);
   end record;

   type TYPE_PATTERN_MUX_TO_CRC32 is record
      data                : std_logic_vector(C_AVALON_ST_DATA_WIDTH - 1 downto 0);
   end record;

   type TYPE_FIFO_AVALON_TO_LFSR is record
      fifo_full           : boolean;
   end record;

   type TYPE_FIFO_AVALON_TO_LINEAR is record
      fifo_full           : boolean;
   end record;

   type TYPE_LINEAR_GEN_TO_PATTERN_MUX is record
      data                : std_logic_vector(C_AVALON_ST_DATA_WIDTH - 1 downto 0);
      first_byte          : boolean;
      req                 : boolean;
   end record;

   type TYPE_LFSR_GEN_TO_PATTERN_MUX is record
      rand_data           : std_logic_vector(C_AVALON_ST_DATA_WIDTH - 1 downto 0);
      first_byte          : boolean;
      req                 : boolean;
   end record;

end package;
