---------------------------------------------------------------------------
-- File           : ea_avalon_mm_interface_gen.vhd
-- Author(s)      : Nikola Avramovic
-- Created        : March 11th, 2019
---------------------------------------------------------------------------
-- Description    : Input output module for comunicatin with host
---------------------------------------------------------------------------

---------------------------------------------------------------------------
library ieee, work;
   use ieee.std_logic_1164.all;
   use work.p_interfaces.all;
   use work.p_addresses.all;
   use work.p_generator_interface.all;

entity ea_avalon_mm_interface_gen is
   generic(
      G_NO_OF_PATT_GEN    : natural  := 2
      );
   port  (
      clk               : in  std_logic;
      reset             : in  std_logic;
      -- to/from NIOS II processor
      masteri           : in  TYPE_AVALON_MM_MASTER_TO_SLAVE;
      mastero           : out TYPE_AVALON_MM_SLAVE_TO_MASTER;
      -- to/from pattern generator
      pattern_geni      : in  TYPE_PATTERN_GEN_TO_CMD_DECODER_ARRAY(G_NO_OF_PATT_GEN-1 downto 0);
      pattern_geno      : out TYPE_CMD_DECODER_TO_PATTERN_GEN_ARRAY(G_NO_OF_PATT_GEN-1 downto 0);
      -- to/from port generator
      port_geni         : in  TYPE_PORT_GEN_TO_CMD_DECODER;
      port_geno         : out TYPE_CMD_DECODER_TO_PORT_GEN;
      -- to status object
      pattern_statusi   : in  TYPE_PATTERN_GEN_TO_STATUS_ARRAY(G_NO_OF_PATT_GEN-1 downto 0);
      port_statusi      : in  TYPE_PORT_GEN_TO_STATUS
   );
end entity ea_avalon_mm_interface_gen;

architecture rtl of ea_avalon_mm_interface_gen is

   -- wait request is signal from two modules 
   signal waitrequest                  : std_logic;

   -- avalon mm write
   signal master_to_fifo_cmd           : TYPE_MASTER_TO_FIFO_CMD;
   signal fifo_cmd_to_master           : TYPE_FIFO_CMD_TO_MASTER;
   -- in/out to command decoder
   signal cmd_decoder_to_fifo_cmd      : TYPE_CMD_DEC_TO_FIFO_CMD;
   signal fifo_cmd_to_cmd_decoder      : TYPE_FIFO_CMD_TO_CMD_DEC;
   -- status signals
   signal master_to_status             : TYPE_MASTER_TO_STATUS;
   signal status_to_master             : TYPE_STATUS_TO_MASTER;
   
begin

   fifo_cmd_i: entity work.ea_cmd_gen_fifo
   port map (
      clk               => clk,
      reset             => reset,
      -- to/from input generator
      masteri           => master_to_fifo_cmd,
      mastero           => fifo_cmd_to_master,
      -- to/from command decoder
      cmd_decoderi      => cmd_decoder_to_fifo_cmd,
      cmd_decodero      => fifo_cmd_to_cmd_decoder
   );

   cmd_decoder_i: entity work.ea_cmd_gen_decoder
   port map (
      clk               => clk,
      reset             => reset,
      -- to/from FIFO command
      fifo_cmdi         => fifo_cmd_to_cmd_decoder,
      fifo_cmdo         => cmd_decoder_to_fifo_cmd,
      -- to/from pattern generator
      pattern_geni      => pattern_geni,
      pattern_geno      => pattern_geno,
      -- to/from port generator
      port_geni         => port_geni,
      port_geno         => port_geno
   );

   status_obj_i: entity work.ea_status_object_gen
   generic map (
      G_NO_OF_PATT_GEN  => G_NO_OF_PATT_GEN
   )
   port map (
      clk               => clk,
      reset             => reset,
      -- to/from input g=> ,
      masteri           => master_to_status,
      mastero           => status_to_master,
      -- from pattern generator
      pattern_geni      => pattern_statusi,
      -- from port generator
      port_geni         => port_statusi
   );

   waitrequest        <= fifo_cmd_to_master.fifo_full when (masteri.write = '1') else fifo_cmd_to_master.fifo_full;--status_to_master.wait_req;

   master_to_fifo_cmd <= (address       => masteri.address,
                          write_req     => masteri.write,
                          data_in       => masteri.writedata,
                          new_package   => masteri.beginbursttransfer,
                          write_count   => masteri.burstcount);

   mastero            <= (readdatavalid => status_to_master.data_valid,
                          readdata      => status_to_master.read_data,
                          waitrequest   => waitrequest);

end architecture rtl;