---------------------------------------------------------------------------
-- File           : ea_port_mon.vhd
-- Author(s)      : Nikola Avramovic
-- Created        : April 11th, 2019
---------------------------------------------------------------------------
-- Description    : Monitor port top module
---------------------------------------------------------------------------

---------------------------------------------------------------------------
library ieee, work;
   use ieee.std_logic_1164.all;
   use work.p_interfaces.all;
   use work.p_addresses.all;
   use work.p_monitor_interface.all;
   use work.p_port_mon_interface.all;

entity ea_port_mon is
   generic(
      G_NO_OF_PATT_MON: natural;
      G_PORT_MON_NO   : natural
      );
   port (
      clk             : in  std_logic;
      reset           : in  std_logic;
      -- to/from input control module
      cmd_decoderi    : in  TYPE_CMD_DECODER_TO_PORT_MON;
      cmd_decodero    : out TYPE_PORT_MON_TO_CMD_DECODER;
      -- to/from pattern monitor
      pattern_moni    : in  TYPE_AVALON_ST_SINK_TO_SOURCE_ARRAY(G_NO_OF_PATT_MON downto 1);
      pattern_mono    : out TYPE_AVALON_ST_SOURCE_TO_SINK_ARRAY(G_NO_OF_PATT_MON downto 1);
      -- to/from device under test
      duti            : in  TYPE_AVALON_ST_SOURCE_TO_SINK;
      duto            : out TYPE_AVALON_ST_SINK_TO_SOURCE;
      -- status interface
      statusi         : in   TYPE_STATUS_TO_PORT_MON;
      statuso         : out  TYPE_PORT_MON_TO_STATUS

   );
end entity ea_port_mon;

architecture rtl of ea_port_mon is

   -- intercontect signals
   ----------------------------------------------------------------
   signal control_port_to_cam            : TYPE_CONTROL_PORT_TO_CAM;
   signal cam_to_control_port            : TYPE_CAM_TO_CONTROL_PORT;
   signal control_port_to_header_check   : TYPE_CONTROL_PORT_TO_HEADER_CHECK;
   signal header_check_to_control_port   : TYPE_HEADER_CHECK_TO_CONTROL_PORT;
   signal header_check_to_cam            : TYPE_HEADER_CHECK_TO_CAM;
   signal cam_to_header_check            : TYPE_CAM_TO_HEADER_CHECK;

begin
   
   control_port_mon_i: entity work.ea_control_port_mon
   generic map (
      G_PORT_MON_NO    => G_PORT_MON_NO
   ) port map (
      clk              => clk,
      reset            => reset,
      cmd_decoderi     => cmd_decoderi,
      cmd_decodero     => cmd_decodero,
      cami             => cam_to_control_port,
      camo             => control_port_to_cam,
      header_checki    => header_check_to_control_port,
      header_checko    => control_port_to_header_check,
      statusi          => statusi,
      statuso          => statuso
   );

   cam_i: entity work.ea_content_addressable_memory
   generic map (
      G_NO_OF_PATT_MON => G_NO_OF_PATT_MON
   ) 
   port map(
      clk              => clk,
      reset            => reset,
      control_porti    => control_port_to_cam,
      control_porto    => cam_to_control_port,
      header_checki    => header_check_to_cam,
      header_checko    => cam_to_header_check,
      duti             => duti,
      duto             => duto,
      pattern_moni     => pattern_moni,
      pattern_mono     => pattern_mono
   );


   header_check_i:entity work.ea_header_check
   port map (
      clk              => clk,
      reset            => reset,
      control_porti    => control_port_to_header_check,
      control_porto    => header_check_to_control_port,
      cami             => cam_to_header_check,
      camo             => header_check_to_cam
   );

end architecture rtl;