-----------------------------------------------------------------------
--
--   Company: INVEA-TECH a.s.
--
--
--   Project: NetCOPE 05_0C
--
--    $Id$
--
--
-- -----------------------------------------------------------------------
--
--
--   (c) Copyright 2012 INVEA-TECH a.s.
--   All rights reserved.
--
--   Please review the terms of the license agreement before using this
--   file. If you are not an authorized user, please destroy this
--   source code file and notify INVEA-TECH a.s. immediately that you
--   inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- application.vhd : Combov2 NetCOPE application module
-- Copyright (C) 2009 CESNET
-- Author(s): Jan Stourac <xstour03@stud.fit.vutbr.cz>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
--    notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
--    notice, this list of conditions and the following disclaimer in
--    the documentation and/or other materials provided with the
--    distribution.
-- 3. Neither the name of the Company nor the names of its contributors
--    may be used to endorse or promote products derived from this
--    software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id$
--

-- ----------------------------------------------------------------------------
--                             Entity declaration
-- ----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.combov2_core_const.all;
use work.combov2_user_const.all;
use work.math_pack.all;
use work.ibuf_general_pkg.all;
use work.addr_space.all;
use work.network_mod_10g2_64_const.all;
Library UNISIM;
use UNISIM.vcomponents.all;

architecture full of APPLICATION is

	constant DMA_IFC_COUNT       : integer := 8;
	constant FL_IFC_COUNT        : integer := 2;
	constant FL_WIDTH            : integer := 64;

	constant CHANNELS_PER_RX     : integer := DMA_IFC_COUNT / FL_IFC_COUNT;

	component tsu_async is
	-- PORTS
	port (
		RESET          : in std_logic;

		-- Input interface
		IN_CLK         : in std_logic;

		IN_TS          : in std_logic_vector(63 downto 0);
		IN_TS_DV       : in std_logic;

		-- Output interface
		OUT_CLK        : in std_logic;

		OUT_TS         : out std_logic_vector(63 downto 0);
		OUT_TS_DV      : out std_logic
	);
	end component tsu_async;


-- ----------------------------------------------------------------------------
--                            Signal declaration
-- ----------------------------------------------------------------------------

	-- -------------------------------------------------------------------------
	--                         Pacodag signals
	-- -------------------------------------------------------------------------
	signal ts0_sync              : std_logic_vector(63 downto 0);
	signal ts0_dv_sync           : std_logic;
	signal ts1_sync              : std_logic_vector(63 downto 0);
	signal ts1_dv_sync           : std_logic;

	--KOD
	-- -------------------------------------------------------------------------
	--                         NAS PROJEKT KOMPONENTA
	-- -------------------------------------------------------------------------
	constant pociatok_adresovania : integer := 10000;

	component ent_krabica is
		generic
		(
			krabica_pociatok_adresovania			: integer
		);

		port
		(
			--riadenie hodinami
			krabica_CLK                             : in    std_logic;
			--asynchronny reset
			krabica_RESET                           : in    std_logic;
			--ROZHRANIE 0
			--vstupny FrameLink
			krabica_IF0_INPUT_SOF_N                 : in    std_logic;
			krabica_IF0_INPUT_SOP_N                 : in    std_logic;
			krabica_IF0_INPUT_EOP_N                 : in    std_logic;
			krabica_IF0_INPUT_EOF_N                 : in    std_logic;
			krabica_IF0_INPUT_SRC_RDY_N             : in    std_logic;
			krabica_IF0_INPUT_DST_RDY_N             : out   std_logic;
			krabica_IF0_INPUT_DATA                  : in    std_logic_vector ( 63 downto 0 );
			krabica_IF0_INPUT_DREM                  : in    std_logic_vector (  2 downto 0 );
			--vystupny FrameLink
			krabica_IF0_OUTPUT_SOF_N                : out   std_logic;
			krabica_IF0_OUTPUT_SOP_N                : out   std_logic;
			krabica_IF0_OUTPUT_EOP_N                : out   std_logic;
			krabica_IF0_OUTPUT_EOF_N                : out   std_logic;
			krabica_IF0_OUTPUT_SRC_RDY_N            : out   std_logic;
			krabica_IF0_OUTPUT_DST_RDY_N            : in    std_logic;
			krabica_IF0_OUTPUT_DATA                 : out   std_logic_vector ( 63 downto 0 );
			krabica_IF0_OUTPUT_DREM                 : out   std_logic_vector (  2 downto 0 );
			--ROZHRANIE 1
			--vstupny FrameLink
			krabica_IF1_INPUT_SOF_N                 : in    std_logic;
			krabica_IF1_INPUT_SOP_N                 : in    std_logic;
			krabica_IF1_INPUT_EOP_N                 : in    std_logic;
			krabica_IF1_INPUT_EOF_N                 : in    std_logic;
			krabica_IF1_INPUT_SRC_RDY_N             : in    std_logic;
			krabica_IF1_INPUT_DST_RDY_N             : out   std_logic;
			krabica_IF1_INPUT_DATA                  : in    std_logic_vector ( 63 downto 0 );
			krabica_IF1_INPUT_DREM                  : in    std_logic_vector (  2 downto 0 );
			--vystupny FrameLink
			krabica_IF1_OUTPUT_SOF_N                : out   std_logic;
			krabica_IF1_OUTPUT_SOP_N                : out   std_logic;
			krabica_IF1_OUTPUT_EOP_N                : out   std_logic;
			krabica_IF1_OUTPUT_EOF_N                : out   std_logic;
			krabica_IF1_OUTPUT_SRC_RDY_N            : out   std_logic;
			krabica_IF1_OUTPUT_DST_RDY_N            : in    std_logic;
			krabica_IF1_OUTPUT_DATA                 : out   std_logic_vector ( 63 downto 0 );
			krabica_IF1_OUTPUT_DREM                 : out   std_logic_vector (  2 downto 0 );

			krabica_MI32_DWR          				: in  std_logic_vector(31 downto 0);
			krabica_MI32_ADDR         				: in  std_logic_vector(31 downto 0);
			krabica_MI32_RD           				: in  std_logic;
			krabica_MI32_WR           				: in  std_logic;
			krabica_MI32_BE           				: in  std_logic_vector(3 downto 0);
			krabica_MI32_DRD          				: out std_logic_vector(31 downto 0);
			krabica_MI32_ARDY         				: out std_logic;
			krabica_MI32_DRDY         				: out std_logic
		  );
	 end component ent_krabica;
	 --KONIEC_KODU

-- ----------------------------------------------------------------------------
--                             Architecture body
-- ----------------------------------------------------------------------------
begin

	-- -------------------------------------------------------------------------
	--                              PACODAG
	-- -------------------------------------------------------------------------
	PACODAG_TOP_I: entity work.pacodag_tsu_top2_t64
	generic map(
		HEADER_EN => PACODAG_HEADER_EN,
		FOOTER_EN => PACODAG_FOOTER_EN
	)
	port map(
		-- Common interface
		RESET    => RESET,
		-- IBUF interface
		PCD0_CTRL_CLK              => IBUF0_CTRL_CLK,
		PCD0_CTRL_DATA             => IBUF0_CTRL_DATA,
		PCD0_CTRL_REM              => IBUF0_CTRL_REM,
		PCD0_CTRL_SRC_RDY_N        => IBUF0_CTRL_SRC_RDY_N,
		PCD0_CTRL_SOP_N            => IBUF0_CTRL_SOP_N,
		PCD0_CTRL_EOP_N            => IBUF0_CTRL_EOP_N,
		PCD0_CTRL_DST_RDY_N        => IBUF0_CTRL_DST_RDY_N,
		PCD0_CTRL_RDY              => IBUF0_CTRL_RDY,
		PCD0_SOP                   => IBUF0_SOP,
		PCD0_STAT_PAYLOAD_LEN      => IBUF0_PAYLOAD_LEN,
		PCD0_STAT_FRAME_ERROR      => IBUF0_FRAME_ERROR,
		PCD0_STAT_CRC_CHECK_FAILED => IBUF0_CRC_CHECK_FAILED,
		PCD0_STAT_MAC_CHECK_FAILED => IBUF0_MAC_CHECK_FAILED,
		PCD0_STAT_LEN_BELOW_MIN    => IBUF0_LEN_BELOW_MIN,
		PCD0_STAT_LEN_OVER_MTU     => IBUF0_LEN_OVER_MTU,
		PCD0_STAT_DV               => IBUF0_STAT_DV,

		PCD1_CTRL_CLK              => IBUF1_CTRL_CLK,
		PCD1_CTRL_DATA             => IBUF1_CTRL_DATA,
		PCD1_CTRL_REM              => IBUF1_CTRL_REM,
		PCD1_CTRL_SRC_RDY_N        => IBUF1_CTRL_SRC_RDY_N,
		PCD1_CTRL_SOP_N            => IBUF1_CTRL_SOP_N,
		PCD1_CTRL_EOP_N            => IBUF1_CTRL_EOP_N,
		PCD1_CTRL_DST_RDY_N        => IBUF1_CTRL_DST_RDY_N,
		PCD1_CTRL_RDY              => IBUF1_CTRL_RDY,
		PCD1_SOP                   => IBUF1_SOP,
		PCD1_STAT_PAYLOAD_LEN      => IBUF1_PAYLOAD_LEN,
		PCD1_STAT_FRAME_ERROR      => IBUF1_FRAME_ERROR,
		PCD1_STAT_CRC_CHECK_FAILED => IBUF1_CRC_CHECK_FAILED,
		PCD1_STAT_MAC_CHECK_FAILED => IBUF1_MAC_CHECK_FAILED,
		PCD1_STAT_LEN_BELOW_MIN    => IBUF1_LEN_BELOW_MIN,
		PCD1_STAT_LEN_OVER_MTU     => IBUF1_LEN_OVER_MTU,
		PCD1_STAT_DV               => IBUF1_STAT_DV,

		TS0       => ts0_sync,
		TS0_DV    => ts0_dv_sync,
		TS1       => ts1_sync,
		TS1_DV    => ts1_dv_sync
	);

	-- ---------------------------------------------------------------
	-- Generate tsu_async only if timestamp unit is also generated
	ts_true_async : if TIMESTAMP_UNIT = true generate
	tsu_async_i0 : tsu_async
		-- PORTS
		port map (
			RESET          => RESET,
			-- Input interface
			IN_CLK         => TS_CLK,
			IN_TS          => TS,
			IN_TS_DV       => TS_DV,
			-- Output interface
			OUT_CLK        => IBUF0_CTRL_CLK,
			OUT_TS         => ts0_sync,
			OUT_TS_DV      => ts0_dv_sync
		);
		tsu_async_i1 : tsu_async
		-- PORTS
		port map (
			RESET          => RESET,
			-- Input interface
			IN_CLK         => TS_CLK,
			IN_TS          => TS,
			IN_TS_DV       => TS_DV,
			-- Output interface
			OUT_CLK        => IBUF1_CTRL_CLK,
			OUT_TS         => ts1_sync,
			OUT_TS_DV      => ts1_dv_sync
		);
	end generate ts_true_async;

	-- Else map TS and TS_DV signals directly into pacodag
	ts_false_async : if TIMESTAMP_UNIT = false generate
		ts0_sync <= TS;
		ts0_dv_sync <= TS_DV;
		ts1_sync <= TS;
		ts1_dv_sync <= TS_DV;
	end generate ts_false_async;
	-- ---------------------------------------------------------------

	-- -------------------------------------------------------------------------
	-- Intercept packets
	-- -------------------------------------------------------------------------
	-- Insert your code here


	--KOD
	-- -------------------------------------------------------------------------
	--                         NAS EXPERIMENT - INSTANCIA
	-- -------------------------------------------------------------------------
	krabica_top : ent_krabica
		generic map
		(
			krabica_pociatok_adresovania			=>	pociatok_adresovania
		)

		port map(
			--riadenie hodinami
			krabica_CLK                             =>	CLK,
			--asynchronny reset
			krabica_RESET                           =>	RESET,
			--ROZHRANIE 0
			--vstupny FrameLink
			krabica_IF0_INPUT_SOF_N                 =>	IBUF0_TX_SOF_N,
			krabica_IF0_INPUT_SOP_N                 =>	IBUF0_TX_SOP_N,
			krabica_IF0_INPUT_EOP_N                 =>	IBUF0_TX_EOP_N,
			krabica_IF0_INPUT_EOF_N                 =>	IBUF0_TX_EOF_N,
			krabica_IF0_INPUT_SRC_RDY_N             =>	IBUF0_TX_SRC_RDY_N,
			krabica_IF0_INPUT_DST_RDY_N             =>	IBUF0_TX_DST_RDY_N,
			krabica_IF0_INPUT_DATA                  =>	IBUF0_TX_DATA,
			krabica_IF0_INPUT_DREM                  =>	IBUF0_TX_REM,
			--vystupny FrameLink
			krabica_IF0_OUTPUT_SOF_N                =>	OBUF0_RX_SOF_N,
			krabica_IF0_OUTPUT_SOP_N                =>	OBUF0_RX_SOP_N,
			krabica_IF0_OUTPUT_EOP_N                =>	OBUF0_RX_EOP_N,
			krabica_IF0_OUTPUT_EOF_N                =>	OBUF0_RX_EOF_N,
			krabica_IF0_OUTPUT_SRC_RDY_N            =>	OBUF0_RX_SRC_RDY_N,
			krabica_IF0_OUTPUT_DST_RDY_N            =>	OBUF0_RX_DST_RDY_N,
			krabica_IF0_OUTPUT_DATA                 =>	OBUF0_RX_DATA,
			krabica_IF0_OUTPUT_DREM                 =>	OBUF0_RX_REM,
			--ROZHRANIE 1
			--vstupny FrameLink
			krabica_IF1_INPUT_SOF_N                 =>	IBUF1_TX_SOF_N,
			krabica_IF1_INPUT_SOP_N                 =>	IBUF1_TX_SOP_N,
			krabica_IF1_INPUT_EOP_N                 =>	IBUF1_TX_EOP_N,
			krabica_IF1_INPUT_EOF_N                 =>	IBUF1_TX_EOF_N,
			krabica_IF1_INPUT_SRC_RDY_N             =>	IBUF1_TX_SRC_RDY_N,
			krabica_IF1_INPUT_DST_RDY_N             =>	IBUF1_TX_DST_RDY_N,
			krabica_IF1_INPUT_DATA                  =>	IBUF1_TX_DATA,
			krabica_IF1_INPUT_DREM                  =>	IBUF1_TX_REM,
			--vystupny FrameLink
			krabica_IF1_OUTPUT_SOF_N                =>	OBUF1_RX_SOF_N,
			krabica_IF1_OUTPUT_SOP_N                =>	OBUF1_RX_SOP_N,
			krabica_IF1_OUTPUT_EOP_N                =>	OBUF1_RX_EOP_N,
			krabica_IF1_OUTPUT_EOF_N                =>	OBUF1_RX_EOF_N,
			krabica_IF1_OUTPUT_SRC_RDY_N            =>	OBUF1_RX_SRC_RDY_N,
			krabica_IF1_OUTPUT_DST_RDY_N            =>	OBUF1_RX_DST_RDY_N,
			krabica_IF1_OUTPUT_DATA                 =>	OBUF1_RX_DATA,
			krabica_IF1_OUTPUT_DREM                 =>	OBUF1_RX_REM,
			--
			krabica_MI32_DWR     					=>  MI32_DWR,
			krabica_MI32_ADDR    					=>  MI32_ADDR,
			krabica_MI32_RD      					=>  MI32_RD,
			krabica_MI32_WR      					=>  MI32_WR,
			krabica_MI32_BE      					=>  MI32_BE,
			krabica_MI32_DRD     					=>  MI32_DRD,
			krabica_MI32_ARDY    					=>  MI32_ARDY,
			krabica_MI32_DRDY    					=>  MI32_DRDY
		);

	 --KONIEC_KODU

end architecture full;
