// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
// Date        : Fri May 14 16:50:17 2021
// Host        : zz-Latitude-7490 running 64-bit Ubuntu 20.04.2 LTS
// Command     : write_verilog -force -mode funcsim
//               /home/zz/phpix/phpix-vivado-peta/hw_linux/clean_hw/clean_hw.gen/sources_1/bd/blok/ip/blok_xbar_0/blok_xbar_0_sim_netlist.v
// Design      : blok_xbar_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "blok_xbar_0,axi_crossbar_v2_1_23_axi_crossbar,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_crossbar_v2_1_23_axi_crossbar,Vivado 2020.2" *) 
(* NotValidForBitStream *)
module blok_xbar_0
   (aclk,
    aresetn,
    s_axi_awid,
    s_axi_awaddr,
    s_axi_awlen,
    s_axi_awsize,
    s_axi_awburst,
    s_axi_awlock,
    s_axi_awcache,
    s_axi_awprot,
    s_axi_awqos,
    s_axi_awvalid,
    s_axi_awready,
    s_axi_wdata,
    s_axi_wstrb,
    s_axi_wlast,
    s_axi_wvalid,
    s_axi_wready,
    s_axi_bid,
    s_axi_bresp,
    s_axi_bvalid,
    s_axi_bready,
    s_axi_arid,
    s_axi_araddr,
    s_axi_arlen,
    s_axi_arsize,
    s_axi_arburst,
    s_axi_arlock,
    s_axi_arcache,
    s_axi_arprot,
    s_axi_arqos,
    s_axi_arvalid,
    s_axi_arready,
    s_axi_rid,
    s_axi_rdata,
    s_axi_rresp,
    s_axi_rlast,
    s_axi_rvalid,
    s_axi_rready,
    m_axi_awaddr,
    m_axi_awlen,
    m_axi_awsize,
    m_axi_awburst,
    m_axi_awlock,
    m_axi_awcache,
    m_axi_awprot,
    m_axi_awregion,
    m_axi_awqos,
    m_axi_awvalid,
    m_axi_awready,
    m_axi_wdata,
    m_axi_wstrb,
    m_axi_wlast,
    m_axi_wvalid,
    m_axi_wready,
    m_axi_bresp,
    m_axi_bvalid,
    m_axi_bready,
    m_axi_araddr,
    m_axi_arlen,
    m_axi_arsize,
    m_axi_arburst,
    m_axi_arlock,
    m_axi_arcache,
    m_axi_arprot,
    m_axi_arregion,
    m_axi_arqos,
    m_axi_arvalid,
    m_axi_arready,
    m_axi_rdata,
    m_axi_rresp,
    m_axi_rlast,
    m_axi_rvalid,
    m_axi_rready);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 50000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN blok_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *) input aclk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *) input aresetn;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID" *) input [11:0]s_axi_awid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s_axi_awaddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN" *) input [7:0]s_axi_awlen;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE" *) input [2:0]s_axi_awsize;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST" *) input [1:0]s_axi_awburst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK" *) input [0:0]s_axi_awlock;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE" *) input [3:0]s_axi_awcache;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s_axi_awprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS" *) input [3:0]s_axi_awqos;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input [0:0]s_axi_awvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output [0:0]s_axi_awready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s_axi_wdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s_axi_wstrb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST" *) input [0:0]s_axi_wlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input [0:0]s_axi_wvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output [0:0]s_axi_wready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID" *) output [11:0]s_axi_bid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s_axi_bresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output [0:0]s_axi_bvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input [0:0]s_axi_bready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID" *) input [11:0]s_axi_arid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s_axi_araddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *) input [7:0]s_axi_arlen;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *) input [2:0]s_axi_arsize;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *) input [1:0]s_axi_arburst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *) input [0:0]s_axi_arlock;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *) input [3:0]s_axi_arcache;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s_axi_arprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *) input [3:0]s_axi_arqos;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input [0:0]s_axi_arvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output [0:0]s_axi_arready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID" *) output [11:0]s_axi_rid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s_axi_rdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *) output [0:0]s_axi_rlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN blok_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [0:0]s_axi_rready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *) output [95:0]m_axi_awaddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI AWLEN [7:0] [23:16]" *) output [23:0]m_axi_awlen;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE [2:0] [8:6]" *) output [8:0]m_axi_awsize;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI AWBURST [1:0] [5:4]" *) output [5:0]m_axi_awburst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK [0:0] [2:2]" *) output [2:0]m_axi_awlock;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE [3:0] [11:8]" *) output [11:0]m_axi_awcache;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *) output [8:0]m_axi_awprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWREGION [3:0] [11:8]" *) output [11:0]m_axi_awregion;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWQOS [3:0] [11:8]" *) output [11:0]m_axi_awqos;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *) output [2:0]m_axi_awvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *) input [2:0]m_axi_awready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *) output [95:0]m_axi_wdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *) output [11:0]m_axi_wstrb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WLAST [0:0] [2:2]" *) output [2:0]m_axi_wlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *) output [2:0]m_axi_wvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *) input [2:0]m_axi_wready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *) input [5:0]m_axi_bresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *) input [2:0]m_axi_bvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *) output [2:0]m_axi_bready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *) output [95:0]m_axi_araddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI ARLEN [7:0] [23:16]" *) output [23:0]m_axi_arlen;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE [2:0] [8:6]" *) output [8:0]m_axi_arsize;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI ARBURST [1:0] [5:4]" *) output [5:0]m_axi_arburst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK [0:0] [2:2]" *) output [2:0]m_axi_arlock;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE [3:0] [11:8]" *) output [11:0]m_axi_arcache;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *) output [8:0]m_axi_arprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARREGION [3:0] [11:8]" *) output [11:0]m_axi_arregion;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARQOS [3:0] [11:8]" *) output [11:0]m_axi_arqos;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *) output [2:0]m_axi_arvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *) input [2:0]m_axi_arready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *) input [95:0]m_axi_rdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *) input [5:0]m_axi_rresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RLAST [0:0] [2:2]" *) input [2:0]m_axi_rlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *) input [2:0]m_axi_rvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN blok_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN blok_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN blok_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output [2:0]m_axi_rready;

  wire \<const0> ;
  wire aclk;
  wire aresetn;
  wire [95:0]m_axi_araddr;
  wire [5:0]m_axi_arburst;
  wire [11:0]m_axi_arcache;
  wire [23:0]m_axi_arlen;
  wire [2:0]m_axi_arlock;
  wire [8:0]m_axi_arprot;
  wire [11:0]m_axi_arqos;
  wire [2:0]m_axi_arready;
  wire [8:0]m_axi_arsize;
  wire [2:0]m_axi_arvalid;
  wire [95:0]m_axi_awaddr;
  wire [5:0]m_axi_awburst;
  wire [11:0]m_axi_awcache;
  wire [23:0]m_axi_awlen;
  wire [2:0]m_axi_awlock;
  wire [8:0]m_axi_awprot;
  wire [11:0]m_axi_awqos;
  wire [2:0]m_axi_awready;
  wire [8:0]m_axi_awsize;
  wire [2:0]m_axi_awvalid;
  wire [2:0]m_axi_bready;
  wire [5:0]m_axi_bresp;
  wire [2:0]m_axi_bvalid;
  wire [95:0]m_axi_rdata;
  wire [2:0]m_axi_rlast;
  wire [2:0]m_axi_rready;
  wire [5:0]m_axi_rresp;
  wire [2:0]m_axi_rvalid;
  wire [95:0]m_axi_wdata;
  wire [2:0]m_axi_wlast;
  wire [2:0]m_axi_wready;
  wire [11:0]m_axi_wstrb;
  wire [2:0]m_axi_wvalid;
  wire [31:0]s_axi_araddr;
  wire [1:0]s_axi_arburst;
  wire [3:0]s_axi_arcache;
  wire [11:0]s_axi_arid;
  wire [7:0]s_axi_arlen;
  wire [0:0]s_axi_arlock;
  wire [2:0]s_axi_arprot;
  wire [3:0]s_axi_arqos;
  wire [0:0]s_axi_arready;
  wire [2:0]s_axi_arsize;
  wire [0:0]s_axi_arvalid;
  wire [31:0]s_axi_awaddr;
  wire [1:0]s_axi_awburst;
  wire [3:0]s_axi_awcache;
  wire [11:0]s_axi_awid;
  wire [7:0]s_axi_awlen;
  wire [0:0]s_axi_awlock;
  wire [2:0]s_axi_awprot;
  wire [3:0]s_axi_awqos;
  wire [0:0]s_axi_awready;
  wire [2:0]s_axi_awsize;
  wire [0:0]s_axi_awvalid;
  wire [11:0]s_axi_bid;
  wire [0:0]s_axi_bready;
  wire [1:0]s_axi_bresp;
  wire [0:0]s_axi_bvalid;
  wire [31:0]s_axi_rdata;
  wire [11:0]s_axi_rid;
  wire [0:0]s_axi_rlast;
  wire [0:0]s_axi_rready;
  wire [1:0]s_axi_rresp;
  wire [0:0]s_axi_rvalid;
  wire [31:0]s_axi_wdata;
  wire [0:0]s_axi_wlast;
  wire [0:0]s_axi_wready;
  wire [3:0]s_axi_wstrb;
  wire [0:0]s_axi_wvalid;
  wire [35:0]NLW_inst_m_axi_arid_UNCONNECTED;
  wire [11:0]NLW_inst_m_axi_arregion_UNCONNECTED;
  wire [2:0]NLW_inst_m_axi_aruser_UNCONNECTED;
  wire [35:0]NLW_inst_m_axi_awid_UNCONNECTED;
  wire [11:0]NLW_inst_m_axi_awregion_UNCONNECTED;
  wire [2:0]NLW_inst_m_axi_awuser_UNCONNECTED;
  wire [35:0]NLW_inst_m_axi_wid_UNCONNECTED;
  wire [2:0]NLW_inst_m_axi_wuser_UNCONNECTED;
  wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
  wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;

  assign m_axi_arregion[11] = \<const0> ;
  assign m_axi_arregion[10] = \<const0> ;
  assign m_axi_arregion[9] = \<const0> ;
  assign m_axi_arregion[8] = \<const0> ;
  assign m_axi_arregion[7] = \<const0> ;
  assign m_axi_arregion[6] = \<const0> ;
  assign m_axi_arregion[5] = \<const0> ;
  assign m_axi_arregion[4] = \<const0> ;
  assign m_axi_arregion[3] = \<const0> ;
  assign m_axi_arregion[2] = \<const0> ;
  assign m_axi_arregion[1] = \<const0> ;
  assign m_axi_arregion[0] = \<const0> ;
  assign m_axi_awregion[11] = \<const0> ;
  assign m_axi_awregion[10] = \<const0> ;
  assign m_axi_awregion[9] = \<const0> ;
  assign m_axi_awregion[8] = \<const0> ;
  assign m_axi_awregion[7] = \<const0> ;
  assign m_axi_awregion[6] = \<const0> ;
  assign m_axi_awregion[5] = \<const0> ;
  assign m_axi_awregion[4] = \<const0> ;
  assign m_axi_awregion[3] = \<const0> ;
  assign m_axi_awregion[2] = \<const0> ;
  assign m_axi_awregion[1] = \<const0> ;
  assign m_axi_awregion[0] = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* C_AXI_ADDR_WIDTH = "32" *) 
  (* C_AXI_ARUSER_WIDTH = "1" *) 
  (* C_AXI_AWUSER_WIDTH = "1" *) 
  (* C_AXI_BUSER_WIDTH = "1" *) 
  (* C_AXI_DATA_WIDTH = "32" *) 
  (* C_AXI_ID_WIDTH = "12" *) 
  (* C_AXI_PROTOCOL = "0" *) 
  (* C_AXI_RUSER_WIDTH = "1" *) 
  (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *) 
  (* C_AXI_WUSER_WIDTH = "1" *) 
  (* C_CONNECTIVITY_MODE = "0" *) 
  (* C_DEBUG = "1" *) 
  (* C_FAMILY = "zynq" *) 
  (* C_M_AXI_ADDR_WIDTH = "96'b000000000000000000000000000011010000000000000000000000000000111100000000000000000000000000001111" *) 
  (* C_M_AXI_BASE_ADDR = "192'b000000000000000000000000000000000100010000000000000000000000000000000000000000000000000000000000010000100000000000000000000000000000000000000000000000000000000001000000000000000000000000000000" *) 
  (* C_M_AXI_READ_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) 
  (* C_M_AXI_READ_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) 
  (* C_M_AXI_SECURE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_M_AXI_WRITE_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) 
  (* C_M_AXI_WRITE_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) 
  (* C_NUM_ADDR_RANGES = "1" *) 
  (* C_NUM_MASTER_SLOTS = "3" *) 
  (* C_NUM_SLAVE_SLOTS = "1" *) 
  (* C_R_REGISTER = "1" *) 
  (* C_S_AXI_ARB_PRIORITY = "0" *) 
  (* C_S_AXI_BASE_ID = "0" *) 
  (* C_S_AXI_READ_ACCEPTANCE = "1" *) 
  (* C_S_AXI_SINGLE_THREAD = "1" *) 
  (* C_S_AXI_THREAD_ID_WIDTH = "12" *) 
  (* C_S_AXI_WRITE_ACCEPTANCE = "1" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* P_ADDR_DECODE = "1" *) 
  (* P_AXI3 = "1" *) 
  (* P_AXI4 = "0" *) 
  (* P_AXILITE = "2" *) 
  (* P_AXILITE_SIZE = "3'b010" *) 
  (* P_FAMILY = "zynq" *) 
  (* P_INCR = "2'b01" *) 
  (* P_LEN = "8" *) 
  (* P_LOCK = "1" *) 
  (* P_M_AXI_ERR_MODE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) 
  (* P_M_AXI_SUPPORTS_READ = "3'b111" *) 
  (* P_M_AXI_SUPPORTS_WRITE = "3'b111" *) 
  (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) 
  (* P_RANGE_CHECK = "1" *) 
  (* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000111111111111" *) 
  (* P_S_AXI_SUPPORTS_READ = "1'b1" *) 
  (* P_S_AXI_SUPPORTS_WRITE = "1'b1" *) 
  blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar inst
       (.aclk(aclk),
        .aresetn(aresetn),
        .m_axi_araddr(m_axi_araddr),
        .m_axi_arburst(m_axi_arburst),
        .m_axi_arcache(m_axi_arcache),
        .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[35:0]),
        .m_axi_arlen(m_axi_arlen),
        .m_axi_arlock(m_axi_arlock),
        .m_axi_arprot(m_axi_arprot),
        .m_axi_arqos(m_axi_arqos),
        .m_axi_arready(m_axi_arready),
        .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[11:0]),
        .m_axi_arsize(m_axi_arsize),
        .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[2:0]),
        .m_axi_arvalid(m_axi_arvalid),
        .m_axi_awaddr(m_axi_awaddr),
        .m_axi_awburst(m_axi_awburst),
        .m_axi_awcache(m_axi_awcache),
        .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[35:0]),
        .m_axi_awlen(m_axi_awlen),
        .m_axi_awlock(m_axi_awlock),
        .m_axi_awprot(m_axi_awprot),
        .m_axi_awqos(m_axi_awqos),
        .m_axi_awready(m_axi_awready),
        .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[11:0]),
        .m_axi_awsize(m_axi_awsize),
        .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[2:0]),
        .m_axi_awvalid(m_axi_awvalid),
        .m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axi_bready(m_axi_bready),
        .m_axi_bresp(m_axi_bresp),
        .m_axi_buser({1'b0,1'b0,1'b0}),
        .m_axi_bvalid(m_axi_bvalid),
        .m_axi_rdata(m_axi_rdata),
        .m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axi_rlast(m_axi_rlast),
        .m_axi_rready(m_axi_rready),
        .m_axi_rresp(m_axi_rresp),
        .m_axi_ruser({1'b0,1'b0,1'b0}),
        .m_axi_rvalid(m_axi_rvalid),
        .m_axi_wdata(m_axi_wdata),
        .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[35:0]),
        .m_axi_wlast(m_axi_wlast),
        .m_axi_wready(m_axi_wready),
        .m_axi_wstrb(m_axi_wstrb),
        .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[2:0]),
        .m_axi_wvalid(m_axi_wvalid),
        .s_axi_araddr(s_axi_araddr),
        .s_axi_arburst(s_axi_arburst),
        .s_axi_arcache(s_axi_arcache),
        .s_axi_arid(s_axi_arid),
        .s_axi_arlen(s_axi_arlen),
        .s_axi_arlock(s_axi_arlock),
        .s_axi_arprot(s_axi_arprot),
        .s_axi_arqos(s_axi_arqos),
        .s_axi_arready(s_axi_arready),
        .s_axi_arsize(s_axi_arsize),
        .s_axi_aruser(1'b0),
        .s_axi_arvalid(s_axi_arvalid),
        .s_axi_awaddr(s_axi_awaddr),
        .s_axi_awburst(s_axi_awburst),
        .s_axi_awcache(s_axi_awcache),
        .s_axi_awid(s_axi_awid),
        .s_axi_awlen(s_axi_awlen),
        .s_axi_awlock(s_axi_awlock),
        .s_axi_awprot(s_axi_awprot),
        .s_axi_awqos(s_axi_awqos),
        .s_axi_awready(s_axi_awready),
        .s_axi_awsize(s_axi_awsize),
        .s_axi_awuser(1'b0),
        .s_axi_awvalid(s_axi_awvalid),
        .s_axi_bid(s_axi_bid),
        .s_axi_bready(s_axi_bready),
        .s_axi_bresp(s_axi_bresp),
        .s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
        .s_axi_bvalid(s_axi_bvalid),
        .s_axi_rdata(s_axi_rdata),
        .s_axi_rid(s_axi_rid),
        .s_axi_rlast(s_axi_rlast),
        .s_axi_rready(s_axi_rready),
        .s_axi_rresp(s_axi_rresp),
        .s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
        .s_axi_rvalid(s_axi_rvalid),
        .s_axi_wdata(s_axi_wdata),
        .s_axi_wid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wlast(s_axi_wlast),
        .s_axi_wready(s_axi_wready),
        .s_axi_wstrb(s_axi_wstrb),
        .s_axi_wuser(1'b0),
        .s_axi_wvalid(s_axi_wvalid));
endmodule

(* ORIG_REF_NAME = "axi_crossbar_v2_1_23_addr_arbiter_sasd" *) 
module blok_xbar_0_axi_crossbar_v2_1_23_addr_arbiter_sasd
   (p_0_in1_in,
    m_valid_i,
    SR,
    aa_grant_rnw,
    D,
    \gen_no_arbiter.m_amesg_i_reg[34]_0 ,
    Q,
    \m_ready_d_reg[1] ,
    m_ready_d0,
    \gen_no_arbiter.m_amesg_i_reg[27]_0 ,
    \gen_axi.s_axi_rid_i ,
    m_axi_arvalid,
    \aresetn_d_reg[1] ,
    E,
    \aresetn_d_reg[0] ,
    m_axi_awvalid,
    \m_ready_d_reg[2] ,
    s_axi_wready,
    m_axi_wvalid,
    s_axi_wlast_0_sp_1,
    \s_axi_wlast[0]_0 ,
    \gen_no_arbiter.grant_rnw_reg_0 ,
    s_axi_bvalid,
    m_axi_bready,
    \m_ready_d_reg[0] ,
    s_axi_bready_0_sp_1,
    s_axi_awready,
    s_axi_arready,
    \gen_no_arbiter.m_amesg_i_reg[47]_0 ,
    aclk,
    m_ready_d,
    s_ready_i_reg,
    aa_rready,
    aresetn_d,
    \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ,
    s_axi_awvalid,
    s_axi_arvalid,
    \gen_axi.s_axi_awready_i_reg ,
    mi_arready,
    mi_rvalid,
    \gen_no_arbiter.m_valid_i_reg_0 ,
    m_ready_d0_0,
    m_valid_i_reg,
    s_axi_rready,
    sr_rvalid,
    m_ready_d_1,
    \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1 ,
    s_axi_wready_0_sp_1,
    s_axi_wvalid,
    s_axi_wlast,
    s_axi_bvalid_0_sp_1,
    s_axi_bready,
    \gen_axi.s_axi_awready_i_reg_0 ,
    s_axi_arqos,
    s_axi_awqos,
    s_axi_arcache,
    s_axi_awcache,
    s_axi_arburst,
    s_axi_awburst,
    s_axi_arprot,
    s_axi_awprot,
    s_axi_arlock,
    s_axi_awlock,
    s_axi_arsize,
    s_axi_awsize,
    s_axi_arlen,
    s_axi_awlen,
    s_axi_araddr,
    s_axi_awaddr,
    s_axi_arid,
    s_axi_awid);
  output p_0_in1_in;
  output m_valid_i;
  output [0:0]SR;
  output aa_grant_rnw;
  output [3:0]D;
  output \gen_no_arbiter.m_amesg_i_reg[34]_0 ;
  output [68:0]Q;
  output \m_ready_d_reg[1] ;
  output [0:0]m_ready_d0;
  output \gen_no_arbiter.m_amesg_i_reg[27]_0 ;
  output \gen_axi.s_axi_rid_i ;
  output [2:0]m_axi_arvalid;
  output \aresetn_d_reg[1] ;
  output [0:0]E;
  output \aresetn_d_reg[0] ;
  output [2:0]m_axi_awvalid;
  output \m_ready_d_reg[2] ;
  output [0:0]s_axi_wready;
  output [2:0]m_axi_wvalid;
  output s_axi_wlast_0_sp_1;
  output \s_axi_wlast[0]_0 ;
  output \gen_no_arbiter.grant_rnw_reg_0 ;
  output [0:0]s_axi_bvalid;
  output [2:0]m_axi_bready;
  output \m_ready_d_reg[0] ;
  output s_axi_bready_0_sp_1;
  output [0:0]s_axi_awready;
  output [0:0]s_axi_arready;
  output \gen_no_arbiter.m_amesg_i_reg[47]_0 ;
  input aclk;
  input [1:0]m_ready_d;
  input s_ready_i_reg;
  input aa_rready;
  input aresetn_d;
  input \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ;
  input [0:0]s_axi_awvalid;
  input [0:0]s_axi_arvalid;
  input [3:0]\gen_axi.s_axi_awready_i_reg ;
  input [0:0]mi_arready;
  input [0:0]mi_rvalid;
  input \gen_no_arbiter.m_valid_i_reg_0 ;
  input [0:0]m_ready_d0_0;
  input [1:0]m_valid_i_reg;
  input [0:0]s_axi_rready;
  input sr_rvalid;
  input [2:0]m_ready_d_1;
  input \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1 ;
  input s_axi_wready_0_sp_1;
  input [0:0]s_axi_wvalid;
  input [0:0]s_axi_wlast;
  input s_axi_bvalid_0_sp_1;
  input [0:0]s_axi_bready;
  input \gen_axi.s_axi_awready_i_reg_0 ;
  input [3:0]s_axi_arqos;
  input [3:0]s_axi_awqos;
  input [3:0]s_axi_arcache;
  input [3:0]s_axi_awcache;
  input [1:0]s_axi_arburst;
  input [1:0]s_axi_awburst;
  input [2:0]s_axi_arprot;
  input [2:0]s_axi_awprot;
  input [0:0]s_axi_arlock;
  input [0:0]s_axi_awlock;
  input [2:0]s_axi_arsize;
  input [2:0]s_axi_awsize;
  input [7:0]s_axi_arlen;
  input [7:0]s_axi_awlen;
  input [31:0]s_axi_araddr;
  input [31:0]s_axi_awaddr;
  input [11:0]s_axi_arid;
  input [11:0]s_axi_awid;

  wire [3:0]D;
  wire [0:0]E;
  wire [68:0]Q;
  wire [0:0]SR;
  wire aa_grant_rnw;
  wire aa_rready;
  wire aclk;
  wire any_error;
  wire aresetn_d;
  wire \aresetn_d_reg[0] ;
  wire \aresetn_d_reg[1] ;
  wire [3:0]\gen_axi.s_axi_awready_i_reg ;
  wire \gen_axi.s_axi_awready_i_reg_0 ;
  wire \gen_axi.s_axi_rid_i ;
  wire \gen_axi.s_axi_rlast_i_i_4_n_0 ;
  wire \gen_no_arbiter.grant_rnw_i_1_n_0 ;
  wire \gen_no_arbiter.grant_rnw_reg_0 ;
  wire \gen_no_arbiter.m_amesg_i_reg[27]_0 ;
  wire \gen_no_arbiter.m_amesg_i_reg[34]_0 ;
  wire \gen_no_arbiter.m_amesg_i_reg[47]_0 ;
  wire \gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0 ;
  wire \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3_n_0 ;
  wire \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0 ;
  wire \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ;
  wire \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1 ;
  wire \gen_no_arbiter.m_valid_i_i_1_n_0 ;
  wire \gen_no_arbiter.m_valid_i_reg_0 ;
  wire \gen_no_arbiter.s_ready_i[0]_i_1_n_0 ;
  wire \m_atarget_hot[0]_i_2_n_0 ;
  wire \m_atarget_hot[1]_i_3_n_0 ;
  wire \m_atarget_hot[3]_i_3_n_0 ;
  wire \m_atarget_hot[3]_i_4_n_0 ;
  wire \m_atarget_hot[3]_i_5_n_0 ;
  wire [2:0]m_axi_arvalid;
  wire [2:0]m_axi_awvalid;
  wire [2:0]m_axi_bready;
  wire [2:0]m_axi_wvalid;
  wire [1:0]m_ready_d;
  wire [0:0]m_ready_d0;
  wire [0:0]m_ready_d0_0;
  wire [2:0]m_ready_d_1;
  wire \m_ready_d_reg[0] ;
  wire \m_ready_d_reg[1] ;
  wire \m_ready_d_reg[2] ;
  wire m_valid_i;
  wire m_valid_i_i_2_n_0;
  wire [1:0]m_valid_i_reg;
  wire [0:0]mi_arready;
  wire [0:0]mi_rvalid;
  wire p_0_in1_in;
  wire [69:0]s_amesg;
  wire \s_arvalid_reg[0]_i_1_n_0 ;
  wire \s_arvalid_reg_reg_n_0_[0] ;
  wire s_awvalid_reg;
  wire \s_awvalid_reg[0]_i_1_n_0 ;
  wire [31:0]s_axi_araddr;
  wire [1:0]s_axi_arburst;
  wire [3:0]s_axi_arcache;
  wire [11:0]s_axi_arid;
  wire [7:0]s_axi_arlen;
  wire [0:0]s_axi_arlock;
  wire [2:0]s_axi_arprot;
  wire [3:0]s_axi_arqos;
  wire [0:0]s_axi_arready;
  wire [2:0]s_axi_arsize;
  wire [0:0]s_axi_arvalid;
  wire [31:0]s_axi_awaddr;
  wire [1:0]s_axi_awburst;
  wire [3:0]s_axi_awcache;
  wire [11:0]s_axi_awid;
  wire [7:0]s_axi_awlen;
  wire [0:0]s_axi_awlock;
  wire [2:0]s_axi_awprot;
  wire [3:0]s_axi_awqos;
  wire [0:0]s_axi_awready;
  wire [2:0]s_axi_awsize;
  wire [0:0]s_axi_awvalid;
  wire [0:0]s_axi_bready;
  wire s_axi_bready_0_sn_1;
  wire [0:0]s_axi_bvalid;
  wire s_axi_bvalid_0_sn_1;
  wire [0:0]s_axi_rready;
  wire [0:0]s_axi_wlast;
  wire \s_axi_wlast[0]_0 ;
  wire s_axi_wlast_0_sn_1;
  wire [0:0]s_axi_wready;
  wire s_axi_wready_0_sn_1;
  wire [0:0]s_axi_wvalid;
  wire s_ready_i;
  wire s_ready_i_reg;
  wire sr_rvalid;
  wire [1:1]target_mi_enc;

  assign s_axi_bready_0_sp_1 = s_axi_bready_0_sn_1;
  assign s_axi_bvalid_0_sn_1 = s_axi_bvalid_0_sp_1;
  assign s_axi_wlast_0_sp_1 = s_axi_wlast_0_sn_1;
  assign s_axi_wready_0_sn_1 = s_axi_wready_0_sp_1;
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \gen_axi.read_cnt[7]_i_4 
       (.I0(m_ready_d[1]),
        .I1(aa_grant_rnw),
        .I2(m_valid_i),
        .O(\m_ready_d_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hFB)) 
    \gen_axi.s_axi_awready_i_i_2 
       (.I0(m_ready_d_1[2]),
        .I1(m_valid_i),
        .I2(aa_grant_rnw),
        .O(\m_ready_d_reg[2] ));
  LUT6 #(
    .INIT(64'h0400000000000000)) 
    \gen_axi.s_axi_awready_i_i_3 
       (.I0(m_ready_d_1[0]),
        .I1(m_valid_i),
        .I2(aa_grant_rnw),
        .I3(s_axi_bready),
        .I4(\gen_axi.s_axi_awready_i_reg_0 ),
        .I5(\gen_axi.s_axi_awready_i_reg [3]),
        .O(\m_ready_d_reg[0] ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \gen_axi.s_axi_rlast_i_i_2 
       (.I0(Q[47]),
        .I1(Q[44]),
        .I2(Q[46]),
        .I3(Q[45]),
        .I4(\gen_axi.s_axi_rlast_i_i_4_n_0 ),
        .O(\gen_no_arbiter.m_amesg_i_reg[47]_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \gen_axi.s_axi_rlast_i_i_4 
       (.I0(Q[50]),
        .I1(Q[51]),
        .I2(Q[48]),
        .I3(Q[49]),
        .O(\gen_axi.s_axi_rlast_i_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000800000)) 
    \gen_axi.s_axi_rlast_i_i_5 
       (.I0(\gen_axi.s_axi_awready_i_reg [3]),
        .I1(m_valid_i),
        .I2(aa_grant_rnw),
        .I3(m_ready_d[1]),
        .I4(mi_arready),
        .I5(mi_rvalid),
        .O(\gen_axi.s_axi_rid_i ));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT4 #(
    .INIT(16'hFBFF)) 
    \gen_axi.s_axi_wready_i_i_2 
       (.I0(aa_grant_rnw),
        .I1(m_valid_i),
        .I2(m_ready_d_1[1]),
        .I3(s_axi_wvalid),
        .O(\gen_no_arbiter.grant_rnw_reg_0 ));
  LUT6 #(
    .INIT(64'hFFFF47FF00004400)) 
    \gen_no_arbiter.grant_rnw_i_1 
       (.I0(s_awvalid_reg),
        .I1(s_axi_arvalid),
        .I2(s_axi_awvalid),
        .I3(p_0_in1_in),
        .I4(m_valid_i),
        .I5(aa_grant_rnw),
        .O(\gen_no_arbiter.grant_rnw_i_1_n_0 ));
  FDRE \gen_no_arbiter.grant_rnw_reg 
       (.C(aclk),
        .CE(1'b1),
        .D(\gen_no_arbiter.grant_rnw_i_1_n_0 ),
        .Q(aa_grant_rnw),
        .R(SR));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[0]_i_1 
       (.I0(s_axi_arid[0]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awid[0]),
        .O(s_amesg[0]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[10]_i_1 
       (.I0(s_axi_arid[10]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awid[10]),
        .O(s_amesg[10]));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_no_arbiter.m_amesg_i[11]_i_1 
       (.I0(aresetn_d),
        .O(SR));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[11]_i_2 
       (.I0(s_axi_arid[11]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awid[11]),
        .O(s_amesg[11]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[12]_i_1 
       (.I0(s_axi_araddr[0]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[0]),
        .O(s_amesg[12]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[13]_i_1 
       (.I0(s_axi_araddr[1]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[1]),
        .O(s_amesg[13]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[14]_i_1 
       (.I0(s_axi_araddr[2]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[2]),
        .O(s_amesg[14]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[15]_i_1 
       (.I0(s_axi_araddr[3]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[3]),
        .O(s_amesg[15]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[16]_i_1 
       (.I0(s_axi_araddr[4]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[4]),
        .O(s_amesg[16]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[17]_i_1 
       (.I0(s_axi_araddr[5]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[5]),
        .O(s_amesg[17]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[18]_i_1 
       (.I0(s_axi_araddr[6]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[6]),
        .O(s_amesg[18]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[19]_i_1 
       (.I0(s_axi_araddr[7]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[7]),
        .O(s_amesg[19]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[1]_i_1 
       (.I0(s_axi_arid[1]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awid[1]),
        .O(s_amesg[1]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[20]_i_1 
       (.I0(s_axi_araddr[8]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[8]),
        .O(s_amesg[20]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[21]_i_1 
       (.I0(s_axi_araddr[9]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[9]),
        .O(s_amesg[21]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[22]_i_1 
       (.I0(s_axi_araddr[10]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[10]),
        .O(s_amesg[22]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[23]_i_1 
       (.I0(s_axi_araddr[11]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[11]),
        .O(s_amesg[23]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[24]_i_1 
       (.I0(s_axi_araddr[12]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[12]),
        .O(s_amesg[24]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[25]_i_1 
       (.I0(s_axi_araddr[13]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[13]),
        .O(s_amesg[25]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[26]_i_1 
       (.I0(s_axi_araddr[14]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[14]),
        .O(s_amesg[26]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[27]_i_1 
       (.I0(s_axi_araddr[15]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[15]),
        .O(s_amesg[27]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[28]_i_1 
       (.I0(s_axi_araddr[16]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[16]),
        .O(s_amesg[28]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[29]_i_1 
       (.I0(s_axi_araddr[17]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[17]),
        .O(s_amesg[29]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[2]_i_1 
       (.I0(s_axi_arid[2]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awid[2]),
        .O(s_amesg[2]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[30]_i_1 
       (.I0(s_axi_araddr[18]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[18]),
        .O(s_amesg[30]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[31]_i_1 
       (.I0(s_axi_araddr[19]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[19]),
        .O(s_amesg[31]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[32]_i_1 
       (.I0(s_axi_araddr[20]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[20]),
        .O(s_amesg[32]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[33]_i_1 
       (.I0(s_axi_araddr[21]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[21]),
        .O(s_amesg[33]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[34]_i_1 
       (.I0(s_axi_araddr[22]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[22]),
        .O(s_amesg[34]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[35]_i_1 
       (.I0(s_axi_araddr[23]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[23]),
        .O(s_amesg[35]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[36]_i_1 
       (.I0(s_axi_araddr[24]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[24]),
        .O(s_amesg[36]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[37]_i_1 
       (.I0(s_axi_araddr[25]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[25]),
        .O(s_amesg[37]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[38]_i_1 
       (.I0(s_axi_araddr[26]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[26]),
        .O(s_amesg[38]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[39]_i_1 
       (.I0(s_axi_araddr[27]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[27]),
        .O(s_amesg[39]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[3]_i_1 
       (.I0(s_axi_arid[3]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awid[3]),
        .O(s_amesg[3]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[40]_i_1 
       (.I0(s_axi_araddr[28]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[28]),
        .O(s_amesg[40]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[41]_i_1 
       (.I0(s_axi_araddr[29]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[29]),
        .O(s_amesg[41]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[42]_i_1 
       (.I0(s_axi_araddr[30]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[30]),
        .O(s_amesg[42]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[43]_i_1 
       (.I0(s_axi_araddr[31]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awaddr[31]),
        .O(s_amesg[43]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[44]_i_1 
       (.I0(s_axi_arlen[0]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awlen[0]),
        .O(s_amesg[44]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[45]_i_1 
       (.I0(s_axi_arlen[1]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awlen[1]),
        .O(s_amesg[45]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[46]_i_1 
       (.I0(s_axi_arlen[2]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awlen[2]),
        .O(s_amesg[46]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[47]_i_1 
       (.I0(s_axi_arlen[3]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awlen[3]),
        .O(s_amesg[47]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[48]_i_1 
       (.I0(s_axi_arlen[4]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awlen[4]),
        .O(s_amesg[48]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[49]_i_1 
       (.I0(s_axi_arlen[5]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awlen[5]),
        .O(s_amesg[49]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[4]_i_1 
       (.I0(s_axi_arid[4]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awid[4]),
        .O(s_amesg[4]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[50]_i_1 
       (.I0(s_axi_arlen[6]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awlen[6]),
        .O(s_amesg[50]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[51]_i_1 
       (.I0(s_axi_arlen[7]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awlen[7]),
        .O(s_amesg[51]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[52]_i_1 
       (.I0(s_axi_arsize[0]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awsize[0]),
        .O(s_amesg[52]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[53]_i_1 
       (.I0(s_axi_arsize[1]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awsize[1]),
        .O(s_amesg[53]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[54]_i_1 
       (.I0(s_axi_arsize[2]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awsize[2]),
        .O(s_amesg[54]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[55]_i_1 
       (.I0(s_axi_arlock),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awlock),
        .O(s_amesg[55]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[57]_i_1 
       (.I0(s_axi_arprot[0]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awprot[0]),
        .O(s_amesg[57]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[58]_i_1 
       (.I0(s_axi_arprot[1]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awprot[1]),
        .O(s_amesg[58]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[59]_i_1 
       (.I0(s_axi_arprot[2]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awprot[2]),
        .O(s_amesg[59]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[5]_i_1 
       (.I0(s_axi_arid[5]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awid[5]),
        .O(s_amesg[5]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[60]_i_1 
       (.I0(s_axi_arburst[0]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awburst[0]),
        .O(s_amesg[60]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[61]_i_1 
       (.I0(s_axi_arburst[1]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awburst[1]),
        .O(s_amesg[61]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[62]_i_1 
       (.I0(s_axi_arcache[0]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awcache[0]),
        .O(s_amesg[62]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[63]_i_1 
       (.I0(s_axi_arcache[1]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awcache[1]),
        .O(s_amesg[63]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[64]_i_1 
       (.I0(s_axi_arcache[2]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awcache[2]),
        .O(s_amesg[64]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[65]_i_1 
       (.I0(s_axi_arcache[3]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awcache[3]),
        .O(s_amesg[65]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[66]_i_1 
       (.I0(s_axi_arqos[0]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awqos[0]),
        .O(s_amesg[66]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[67]_i_1 
       (.I0(s_axi_arqos[1]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awqos[1]),
        .O(s_amesg[67]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[68]_i_1 
       (.I0(s_axi_arqos[2]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awqos[2]),
        .O(s_amesg[68]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[69]_i_1 
       (.I0(s_axi_arqos[3]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awqos[3]),
        .O(s_amesg[69]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[6]_i_1 
       (.I0(s_axi_arid[6]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awid[6]),
        .O(s_amesg[6]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[7]_i_1 
       (.I0(s_axi_arid[7]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awid[7]),
        .O(s_amesg[7]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[8]_i_1 
       (.I0(s_axi_arid[8]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awid[8]),
        .O(s_amesg[8]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \gen_no_arbiter.m_amesg_i[9]_i_1 
       (.I0(s_axi_arid[9]),
        .I1(s_axi_arvalid),
        .I2(s_awvalid_reg),
        .I3(s_axi_awid[9]),
        .O(s_amesg[9]));
  FDRE \gen_no_arbiter.m_amesg_i_reg[0] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[0]),
        .Q(Q[0]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[10] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[10]),
        .Q(Q[10]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[11] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[11]),
        .Q(Q[11]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[12] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[12]),
        .Q(Q[12]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[13] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[13]),
        .Q(Q[13]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[14] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[14]),
        .Q(Q[14]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[15] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[15]),
        .Q(Q[15]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[16] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[16]),
        .Q(Q[16]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[17] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[17]),
        .Q(Q[17]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[18] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[18]),
        .Q(Q[18]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[19] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[19]),
        .Q(Q[19]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[1] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[1]),
        .Q(Q[1]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[20] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[20]),
        .Q(Q[20]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[21] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[21]),
        .Q(Q[21]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[22] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[22]),
        .Q(Q[22]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[23] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[23]),
        .Q(Q[23]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[24] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[24]),
        .Q(Q[24]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[25] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[25]),
        .Q(Q[25]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[26] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[26]),
        .Q(Q[26]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[27] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[27]),
        .Q(Q[27]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[28] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[28]),
        .Q(Q[28]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[29] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[29]),
        .Q(Q[29]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[2] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[2]),
        .Q(Q[2]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[30] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[30]),
        .Q(Q[30]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[31] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[31]),
        .Q(Q[31]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[32] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[32]),
        .Q(Q[32]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[33] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[33]),
        .Q(Q[33]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[34] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[34]),
        .Q(Q[34]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[35] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[35]),
        .Q(Q[35]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[36] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[36]),
        .Q(Q[36]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[37] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[37]),
        .Q(Q[37]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[38] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[38]),
        .Q(Q[38]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[39] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[39]),
        .Q(Q[39]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[3] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[3]),
        .Q(Q[3]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[40] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[40]),
        .Q(Q[40]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[41] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[41]),
        .Q(Q[41]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[42] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[42]),
        .Q(Q[42]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[43] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[43]),
        .Q(Q[43]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[44] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[44]),
        .Q(Q[44]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[45] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[45]),
        .Q(Q[45]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[46] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[46]),
        .Q(Q[46]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[47] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[47]),
        .Q(Q[47]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[48] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[48]),
        .Q(Q[48]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[49] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[49]),
        .Q(Q[49]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[4] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[4]),
        .Q(Q[4]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[50] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[50]),
        .Q(Q[50]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[51] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[51]),
        .Q(Q[51]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[52] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[52]),
        .Q(Q[52]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[53] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[53]),
        .Q(Q[53]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[54] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[54]),
        .Q(Q[54]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[55] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[55]),
        .Q(Q[55]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[57] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[57]),
        .Q(Q[56]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[58] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[58]),
        .Q(Q[57]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[59] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[59]),
        .Q(Q[58]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[5] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[5]),
        .Q(Q[5]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[60] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[60]),
        .Q(Q[59]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[61] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[61]),
        .Q(Q[60]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[62] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[62]),
        .Q(Q[61]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[63] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[63]),
        .Q(Q[62]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[64] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[64]),
        .Q(Q[63]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[65] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[65]),
        .Q(Q[64]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[66] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[66]),
        .Q(Q[65]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[67] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[67]),
        .Q(Q[66]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[68] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[68]),
        .Q(Q[67]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[69] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[69]),
        .Q(Q[68]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[6] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[6]),
        .Q(Q[6]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[7] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[7]),
        .Q(Q[7]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[8] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[8]),
        .Q(Q[8]),
        .R(SR));
  FDRE \gen_no_arbiter.m_amesg_i_reg[9] 
       (.C(aclk),
        .CE(p_0_in1_in),
        .D(s_amesg[9]),
        .Q(Q[9]),
        .R(SR));
  LUT6 #(
    .INIT(64'hFFFFFFFF0040F040)) 
    \gen_no_arbiter.m_grant_hot_i[0]_inv_i_1 
       (.I0(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ),
        .I1(m_ready_d0),
        .I2(m_valid_i),
        .I3(aa_grant_rnw),
        .I4(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_3_n_0 ),
        .I5(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0 ),
        .O(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT5 #(
    .INIT(32'h0F07FFFF)) 
    \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3 
       (.I0(m_valid_i),
        .I1(aa_grant_rnw),
        .I2(m_ready_d[1]),
        .I3(\gen_no_arbiter.m_valid_i_reg_0 ),
        .I4(m_ready_d0_0),
        .O(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT5 #(
    .INIT(32'hD5D5D5F5)) 
    \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4 
       (.I0(aresetn_d),
        .I1(m_valid_i),
        .I2(p_0_in1_in),
        .I3(s_axi_awvalid),
        .I4(s_axi_arvalid),
        .O(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT5 #(
    .INIT(32'h00000800)) 
    \gen_no_arbiter.m_grant_hot_i[0]_inv_i_5 
       (.I0(s_axi_wlast),
        .I1(s_axi_wvalid),
        .I2(m_ready_d_1[1]),
        .I3(m_valid_i),
        .I4(aa_grant_rnw),
        .O(\s_axi_wlast[0]_0 ));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \gen_no_arbiter.m_grant_hot_i_reg[0]_inv 
       (.C(aclk),
        .CE(1'b1),
        .D(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0 ),
        .Q(p_0_in1_in),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFF55CF550055CF55)) 
    \gen_no_arbiter.m_valid_i_i_1 
       (.I0(p_0_in1_in),
        .I1(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ),
        .I2(m_ready_d0),
        .I3(m_valid_i),
        .I4(aa_grant_rnw),
        .I5(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_3_n_0 ),
        .O(\gen_no_arbiter.m_valid_i_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \gen_no_arbiter.m_valid_i_reg 
       (.C(aclk),
        .CE(1'b1),
        .D(\gen_no_arbiter.m_valid_i_i_1_n_0 ),
        .Q(m_valid_i),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'h10)) 
    \gen_no_arbiter.s_ready_i[0]_i_1 
       (.I0(m_valid_i),
        .I1(p_0_in1_in),
        .I2(aresetn_d),
        .O(\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \gen_no_arbiter.s_ready_i_reg[0] 
       (.C(aclk),
        .CE(1'b1),
        .D(\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ),
        .Q(s_ready_i),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \m_atarget_enc[1]_i_2 
       (.I0(Q[27]),
        .I1(Q[28]),
        .I2(Q[43]),
        .I3(Q[30]),
        .I4(\m_atarget_hot[3]_i_4_n_0 ),
        .O(\gen_no_arbiter.m_amesg_i_reg[27]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \m_atarget_hot[0]_i_1 
       (.I0(\m_atarget_hot[1]_i_3_n_0 ),
        .I1(p_0_in1_in),
        .I2(\m_atarget_hot[0]_i_2_n_0 ),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \m_atarget_hot[0]_i_2 
       (.I0(Q[37]),
        .I1(Q[32]),
        .I2(Q[33]),
        .I3(Q[36]),
        .I4(Q[35]),
        .I5(Q[34]),
        .O(\m_atarget_hot[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \m_atarget_hot[1]_i_1 
       (.I0(\gen_no_arbiter.m_amesg_i_reg[34]_0 ),
        .I1(\m_atarget_hot[1]_i_3_n_0 ),
        .I2(Q[37]),
        .I3(p_0_in1_in),
        .O(D[1]));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \m_atarget_hot[1]_i_2 
       (.I0(Q[34]),
        .I1(Q[35]),
        .I2(Q[36]),
        .I3(Q[33]),
        .I4(Q[32]),
        .O(\gen_no_arbiter.m_amesg_i_reg[34]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \m_atarget_hot[1]_i_3 
       (.I0(Q[38]),
        .I1(\m_atarget_hot[3]_i_4_n_0 ),
        .I2(Q[30]),
        .I3(Q[43]),
        .I4(Q[28]),
        .I5(Q[27]),
        .O(\m_atarget_hot[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \m_atarget_hot[2]_i_1 
       (.I0(target_mi_enc),
        .I1(p_0_in1_in),
        .O(D[2]));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \m_atarget_hot[2]_i_2 
       (.I0(\m_atarget_hot[3]_i_4_n_0 ),
        .I1(\m_atarget_hot[3]_i_5_n_0 ),
        .I2(Q[26]),
        .I3(Q[38]),
        .I4(Q[25]),
        .I5(\m_atarget_hot[0]_i_2_n_0 ),
        .O(target_mi_enc));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \m_atarget_hot[3]_i_1 
       (.I0(any_error),
        .I1(p_0_in1_in),
        .O(D[3]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFE0)) 
    \m_atarget_hot[3]_i_2 
       (.I0(Q[37]),
        .I1(\m_atarget_hot[3]_i_3_n_0 ),
        .I2(Q[38]),
        .I3(\m_atarget_hot[3]_i_4_n_0 ),
        .I4(\m_atarget_hot[3]_i_5_n_0 ),
        .I5(\gen_no_arbiter.m_amesg_i_reg[34]_0 ),
        .O(any_error));
  LUT3 #(
    .INIT(8'hFB)) 
    \m_atarget_hot[3]_i_3 
       (.I0(Q[26]),
        .I1(Q[38]),
        .I2(Q[25]),
        .O(\m_atarget_hot[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \m_atarget_hot[3]_i_4 
       (.I0(Q[31]),
        .I1(Q[40]),
        .I2(Q[41]),
        .I3(Q[42]),
        .I4(Q[39]),
        .I5(Q[29]),
        .O(\m_atarget_hot[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \m_atarget_hot[3]_i_5 
       (.I0(Q[30]),
        .I1(Q[43]),
        .I2(Q[28]),
        .I3(Q[27]),
        .O(\m_atarget_hot[3]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \m_axi_arvalid[0]_INST_0 
       (.I0(\gen_axi.s_axi_awready_i_reg [0]),
        .I1(m_valid_i),
        .I2(aa_grant_rnw),
        .I3(m_ready_d[1]),
        .O(m_axi_arvalid[0]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \m_axi_arvalid[1]_INST_0 
       (.I0(\gen_axi.s_axi_awready_i_reg [1]),
        .I1(m_valid_i),
        .I2(aa_grant_rnw),
        .I3(m_ready_d[1]),
        .O(m_axi_arvalid[1]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \m_axi_arvalid[2]_INST_0 
       (.I0(\gen_axi.s_axi_awready_i_reg [2]),
        .I1(m_valid_i),
        .I2(aa_grant_rnw),
        .I3(m_ready_d[1]),
        .O(m_axi_arvalid[2]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT4 #(
    .INIT(16'h0020)) 
    \m_axi_awvalid[0]_INST_0 
       (.I0(\gen_axi.s_axi_awready_i_reg [0]),
        .I1(aa_grant_rnw),
        .I2(m_valid_i),
        .I3(m_ready_d_1[2]),
        .O(m_axi_awvalid[0]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT4 #(
    .INIT(16'h0020)) 
    \m_axi_awvalid[1]_INST_0 
       (.I0(\gen_axi.s_axi_awready_i_reg [1]),
        .I1(aa_grant_rnw),
        .I2(m_valid_i),
        .I3(m_ready_d_1[2]),
        .O(m_axi_awvalid[1]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT4 #(
    .INIT(16'h0020)) 
    \m_axi_awvalid[2]_INST_0 
       (.I0(\gen_axi.s_axi_awready_i_reg [2]),
        .I1(aa_grant_rnw),
        .I2(m_valid_i),
        .I3(m_ready_d_1[2]),
        .O(m_axi_awvalid[2]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \m_axi_bready[0]_INST_0 
       (.I0(\gen_axi.s_axi_awready_i_reg [0]),
        .I1(m_ready_d_1[0]),
        .I2(m_valid_i),
        .I3(aa_grant_rnw),
        .I4(s_axi_bready),
        .O(m_axi_bready[0]));
  LUT5 #(
    .INIT(32'h00200000)) 
    \m_axi_bready[1]_INST_0 
       (.I0(\gen_axi.s_axi_awready_i_reg [1]),
        .I1(m_ready_d_1[0]),
        .I2(m_valid_i),
        .I3(aa_grant_rnw),
        .I4(s_axi_bready),
        .O(m_axi_bready[1]));
  LUT5 #(
    .INIT(32'h00200000)) 
    \m_axi_bready[2]_INST_0 
       (.I0(\gen_axi.s_axi_awready_i_reg [2]),
        .I1(m_ready_d_1[0]),
        .I2(m_valid_i),
        .I3(aa_grant_rnw),
        .I4(s_axi_bready),
        .O(m_axi_bready[2]));
  LUT5 #(
    .INIT(32'h00000800)) 
    \m_axi_wvalid[0]_INST_0 
       (.I0(\gen_axi.s_axi_awready_i_reg [0]),
        .I1(s_axi_wvalid),
        .I2(m_ready_d_1[1]),
        .I3(m_valid_i),
        .I4(aa_grant_rnw),
        .O(m_axi_wvalid[0]));
  LUT5 #(
    .INIT(32'h00000800)) 
    \m_axi_wvalid[1]_INST_0 
       (.I0(\gen_axi.s_axi_awready_i_reg [1]),
        .I1(s_axi_wvalid),
        .I2(m_ready_d_1[1]),
        .I3(m_valid_i),
        .I4(aa_grant_rnw),
        .O(m_axi_wvalid[1]));
  LUT5 #(
    .INIT(32'h00000800)) 
    \m_axi_wvalid[2]_INST_0 
       (.I0(\gen_axi.s_axi_awready_i_reg [2]),
        .I1(s_axi_wvalid),
        .I2(m_ready_d_1[1]),
        .I3(m_valid_i),
        .I4(aa_grant_rnw),
        .O(m_axi_wvalid[2]));
  LUT5 #(
    .INIT(32'h4000FFFF)) 
    \m_payload_i[34]_i_1 
       (.I0(m_ready_d[0]),
        .I1(aa_grant_rnw),
        .I2(m_valid_i),
        .I3(s_axi_rready),
        .I4(sr_rvalid),
        .O(E));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT4 #(
    .INIT(16'hBAAA)) 
    \m_ready_d[2]_i_2 
       (.I0(m_ready_d_1[2]),
        .I1(aa_grant_rnw),
        .I2(m_valid_i),
        .I3(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1 ),
        .O(m_ready_d0));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT4 #(
    .INIT(16'h0020)) 
    \m_ready_d[2]_i_3 
       (.I0(s_axi_bready),
        .I1(aa_grant_rnw),
        .I2(m_valid_i),
        .I3(m_ready_d_1[0]),
        .O(s_axi_bready_0_sn_1));
  LUT6 #(
    .INIT(64'h0F0F070F0F0F0F0F)) 
    \m_ready_d[2]_i_4 
       (.I0(s_axi_wlast),
        .I1(s_axi_wvalid),
        .I2(m_ready_d_1[1]),
        .I3(m_valid_i),
        .I4(aa_grant_rnw),
        .I5(s_axi_wready_0_sn_1),
        .O(s_axi_wlast_0_sn_1));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    m_valid_i_i_1
       (.I0(m_valid_i_reg[1]),
        .I1(m_valid_i_i_2_n_0),
        .I2(E),
        .O(\aresetn_d_reg[1] ));
  LUT5 #(
    .INIT(32'h4000FFFF)) 
    m_valid_i_i_2
       (.I0(m_ready_d[0]),
        .I1(aa_grant_rnw),
        .I2(m_valid_i),
        .I3(s_ready_i_reg),
        .I4(aa_rready),
        .O(m_valid_i_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    \s_arvalid_reg[0]_i_1 
       (.I0(s_awvalid_reg),
        .I1(s_axi_arvalid),
        .I2(aresetn_d),
        .I3(s_ready_i),
        .O(\s_arvalid_reg[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \s_arvalid_reg_reg[0] 
       (.C(aclk),
        .CE(1'b1),
        .D(\s_arvalid_reg[0]_i_1_n_0 ),
        .Q(\s_arvalid_reg_reg_n_0_[0] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000D00000)) 
    \s_awvalid_reg[0]_i_1 
       (.I0(s_axi_arvalid),
        .I1(s_awvalid_reg),
        .I2(s_axi_awvalid),
        .I3(\s_arvalid_reg_reg_n_0_[0] ),
        .I4(aresetn_d),
        .I5(s_ready_i),
        .O(\s_awvalid_reg[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \s_awvalid_reg_reg[0] 
       (.C(aclk),
        .CE(1'b1),
        .D(\s_awvalid_reg[0]_i_1_n_0 ),
        .Q(s_awvalid_reg),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h8)) 
    \s_axi_arready[0]_INST_0 
       (.I0(aa_grant_rnw),
        .I1(s_ready_i),
        .O(s_axi_arready));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \s_axi_awready[0]_INST_0 
       (.I0(s_ready_i),
        .I1(aa_grant_rnw),
        .O(s_axi_awready));
  LUT5 #(
    .INIT(32'h00000004)) 
    \s_axi_bvalid[0]_INST_0 
       (.I0(m_ready_d_1[0]),
        .I1(m_valid_i),
        .I2(aa_grant_rnw),
        .I3(p_0_in1_in),
        .I4(s_axi_bvalid_0_sn_1),
        .O(s_axi_bvalid));
  LUT5 #(
    .INIT(32'h00000200)) 
    \s_axi_wready[0]_INST_0 
       (.I0(s_axi_wready_0_sn_1),
        .I1(p_0_in1_in),
        .I2(m_ready_d_1[1]),
        .I3(m_valid_i),
        .I4(aa_grant_rnw),
        .O(s_axi_wready));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    s_ready_i_i_1
       (.I0(m_valid_i_reg[0]),
        .I1(E),
        .I2(m_valid_i_i_2_n_0),
        .O(\aresetn_d_reg[0] ));
endmodule

(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) 
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *) 
(* C_AXI_PROTOCOL = "0" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *) 
(* C_AXI_WUSER_WIDTH = "1" *) (* C_CONNECTIVITY_MODE = "0" *) (* C_DEBUG = "1" *) 
(* C_FAMILY = "zynq" *) (* C_M_AXI_ADDR_WIDTH = "96'b000000000000000000000000000011010000000000000000000000000000111100000000000000000000000000001111" *) (* C_M_AXI_BASE_ADDR = "192'b000000000000000000000000000000000100010000000000000000000000000000000000000000000000000000000000010000100000000000000000000000000000000000000000000000000000000001000000000000000000000000000000" *) 
(* C_M_AXI_READ_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_READ_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_SECURE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) 
(* C_M_AXI_WRITE_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_WRITE_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_NUM_ADDR_RANGES = "1" *) 
(* C_NUM_MASTER_SLOTS = "3" *) (* C_NUM_SLAVE_SLOTS = "1" *) (* C_R_REGISTER = "1" *) 
(* C_S_AXI_ARB_PRIORITY = "0" *) (* C_S_AXI_BASE_ID = "0" *) (* C_S_AXI_READ_ACCEPTANCE = "1" *) 
(* C_S_AXI_SINGLE_THREAD = "1" *) (* C_S_AXI_THREAD_ID_WIDTH = "12" *) (* C_S_AXI_WRITE_ACCEPTANCE = "1" *) 
(* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "axi_crossbar_v2_1_23_axi_crossbar" *) (* P_ADDR_DECODE = "1" *) 
(* P_AXI3 = "1" *) (* P_AXI4 = "0" *) (* P_AXILITE = "2" *) 
(* P_AXILITE_SIZE = "3'b010" *) (* P_FAMILY = "zynq" *) (* P_INCR = "2'b01" *) 
(* P_LEN = "8" *) (* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) 
(* P_M_AXI_SUPPORTS_READ = "3'b111" *) (* P_M_AXI_SUPPORTS_WRITE = "3'b111" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) 
(* P_RANGE_CHECK = "1" *) (* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000111111111111" *) 
(* P_S_AXI_SUPPORTS_READ = "1'b1" *) (* P_S_AXI_SUPPORTS_WRITE = "1'b1" *) 
module blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar
   (aclk,
    aresetn,
    s_axi_awid,
    s_axi_awaddr,
    s_axi_awlen,
    s_axi_awsize,
    s_axi_awburst,
    s_axi_awlock,
    s_axi_awcache,
    s_axi_awprot,
    s_axi_awqos,
    s_axi_awuser,
    s_axi_awvalid,
    s_axi_awready,
    s_axi_wid,
    s_axi_wdata,
    s_axi_wstrb,
    s_axi_wlast,
    s_axi_wuser,
    s_axi_wvalid,
    s_axi_wready,
    s_axi_bid,
    s_axi_bresp,
    s_axi_buser,
    s_axi_bvalid,
    s_axi_bready,
    s_axi_arid,
    s_axi_araddr,
    s_axi_arlen,
    s_axi_arsize,
    s_axi_arburst,
    s_axi_arlock,
    s_axi_arcache,
    s_axi_arprot,
    s_axi_arqos,
    s_axi_aruser,
    s_axi_arvalid,
    s_axi_arready,
    s_axi_rid,
    s_axi_rdata,
    s_axi_rresp,
    s_axi_rlast,
    s_axi_ruser,
    s_axi_rvalid,
    s_axi_rready,
    m_axi_awid,
    m_axi_awaddr,
    m_axi_awlen,
    m_axi_awsize,
    m_axi_awburst,
    m_axi_awlock,
    m_axi_awcache,
    m_axi_awprot,
    m_axi_awregion,
    m_axi_awqos,
    m_axi_awuser,
    m_axi_awvalid,
    m_axi_awready,
    m_axi_wid,
    m_axi_wdata,
    m_axi_wstrb,
    m_axi_wlast,
    m_axi_wuser,
    m_axi_wvalid,
    m_axi_wready,
    m_axi_bid,
    m_axi_bresp,
    m_axi_buser,
    m_axi_bvalid,
    m_axi_bready,
    m_axi_arid,
    m_axi_araddr,
    m_axi_arlen,
    m_axi_arsize,
    m_axi_arburst,
    m_axi_arlock,
    m_axi_arcache,
    m_axi_arprot,
    m_axi_arregion,
    m_axi_arqos,
    m_axi_aruser,
    m_axi_arvalid,
    m_axi_arready,
    m_axi_rid,
    m_axi_rdata,
    m_axi_rresp,
    m_axi_rlast,
    m_axi_ruser,
    m_axi_rvalid,
    m_axi_rready);
  input aclk;
  input aresetn;
  input [11:0]s_axi_awid;
  input [31:0]s_axi_awaddr;
  input [7:0]s_axi_awlen;
  input [2:0]s_axi_awsize;
  input [1:0]s_axi_awburst;
  input [0:0]s_axi_awlock;
  input [3:0]s_axi_awcache;
  input [2:0]s_axi_awprot;
  input [3:0]s_axi_awqos;
  input [0:0]s_axi_awuser;
  input [0:0]s_axi_awvalid;
  output [0:0]s_axi_awready;
  input [11:0]s_axi_wid;
  input [31:0]s_axi_wdata;
  input [3:0]s_axi_wstrb;
  input [0:0]s_axi_wlast;
  input [0:0]s_axi_wuser;
  input [0:0]s_axi_wvalid;
  output [0:0]s_axi_wready;
  output [11:0]s_axi_bid;
  output [1:0]s_axi_bresp;
  output [0:0]s_axi_buser;
  output [0:0]s_axi_bvalid;
  input [0:0]s_axi_bready;
  input [11:0]s_axi_arid;
  input [31:0]s_axi_araddr;
  input [7:0]s_axi_arlen;
  input [2:0]s_axi_arsize;
  input [1:0]s_axi_arburst;
  input [0:0]s_axi_arlock;
  input [3:0]s_axi_arcache;
  input [2:0]s_axi_arprot;
  input [3:0]s_axi_arqos;
  input [0:0]s_axi_aruser;
  input [0:0]s_axi_arvalid;
  output [0:0]s_axi_arready;
  output [11:0]s_axi_rid;
  output [31:0]s_axi_rdata;
  output [1:0]s_axi_rresp;
  output [0:0]s_axi_rlast;
  output [0:0]s_axi_ruser;
  output [0:0]s_axi_rvalid;
  input [0:0]s_axi_rready;
  output [35:0]m_axi_awid;
  output [95:0]m_axi_awaddr;
  output [23:0]m_axi_awlen;
  output [8:0]m_axi_awsize;
  output [5:0]m_axi_awburst;
  output [2:0]m_axi_awlock;
  output [11:0]m_axi_awcache;
  output [8:0]m_axi_awprot;
  output [11:0]m_axi_awregion;
  output [11:0]m_axi_awqos;
  output [2:0]m_axi_awuser;
  output [2:0]m_axi_awvalid;
  input [2:0]m_axi_awready;
  output [35:0]m_axi_wid;
  output [95:0]m_axi_wdata;
  output [11:0]m_axi_wstrb;
  output [2:0]m_axi_wlast;
  output [2:0]m_axi_wuser;
  output [2:0]m_axi_wvalid;
  input [2:0]m_axi_wready;
  input [35:0]m_axi_bid;
  input [5:0]m_axi_bresp;
  input [2:0]m_axi_buser;
  input [2:0]m_axi_bvalid;
  output [2:0]m_axi_bready;
  output [35:0]m_axi_arid;
  output [95:0]m_axi_araddr;
  output [23:0]m_axi_arlen;
  output [8:0]m_axi_arsize;
  output [5:0]m_axi_arburst;
  output [2:0]m_axi_arlock;
  output [11:0]m_axi_arcache;
  output [8:0]m_axi_arprot;
  output [11:0]m_axi_arregion;
  output [11:0]m_axi_arqos;
  output [2:0]m_axi_aruser;
  output [2:0]m_axi_arvalid;
  input [2:0]m_axi_arready;
  input [35:0]m_axi_rid;
  input [95:0]m_axi_rdata;
  input [5:0]m_axi_rresp;
  input [2:0]m_axi_rlast;
  input [2:0]m_axi_ruser;
  input [2:0]m_axi_rvalid;
  output [2:0]m_axi_rready;

  wire \<const0> ;
  wire aclk;
  wire aresetn;
  wire [12:0]\^m_axi_araddr ;
  wire [1:0]\^m_axi_arburst ;
  wire [3:0]\^m_axi_arcache ;
  wire [0:0]\^m_axi_arlock ;
  wire [2:0]\^m_axi_arprot ;
  wire [3:0]\^m_axi_arqos ;
  wire [2:0]m_axi_arready;
  wire [2:0]\^m_axi_arsize ;
  wire [2:0]m_axi_arvalid;
  wire [95:77]\^m_axi_awaddr ;
  wire [23:16]\^m_axi_awlen ;
  wire [2:0]m_axi_awready;
  wire [2:0]m_axi_awvalid;
  wire [2:0]m_axi_bready;
  wire [5:0]m_axi_bresp;
  wire [2:0]m_axi_bvalid;
  wire [95:0]m_axi_rdata;
  wire [2:0]m_axi_rlast;
  wire [2:0]m_axi_rready;
  wire [5:0]m_axi_rresp;
  wire [2:0]m_axi_rvalid;
  wire [2:0]m_axi_wready;
  wire [2:0]m_axi_wvalid;
  wire [31:0]s_axi_araddr;
  wire [1:0]s_axi_arburst;
  wire [3:0]s_axi_arcache;
  wire [11:0]s_axi_arid;
  wire [7:0]s_axi_arlen;
  wire [0:0]s_axi_arlock;
  wire [2:0]s_axi_arprot;
  wire [3:0]s_axi_arqos;
  wire [0:0]s_axi_arready;
  wire [2:0]s_axi_arsize;
  wire [0:0]s_axi_arvalid;
  wire [31:0]s_axi_awaddr;
  wire [1:0]s_axi_awburst;
  wire [3:0]s_axi_awcache;
  wire [11:0]s_axi_awid;
  wire [7:0]s_axi_awlen;
  wire [0:0]s_axi_awlock;
  wire [2:0]s_axi_awprot;
  wire [3:0]s_axi_awqos;
  wire [0:0]s_axi_awready;
  wire [2:0]s_axi_awsize;
  wire [0:0]s_axi_awvalid;
  wire [0:0]s_axi_bready;
  wire [1:0]s_axi_bresp;
  wire [0:0]s_axi_bvalid;
  wire [31:0]s_axi_rdata;
  wire [11:0]s_axi_rid;
  wire [0:0]s_axi_rlast;
  wire [0:0]s_axi_rready;
  wire [1:0]s_axi_rresp;
  wire [0:0]s_axi_rvalid;
  wire [31:0]s_axi_wdata;
  wire [0:0]s_axi_wlast;
  wire [0:0]s_axi_wready;
  wire [3:0]s_axi_wstrb;
  wire [0:0]s_axi_wvalid;

  assign m_axi_araddr[95:77] = \^m_axi_awaddr [95:77];
  assign m_axi_araddr[76:64] = \^m_axi_araddr [12:0];
  assign m_axi_araddr[63:45] = \^m_axi_awaddr [95:77];
  assign m_axi_araddr[44:32] = \^m_axi_araddr [12:0];
  assign m_axi_araddr[31:13] = \^m_axi_awaddr [95:77];
  assign m_axi_araddr[12:0] = \^m_axi_araddr [12:0];
  assign m_axi_arburst[5:4] = \^m_axi_arburst [1:0];
  assign m_axi_arburst[3:2] = \^m_axi_arburst [1:0];
  assign m_axi_arburst[1:0] = \^m_axi_arburst [1:0];
  assign m_axi_arcache[11:8] = \^m_axi_arcache [3:0];
  assign m_axi_arcache[7:4] = \^m_axi_arcache [3:0];
  assign m_axi_arcache[3:0] = \^m_axi_arcache [3:0];
  assign m_axi_arid[35] = \<const0> ;
  assign m_axi_arid[34] = \<const0> ;
  assign m_axi_arid[33] = \<const0> ;
  assign m_axi_arid[32] = \<const0> ;
  assign m_axi_arid[31] = \<const0> ;
  assign m_axi_arid[30] = \<const0> ;
  assign m_axi_arid[29] = \<const0> ;
  assign m_axi_arid[28] = \<const0> ;
  assign m_axi_arid[27] = \<const0> ;
  assign m_axi_arid[26] = \<const0> ;
  assign m_axi_arid[25] = \<const0> ;
  assign m_axi_arid[24] = \<const0> ;
  assign m_axi_arid[23] = \<const0> ;
  assign m_axi_arid[22] = \<const0> ;
  assign m_axi_arid[21] = \<const0> ;
  assign m_axi_arid[20] = \<const0> ;
  assign m_axi_arid[19] = \<const0> ;
  assign m_axi_arid[18] = \<const0> ;
  assign m_axi_arid[17] = \<const0> ;
  assign m_axi_arid[16] = \<const0> ;
  assign m_axi_arid[15] = \<const0> ;
  assign m_axi_arid[14] = \<const0> ;
  assign m_axi_arid[13] = \<const0> ;
  assign m_axi_arid[12] = \<const0> ;
  assign m_axi_arid[11] = \<const0> ;
  assign m_axi_arid[10] = \<const0> ;
  assign m_axi_arid[9] = \<const0> ;
  assign m_axi_arid[8] = \<const0> ;
  assign m_axi_arid[7] = \<const0> ;
  assign m_axi_arid[6] = \<const0> ;
  assign m_axi_arid[5] = \<const0> ;
  assign m_axi_arid[4] = \<const0> ;
  assign m_axi_arid[3] = \<const0> ;
  assign m_axi_arid[2] = \<const0> ;
  assign m_axi_arid[1] = \<const0> ;
  assign m_axi_arid[0] = \<const0> ;
  assign m_axi_arlen[23:16] = \^m_axi_awlen [23:16];
  assign m_axi_arlen[15:8] = \^m_axi_awlen [23:16];
  assign m_axi_arlen[7:0] = \^m_axi_awlen [23:16];
  assign m_axi_arlock[2] = \^m_axi_arlock [0];
  assign m_axi_arlock[1] = \^m_axi_arlock [0];
  assign m_axi_arlock[0] = \^m_axi_arlock [0];
  assign m_axi_arprot[8:6] = \^m_axi_arprot [2:0];
  assign m_axi_arprot[5:3] = \^m_axi_arprot [2:0];
  assign m_axi_arprot[2:0] = \^m_axi_arprot [2:0];
  assign m_axi_arqos[11:8] = \^m_axi_arqos [3:0];
  assign m_axi_arqos[7:4] = \^m_axi_arqos [3:0];
  assign m_axi_arqos[3:0] = \^m_axi_arqos [3:0];
  assign m_axi_arregion[11] = \<const0> ;
  assign m_axi_arregion[10] = \<const0> ;
  assign m_axi_arregion[9] = \<const0> ;
  assign m_axi_arregion[8] = \<const0> ;
  assign m_axi_arregion[7] = \<const0> ;
  assign m_axi_arregion[6] = \<const0> ;
  assign m_axi_arregion[5] = \<const0> ;
  assign m_axi_arregion[4] = \<const0> ;
  assign m_axi_arregion[3] = \<const0> ;
  assign m_axi_arregion[2] = \<const0> ;
  assign m_axi_arregion[1] = \<const0> ;
  assign m_axi_arregion[0] = \<const0> ;
  assign m_axi_arsize[8:6] = \^m_axi_arsize [2:0];
  assign m_axi_arsize[5:3] = \^m_axi_arsize [2:0];
  assign m_axi_arsize[2:0] = \^m_axi_arsize [2:0];
  assign m_axi_aruser[2] = \<const0> ;
  assign m_axi_aruser[1] = \<const0> ;
  assign m_axi_aruser[0] = \<const0> ;
  assign m_axi_awaddr[95:77] = \^m_axi_awaddr [95:77];
  assign m_axi_awaddr[76:64] = \^m_axi_araddr [12:0];
  assign m_axi_awaddr[63:45] = \^m_axi_awaddr [95:77];
  assign m_axi_awaddr[44:32] = \^m_axi_araddr [12:0];
  assign m_axi_awaddr[31:13] = \^m_axi_awaddr [95:77];
  assign m_axi_awaddr[12:0] = \^m_axi_araddr [12:0];
  assign m_axi_awburst[5:4] = \^m_axi_arburst [1:0];
  assign m_axi_awburst[3:2] = \^m_axi_arburst [1:0];
  assign m_axi_awburst[1:0] = \^m_axi_arburst [1:0];
  assign m_axi_awcache[11:8] = \^m_axi_arcache [3:0];
  assign m_axi_awcache[7:4] = \^m_axi_arcache [3:0];
  assign m_axi_awcache[3:0] = \^m_axi_arcache [3:0];
  assign m_axi_awid[35] = \<const0> ;
  assign m_axi_awid[34] = \<const0> ;
  assign m_axi_awid[33] = \<const0> ;
  assign m_axi_awid[32] = \<const0> ;
  assign m_axi_awid[31] = \<const0> ;
  assign m_axi_awid[30] = \<const0> ;
  assign m_axi_awid[29] = \<const0> ;
  assign m_axi_awid[28] = \<const0> ;
  assign m_axi_awid[27] = \<const0> ;
  assign m_axi_awid[26] = \<const0> ;
  assign m_axi_awid[25] = \<const0> ;
  assign m_axi_awid[24] = \<const0> ;
  assign m_axi_awid[23] = \<const0> ;
  assign m_axi_awid[22] = \<const0> ;
  assign m_axi_awid[21] = \<const0> ;
  assign m_axi_awid[20] = \<const0> ;
  assign m_axi_awid[19] = \<const0> ;
  assign m_axi_awid[18] = \<const0> ;
  assign m_axi_awid[17] = \<const0> ;
  assign m_axi_awid[16] = \<const0> ;
  assign m_axi_awid[15] = \<const0> ;
  assign m_axi_awid[14] = \<const0> ;
  assign m_axi_awid[13] = \<const0> ;
  assign m_axi_awid[12] = \<const0> ;
  assign m_axi_awid[11] = \<const0> ;
  assign m_axi_awid[10] = \<const0> ;
  assign m_axi_awid[9] = \<const0> ;
  assign m_axi_awid[8] = \<const0> ;
  assign m_axi_awid[7] = \<const0> ;
  assign m_axi_awid[6] = \<const0> ;
  assign m_axi_awid[5] = \<const0> ;
  assign m_axi_awid[4] = \<const0> ;
  assign m_axi_awid[3] = \<const0> ;
  assign m_axi_awid[2] = \<const0> ;
  assign m_axi_awid[1] = \<const0> ;
  assign m_axi_awid[0] = \<const0> ;
  assign m_axi_awlen[23:16] = \^m_axi_awlen [23:16];
  assign m_axi_awlen[15:8] = \^m_axi_awlen [23:16];
  assign m_axi_awlen[7:0] = \^m_axi_awlen [23:16];
  assign m_axi_awlock[2] = \^m_axi_arlock [0];
  assign m_axi_awlock[1] = \^m_axi_arlock [0];
  assign m_axi_awlock[0] = \^m_axi_arlock [0];
  assign m_axi_awprot[8:6] = \^m_axi_arprot [2:0];
  assign m_axi_awprot[5:3] = \^m_axi_arprot [2:0];
  assign m_axi_awprot[2:0] = \^m_axi_arprot [2:0];
  assign m_axi_awqos[11:8] = \^m_axi_arqos [3:0];
  assign m_axi_awqos[7:4] = \^m_axi_arqos [3:0];
  assign m_axi_awqos[3:0] = \^m_axi_arqos [3:0];
  assign m_axi_awregion[11] = \<const0> ;
  assign m_axi_awregion[10] = \<const0> ;
  assign m_axi_awregion[9] = \<const0> ;
  assign m_axi_awregion[8] = \<const0> ;
  assign m_axi_awregion[7] = \<const0> ;
  assign m_axi_awregion[6] = \<const0> ;
  assign m_axi_awregion[5] = \<const0> ;
  assign m_axi_awregion[4] = \<const0> ;
  assign m_axi_awregion[3] = \<const0> ;
  assign m_axi_awregion[2] = \<const0> ;
  assign m_axi_awregion[1] = \<const0> ;
  assign m_axi_awregion[0] = \<const0> ;
  assign m_axi_awsize[8:6] = \^m_axi_arsize [2:0];
  assign m_axi_awsize[5:3] = \^m_axi_arsize [2:0];
  assign m_axi_awsize[2:0] = \^m_axi_arsize [2:0];
  assign m_axi_awuser[2] = \<const0> ;
  assign m_axi_awuser[1] = \<const0> ;
  assign m_axi_awuser[0] = \<const0> ;
  assign m_axi_wdata[95:64] = s_axi_wdata;
  assign m_axi_wdata[63:32] = s_axi_wdata;
  assign m_axi_wdata[31:0] = s_axi_wdata;
  assign m_axi_wid[35] = \<const0> ;
  assign m_axi_wid[34] = \<const0> ;
  assign m_axi_wid[33] = \<const0> ;
  assign m_axi_wid[32] = \<const0> ;
  assign m_axi_wid[31] = \<const0> ;
  assign m_axi_wid[30] = \<const0> ;
  assign m_axi_wid[29] = \<const0> ;
  assign m_axi_wid[28] = \<const0> ;
  assign m_axi_wid[27] = \<const0> ;
  assign m_axi_wid[26] = \<const0> ;
  assign m_axi_wid[25] = \<const0> ;
  assign m_axi_wid[24] = \<const0> ;
  assign m_axi_wid[23] = \<const0> ;
  assign m_axi_wid[22] = \<const0> ;
  assign m_axi_wid[21] = \<const0> ;
  assign m_axi_wid[20] = \<const0> ;
  assign m_axi_wid[19] = \<const0> ;
  assign m_axi_wid[18] = \<const0> ;
  assign m_axi_wid[17] = \<const0> ;
  assign m_axi_wid[16] = \<const0> ;
  assign m_axi_wid[15] = \<const0> ;
  assign m_axi_wid[14] = \<const0> ;
  assign m_axi_wid[13] = \<const0> ;
  assign m_axi_wid[12] = \<const0> ;
  assign m_axi_wid[11] = \<const0> ;
  assign m_axi_wid[10] = \<const0> ;
  assign m_axi_wid[9] = \<const0> ;
  assign m_axi_wid[8] = \<const0> ;
  assign m_axi_wid[7] = \<const0> ;
  assign m_axi_wid[6] = \<const0> ;
  assign m_axi_wid[5] = \<const0> ;
  assign m_axi_wid[4] = \<const0> ;
  assign m_axi_wid[3] = \<const0> ;
  assign m_axi_wid[2] = \<const0> ;
  assign m_axi_wid[1] = \<const0> ;
  assign m_axi_wid[0] = \<const0> ;
  assign m_axi_wlast[2] = s_axi_wlast;
  assign m_axi_wlast[1] = s_axi_wlast;
  assign m_axi_wlast[0] = s_axi_wlast;
  assign m_axi_wstrb[11:8] = s_axi_wstrb;
  assign m_axi_wstrb[7:4] = s_axi_wstrb;
  assign m_axi_wstrb[3:0] = s_axi_wstrb;
  assign m_axi_wuser[2] = \<const0> ;
  assign m_axi_wuser[1] = \<const0> ;
  assign m_axi_wuser[0] = \<const0> ;
  assign s_axi_bid[11:0] = s_axi_rid;
  assign s_axi_buser[0] = \<const0> ;
  assign s_axi_ruser[0] = \<const0> ;
  GND GND
       (.G(\<const0> ));
  blok_xbar_0_axi_crossbar_v2_1_23_crossbar_sasd \gen_sasd.crossbar_sasd_0 
       (.Q({\^m_axi_arqos ,\^m_axi_arcache ,\^m_axi_arburst ,\^m_axi_arprot ,\^m_axi_arlock ,\^m_axi_arsize ,\^m_axi_awlen ,\^m_axi_awaddr ,\^m_axi_araddr ,s_axi_rid}),
        .aclk(aclk),
        .aresetn(aresetn),
        .m_axi_arready(m_axi_arready),
        .m_axi_arvalid(m_axi_arvalid),
        .m_axi_awready(m_axi_awready),
        .m_axi_awvalid(m_axi_awvalid),
        .m_axi_bready(m_axi_bready),
        .m_axi_bresp(m_axi_bresp),
        .m_axi_bvalid(m_axi_bvalid),
        .m_axi_rdata(m_axi_rdata),
        .m_axi_rlast(m_axi_rlast),
        .m_axi_rready(m_axi_rready),
        .m_axi_rresp(m_axi_rresp),
        .m_axi_rvalid(m_axi_rvalid),
        .m_axi_wready(m_axi_wready),
        .m_axi_wvalid(m_axi_wvalid),
        .\m_payload_i_reg[34] ({s_axi_rdata,s_axi_rresp,s_axi_rlast}),
        .s_axi_araddr(s_axi_araddr),
        .s_axi_arburst(s_axi_arburst),
        .s_axi_arcache(s_axi_arcache),
        .s_axi_arid(s_axi_arid),
        .s_axi_arlen(s_axi_arlen),
        .s_axi_arlock(s_axi_arlock),
        .s_axi_arprot(s_axi_arprot),
        .s_axi_arqos(s_axi_arqos),
        .s_axi_arready(s_axi_arready),
        .s_axi_arsize(s_axi_arsize),
        .s_axi_arvalid(s_axi_arvalid),
        .s_axi_awaddr(s_axi_awaddr),
        .s_axi_awburst(s_axi_awburst),
        .s_axi_awcache(s_axi_awcache),
        .s_axi_awid(s_axi_awid),
        .s_axi_awlen(s_axi_awlen),
        .s_axi_awlock(s_axi_awlock),
        .s_axi_awprot(s_axi_awprot),
        .s_axi_awqos(s_axi_awqos),
        .s_axi_awready(s_axi_awready),
        .s_axi_awsize(s_axi_awsize),
        .s_axi_awvalid(s_axi_awvalid),
        .s_axi_bready(s_axi_bready),
        .s_axi_bresp(s_axi_bresp),
        .s_axi_bvalid(s_axi_bvalid),
        .s_axi_rready(s_axi_rready),
        .s_axi_rvalid(s_axi_rvalid),
        .s_axi_wlast(s_axi_wlast),
        .s_axi_wready(s_axi_wready),
        .s_axi_wvalid(s_axi_wvalid));
endmodule

(* ORIG_REF_NAME = "axi_crossbar_v2_1_23_crossbar_sasd" *) 
module blok_xbar_0_axi_crossbar_v2_1_23_crossbar_sasd
   (Q,
    \m_payload_i_reg[34] ,
    m_axi_arvalid,
    m_axi_awvalid,
    s_axi_wready,
    m_axi_wvalid,
    s_axi_bvalid,
    m_axi_bready,
    s_axi_bresp,
    s_axi_awready,
    s_axi_arready,
    s_axi_rvalid,
    m_axi_rready,
    aclk,
    aresetn,
    s_axi_awvalid,
    s_axi_arvalid,
    s_axi_rready,
    s_axi_wlast,
    s_axi_wvalid,
    s_axi_bready,
    m_axi_rlast,
    m_axi_rresp,
    m_axi_rdata,
    m_axi_rvalid,
    m_axi_arready,
    m_axi_awready,
    m_axi_wready,
    m_axi_bvalid,
    m_axi_bresp,
    s_axi_arqos,
    s_axi_awqos,
    s_axi_arcache,
    s_axi_awcache,
    s_axi_arburst,
    s_axi_awburst,
    s_axi_arprot,
    s_axi_awprot,
    s_axi_arlock,
    s_axi_awlock,
    s_axi_arsize,
    s_axi_awsize,
    s_axi_arlen,
    s_axi_awlen,
    s_axi_araddr,
    s_axi_awaddr,
    s_axi_arid,
    s_axi_awid);
  output [68:0]Q;
  output [34:0]\m_payload_i_reg[34] ;
  output [2:0]m_axi_arvalid;
  output [2:0]m_axi_awvalid;
  output [0:0]s_axi_wready;
  output [2:0]m_axi_wvalid;
  output [0:0]s_axi_bvalid;
  output [2:0]m_axi_bready;
  output [1:0]s_axi_bresp;
  output [0:0]s_axi_awready;
  output [0:0]s_axi_arready;
  output [0:0]s_axi_rvalid;
  output [2:0]m_axi_rready;
  input aclk;
  input aresetn;
  input [0:0]s_axi_awvalid;
  input [0:0]s_axi_arvalid;
  input [0:0]s_axi_rready;
  input [0:0]s_axi_wlast;
  input [0:0]s_axi_wvalid;
  input [0:0]s_axi_bready;
  input [2:0]m_axi_rlast;
  input [5:0]m_axi_rresp;
  input [95:0]m_axi_rdata;
  input [2:0]m_axi_rvalid;
  input [2:0]m_axi_arready;
  input [2:0]m_axi_awready;
  input [2:0]m_axi_wready;
  input [2:0]m_axi_bvalid;
  input [5:0]m_axi_bresp;
  input [3:0]s_axi_arqos;
  input [3:0]s_axi_awqos;
  input [3:0]s_axi_arcache;
  input [3:0]s_axi_awcache;
  input [1:0]s_axi_arburst;
  input [1:0]s_axi_awburst;
  input [2:0]s_axi_arprot;
  input [2:0]s_axi_awprot;
  input [0:0]s_axi_arlock;
  input [0:0]s_axi_awlock;
  input [2:0]s_axi_arsize;
  input [2:0]s_axi_awsize;
  input [7:0]s_axi_arlen;
  input [7:0]s_axi_awlen;
  input [31:0]s_axi_araddr;
  input [31:0]s_axi_awaddr;
  input [11:0]s_axi_arid;
  input [11:0]s_axi_awid;

  wire [68:0]Q;
  wire aa_grant_rnw;
  wire aa_rready;
  wire aclk;
  wire addr_arbiter_inst_n_103;
  wire addr_arbiter_inst_n_104;
  wire addr_arbiter_inst_n_107;
  wire addr_arbiter_inst_n_4;
  wire addr_arbiter_inst_n_5;
  wire addr_arbiter_inst_n_6;
  wire addr_arbiter_inst_n_78;
  wire addr_arbiter_inst_n_8;
  wire addr_arbiter_inst_n_80;
  wire addr_arbiter_inst_n_85;
  wire addr_arbiter_inst_n_87;
  wire addr_arbiter_inst_n_91;
  wire addr_arbiter_inst_n_96;
  wire addr_arbiter_inst_n_97;
  wire addr_arbiter_inst_n_98;
  wire aresetn;
  wire aresetn_d;
  wire \gen_axi.s_axi_rid_i ;
  wire \gen_decerr.decerr_slave_inst_n_2 ;
  wire \gen_decerr.decerr_slave_inst_n_3 ;
  wire \gen_decerr.decerr_slave_inst_n_4 ;
  wire \gen_decerr.decerr_slave_inst_n_5 ;
  wire \gen_decerr.decerr_slave_inst_n_6 ;
  wire \gen_decerr.decerr_slave_inst_n_7 ;
  wire \gen_decerr.decerr_slave_inst_n_8 ;
  wire \gen_decerr.decerr_slave_inst_n_9 ;
  wire [1:0]m_atarget_enc;
  wire \m_atarget_enc[0]_i_1_n_0 ;
  wire \m_atarget_enc[1]_i_1_n_0 ;
  wire [3:0]m_atarget_hot;
  wire [0:0]m_atarget_hot0;
  wire [2:0]m_axi_arready;
  wire [2:0]m_axi_arvalid;
  wire [2:0]m_axi_awready;
  wire [2:0]m_axi_awvalid;
  wire [2:0]m_axi_bready;
  wire [5:0]m_axi_bresp;
  wire [2:0]m_axi_bvalid;
  wire [95:0]m_axi_rdata;
  wire [2:0]m_axi_rlast;
  wire [2:0]m_axi_rready;
  wire [5:0]m_axi_rresp;
  wire [2:0]m_axi_rvalid;
  wire [2:0]m_axi_wready;
  wire [2:0]m_axi_wvalid;
  wire [34:0]\m_payload_i_reg[34] ;
  wire [1:0]m_ready_d;
  wire [2:2]m_ready_d0;
  wire [0:0]m_ready_d0_0;
  wire [2:0]m_ready_d_1;
  wire m_valid_i;
  wire [3:3]mi_arready;
  wire [3:3]mi_rvalid;
  wire p_0_in1_in;
  wire p_1_in;
  wire reg_slice_r_n_42;
  wire reg_slice_r_n_43;
  wire reset;
  wire [31:0]s_axi_araddr;
  wire [1:0]s_axi_arburst;
  wire [3:0]s_axi_arcache;
  wire [11:0]s_axi_arid;
  wire [7:0]s_axi_arlen;
  wire [0:0]s_axi_arlock;
  wire [2:0]s_axi_arprot;
  wire [3:0]s_axi_arqos;
  wire [0:0]s_axi_arready;
  wire [2:0]s_axi_arsize;
  wire [0:0]s_axi_arvalid;
  wire [31:0]s_axi_awaddr;
  wire [1:0]s_axi_awburst;
  wire [3:0]s_axi_awcache;
  wire [11:0]s_axi_awid;
  wire [7:0]s_axi_awlen;
  wire [0:0]s_axi_awlock;
  wire [2:0]s_axi_awprot;
  wire [3:0]s_axi_awqos;
  wire [0:0]s_axi_awready;
  wire [2:0]s_axi_awsize;
  wire [0:0]s_axi_awvalid;
  wire [0:0]s_axi_bready;
  wire [1:0]s_axi_bresp;
  wire [0:0]s_axi_bvalid;
  wire [0:0]s_axi_rready;
  wire [0:0]s_axi_rvalid;
  wire [0:0]s_axi_wlast;
  wire [0:0]s_axi_wready;
  wire [0:0]s_axi_wvalid;
  wire sr_rvalid;

  blok_xbar_0_axi_crossbar_v2_1_23_addr_arbiter_sasd addr_arbiter_inst
       (.D({addr_arbiter_inst_n_4,addr_arbiter_inst_n_5,addr_arbiter_inst_n_6,m_atarget_hot0}),
        .E(p_1_in),
        .Q(Q),
        .SR(reset),
        .aa_grant_rnw(aa_grant_rnw),
        .aa_rready(aa_rready),
        .aclk(aclk),
        .aresetn_d(aresetn_d),
        .\aresetn_d_reg[0] (addr_arbiter_inst_n_87),
        .\aresetn_d_reg[1] (addr_arbiter_inst_n_85),
        .\gen_axi.s_axi_awready_i_reg (m_atarget_hot),
        .\gen_axi.s_axi_awready_i_reg_0 (\gen_decerr.decerr_slave_inst_n_9 ),
        .\gen_axi.s_axi_rid_i (\gen_axi.s_axi_rid_i ),
        .\gen_no_arbiter.grant_rnw_reg_0 (addr_arbiter_inst_n_98),
        .\gen_no_arbiter.m_amesg_i_reg[27]_0 (addr_arbiter_inst_n_80),
        .\gen_no_arbiter.m_amesg_i_reg[34]_0 (addr_arbiter_inst_n_8),
        .\gen_no_arbiter.m_amesg_i_reg[47]_0 (addr_arbiter_inst_n_107),
        .\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 (\gen_decerr.decerr_slave_inst_n_2 ),
        .\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1 (\gen_decerr.decerr_slave_inst_n_8 ),
        .\gen_no_arbiter.m_valid_i_reg_0 (\gen_decerr.decerr_slave_inst_n_7 ),
        .m_axi_arvalid(m_axi_arvalid),
        .m_axi_awvalid(m_axi_awvalid),
        .m_axi_bready(m_axi_bready),
        .m_axi_wvalid(m_axi_wvalid),
        .m_ready_d(m_ready_d),
        .m_ready_d0(m_ready_d0),
        .m_ready_d0_0(m_ready_d0_0),
        .m_ready_d_1(m_ready_d_1),
        .\m_ready_d_reg[0] (addr_arbiter_inst_n_103),
        .\m_ready_d_reg[1] (addr_arbiter_inst_n_78),
        .\m_ready_d_reg[2] (addr_arbiter_inst_n_91),
        .m_valid_i(m_valid_i),
        .m_valid_i_reg({reg_slice_r_n_42,reg_slice_r_n_43}),
        .mi_arready(mi_arready),
        .mi_rvalid(mi_rvalid),
        .p_0_in1_in(p_0_in1_in),
        .s_axi_araddr(s_axi_araddr),
        .s_axi_arburst(s_axi_arburst),
        .s_axi_arcache(s_axi_arcache),
        .s_axi_arid(s_axi_arid),
        .s_axi_arlen(s_axi_arlen),
        .s_axi_arlock(s_axi_arlock),
        .s_axi_arprot(s_axi_arprot),
        .s_axi_arqos(s_axi_arqos),
        .s_axi_arready(s_axi_arready),
        .s_axi_arsize(s_axi_arsize),
        .s_axi_arvalid(s_axi_arvalid),
        .s_axi_awaddr(s_axi_awaddr),
        .s_axi_awburst(s_axi_awburst),
        .s_axi_awcache(s_axi_awcache),
        .s_axi_awid(s_axi_awid),
        .s_axi_awlen(s_axi_awlen),
        .s_axi_awlock(s_axi_awlock),
        .s_axi_awprot(s_axi_awprot),
        .s_axi_awqos(s_axi_awqos),
        .s_axi_awready(s_axi_awready),
        .s_axi_awsize(s_axi_awsize),
        .s_axi_awvalid(s_axi_awvalid),
        .s_axi_bready(s_axi_bready),
        .s_axi_bready_0_sp_1(addr_arbiter_inst_n_104),
        .s_axi_bvalid(s_axi_bvalid),
        .s_axi_bvalid_0_sp_1(\gen_decerr.decerr_slave_inst_n_4 ),
        .s_axi_rready(s_axi_rready),
        .s_axi_wlast(s_axi_wlast),
        .\s_axi_wlast[0]_0 (addr_arbiter_inst_n_97),
        .s_axi_wlast_0_sp_1(addr_arbiter_inst_n_96),
        .s_axi_wready(s_axi_wready),
        .s_axi_wready_0_sp_1(\gen_decerr.decerr_slave_inst_n_3 ),
        .s_axi_wvalid(s_axi_wvalid),
        .s_ready_i_reg(\gen_decerr.decerr_slave_inst_n_6 ),
        .sr_rvalid(sr_rvalid));
  FDRE #(
    .INIT(1'b0)) 
    aresetn_d_reg
       (.C(aclk),
        .CE(1'b1),
        .D(aresetn),
        .Q(aresetn_d),
        .R(1'b0));
  blok_xbar_0_axi_crossbar_v2_1_23_decerr_slave \gen_decerr.decerr_slave_inst 
       (.\FSM_onehot_gen_axi.write_cs_reg[2]_0 (\gen_decerr.decerr_slave_inst_n_9 ),
        .Q(m_atarget_hot[3]),
        .SR(reset),
        .aa_grant_rnw(aa_grant_rnw),
        .aa_rready(aa_rready),
        .aclk(aclk),
        .aresetn_d(aresetn_d),
        .\gen_axi.read_cnt_reg[7]_0 (Q[51:44]),
        .\gen_axi.s_axi_arready_i_reg_0 (addr_arbiter_inst_n_78),
        .\gen_axi.s_axi_awready_i_reg_0 (\gen_decerr.decerr_slave_inst_n_8 ),
        .\gen_axi.s_axi_awready_i_reg_1 (addr_arbiter_inst_n_103),
        .\gen_axi.s_axi_awready_i_reg_2 (addr_arbiter_inst_n_91),
        .\gen_axi.s_axi_bvalid_i_reg_0 (\gen_decerr.decerr_slave_inst_n_4 ),
        .\gen_axi.s_axi_rid_i (\gen_axi.s_axi_rid_i ),
        .\gen_axi.s_axi_rlast_i_reg_0 (\gen_decerr.decerr_slave_inst_n_5 ),
        .\gen_axi.s_axi_rlast_i_reg_1 (addr_arbiter_inst_n_107),
        .\gen_axi.s_axi_wready_i_reg_0 (\gen_decerr.decerr_slave_inst_n_3 ),
        .\gen_axi.s_axi_wready_i_reg_1 (addr_arbiter_inst_n_98),
        .\gen_no_arbiter.m_grant_hot_i_reg[0]_inv (addr_arbiter_inst_n_97),
        .\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 (addr_arbiter_inst_n_104),
        .m_axi_arready(m_axi_arready),
        .m_axi_arready_0_sp_1(\gen_decerr.decerr_slave_inst_n_7 ),
        .m_axi_awready(m_axi_awready),
        .m_axi_bvalid(m_axi_bvalid),
        .m_axi_rlast(m_axi_rlast),
        .m_axi_rvalid(m_axi_rvalid),
        .m_axi_rvalid_0_sp_1(\gen_decerr.decerr_slave_inst_n_6 ),
        .m_axi_wready(m_axi_wready),
        .m_ready_d(m_ready_d_1),
        .\m_ready_d_reg[1] (\gen_decerr.decerr_slave_inst_n_2 ),
        .m_valid_i(m_valid_i),
        .mi_arready(mi_arready),
        .mi_rvalid(mi_rvalid),
        .s_axi_wlast(s_axi_wlast),
        .\skid_buffer_reg[0] (m_atarget_enc));
  LUT6 #(
    .INIT(64'hFFFFFFFFFEFEFEEE)) 
    \m_atarget_enc[0]_i_1 
       (.I0(addr_arbiter_inst_n_8),
        .I1(addr_arbiter_inst_n_80),
        .I2(Q[38]),
        .I3(Q[26]),
        .I4(Q[25]),
        .I5(Q[37]),
        .O(\m_atarget_enc[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \m_atarget_enc[1]_i_1 
       (.I0(addr_arbiter_inst_n_8),
        .I1(addr_arbiter_inst_n_80),
        .I2(Q[38]),
        .O(\m_atarget_enc[1]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \m_atarget_enc_reg[0] 
       (.C(aclk),
        .CE(1'b1),
        .D(\m_atarget_enc[0]_i_1_n_0 ),
        .Q(m_atarget_enc[0]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \m_atarget_enc_reg[1] 
       (.C(aclk),
        .CE(1'b1),
        .D(\m_atarget_enc[1]_i_1_n_0 ),
        .Q(m_atarget_enc[1]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \m_atarget_hot_reg[0] 
       (.C(aclk),
        .CE(1'b1),
        .D(m_atarget_hot0),
        .Q(m_atarget_hot[0]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \m_atarget_hot_reg[1] 
       (.C(aclk),
        .CE(1'b1),
        .D(addr_arbiter_inst_n_6),
        .Q(m_atarget_hot[1]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \m_atarget_hot_reg[2] 
       (.C(aclk),
        .CE(1'b1),
        .D(addr_arbiter_inst_n_5),
        .Q(m_atarget_hot[2]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \m_atarget_hot_reg[3] 
       (.C(aclk),
        .CE(1'b1),
        .D(addr_arbiter_inst_n_4),
        .Q(m_atarget_hot[3]),
        .R(reset));
  blok_xbar_0_axi_register_slice_v2_1_22_axic_register_slice reg_slice_r
       (.E(p_1_in),
        .Q(m_atarget_enc),
        .SR(reset),
        .aa_grant_rnw(aa_grant_rnw),
        .aa_rready(aa_rready),
        .aclk(aclk),
        .\aresetn_d_reg[1]_0 ({reg_slice_r_n_42,reg_slice_r_n_43}),
        .m_axi_rdata(m_axi_rdata),
        .m_axi_rready(m_axi_rready),
        .\m_axi_rready[2] (m_atarget_hot[2:0]),
        .m_axi_rresp(m_axi_rresp),
        .\m_payload_i_reg[34]_0 (\m_payload_i_reg[34] ),
        .m_ready_d(m_ready_d[0]),
        .m_ready_d0(m_ready_d0_0),
        .m_valid_i(m_valid_i),
        .m_valid_i_reg_0(addr_arbiter_inst_n_85),
        .p_0_in1_in(p_0_in1_in),
        .s_axi_rready(s_axi_rready),
        .s_axi_rvalid(s_axi_rvalid),
        .s_ready_i_reg_0(addr_arbiter_inst_n_87),
        .\skid_buffer_reg[0]_0 (\gen_decerr.decerr_slave_inst_n_5 ),
        .sr_rvalid(sr_rvalid));
  LUT5 #(
    .INIT(32'hFCEEFC22)) 
    \s_axi_bresp[0]_INST_0 
       (.I0(m_axi_bresp[0]),
        .I1(m_atarget_enc[1]),
        .I2(m_axi_bresp[2]),
        .I3(m_atarget_enc[0]),
        .I4(m_axi_bresp[4]),
        .O(s_axi_bresp[0]));
  LUT5 #(
    .INIT(32'hFCEEFC22)) 
    \s_axi_bresp[1]_INST_0 
       (.I0(m_axi_bresp[1]),
        .I1(m_atarget_enc[1]),
        .I2(m_axi_bresp[3]),
        .I3(m_atarget_enc[0]),
        .I4(m_axi_bresp[5]),
        .O(s_axi_bresp[1]));
  blok_xbar_0_axi_crossbar_v2_1_23_splitter__parameterized0 splitter_ar
       (.aa_grant_rnw(aa_grant_rnw),
        .aclk(aclk),
        .aresetn_d(aresetn_d),
        .m_ready_d(m_ready_d),
        .m_ready_d0(m_ready_d0_0),
        .\m_ready_d_reg[1]_0 (\gen_decerr.decerr_slave_inst_n_7 ),
        .m_valid_i(m_valid_i));
  blok_xbar_0_axi_crossbar_v2_1_23_splitter splitter_aw
       (.aclk(aclk),
        .aresetn_d(aresetn_d),
        .m_ready_d(m_ready_d_1),
        .m_ready_d0(m_ready_d0),
        .\m_ready_d_reg[2]_0 (\gen_decerr.decerr_slave_inst_n_4 ),
        .\m_ready_d_reg[2]_1 (addr_arbiter_inst_n_104),
        .\m_ready_d_reg[2]_2 (addr_arbiter_inst_n_96));
endmodule

(* ORIG_REF_NAME = "axi_crossbar_v2_1_23_decerr_slave" *) 
module blok_xbar_0_axi_crossbar_v2_1_23_decerr_slave
   (mi_rvalid,
    mi_arready,
    \m_ready_d_reg[1] ,
    \gen_axi.s_axi_wready_i_reg_0 ,
    \gen_axi.s_axi_bvalid_i_reg_0 ,
    \gen_axi.s_axi_rlast_i_reg_0 ,
    m_axi_rvalid_0_sp_1,
    m_axi_arready_0_sp_1,
    \gen_axi.s_axi_awready_i_reg_0 ,
    \FSM_onehot_gen_axi.write_cs_reg[2]_0 ,
    SR,
    aclk,
    aa_rready,
    Q,
    aresetn_d,
    \gen_axi.s_axi_arready_i_reg_0 ,
    \gen_axi.s_axi_rid_i ,
    \gen_axi.read_cnt_reg[7]_0 ,
    \gen_axi.s_axi_awready_i_reg_1 ,
    \gen_axi.s_axi_wready_i_reg_1 ,
    s_axi_wlast,
    m_ready_d,
    m_valid_i,
    aa_grant_rnw,
    \gen_no_arbiter.m_grant_hot_i_reg[0]_inv ,
    \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ,
    m_axi_rlast,
    \skid_buffer_reg[0] ,
    m_axi_rvalid,
    m_axi_arready,
    m_axi_awready,
    m_axi_wready,
    m_axi_bvalid,
    \gen_axi.s_axi_awready_i_reg_2 ,
    \gen_axi.s_axi_rlast_i_reg_1 );
  output [0:0]mi_rvalid;
  output [0:0]mi_arready;
  output \m_ready_d_reg[1] ;
  output \gen_axi.s_axi_wready_i_reg_0 ;
  output \gen_axi.s_axi_bvalid_i_reg_0 ;
  output \gen_axi.s_axi_rlast_i_reg_0 ;
  output m_axi_rvalid_0_sp_1;
  output m_axi_arready_0_sp_1;
  output \gen_axi.s_axi_awready_i_reg_0 ;
  output \FSM_onehot_gen_axi.write_cs_reg[2]_0 ;
  input [0:0]SR;
  input aclk;
  input aa_rready;
  input [0:0]Q;
  input aresetn_d;
  input \gen_axi.s_axi_arready_i_reg_0 ;
  input \gen_axi.s_axi_rid_i ;
  input [7:0]\gen_axi.read_cnt_reg[7]_0 ;
  input \gen_axi.s_axi_awready_i_reg_1 ;
  input \gen_axi.s_axi_wready_i_reg_1 ;
  input [0:0]s_axi_wlast;
  input [2:0]m_ready_d;
  input m_valid_i;
  input aa_grant_rnw;
  input \gen_no_arbiter.m_grant_hot_i_reg[0]_inv ;
  input \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ;
  input [2:0]m_axi_rlast;
  input [1:0]\skid_buffer_reg[0] ;
  input [2:0]m_axi_rvalid;
  input [2:0]m_axi_arready;
  input [2:0]m_axi_awready;
  input [2:0]m_axi_wready;
  input [2:0]m_axi_bvalid;
  input \gen_axi.s_axi_awready_i_reg_2 ;
  input \gen_axi.s_axi_rlast_i_reg_1 ;

  wire \FSM_onehot_gen_axi.write_cs[0]_i_1_n_0 ;
  wire \FSM_onehot_gen_axi.write_cs[1]_i_1_n_0 ;
  wire \FSM_onehot_gen_axi.write_cs[2]_i_1_n_0 ;
  wire \FSM_onehot_gen_axi.write_cs[2]_i_2_n_0 ;
  wire \FSM_onehot_gen_axi.write_cs_reg[2]_0 ;
  wire \FSM_onehot_gen_axi.write_cs_reg_n_0_[0] ;
  wire \FSM_onehot_gen_axi.write_cs_reg_n_0_[1] ;
  wire [0:0]Q;
  wire [0:0]SR;
  wire aa_grant_rnw;
  wire aa_rready;
  wire aclk;
  wire aresetn_d;
  wire \gen_axi.read_cnt[5]_i_2_n_0 ;
  wire \gen_axi.read_cnt[7]_i_1_n_0 ;
  wire \gen_axi.read_cnt[7]_i_3_n_0 ;
  wire \gen_axi.read_cnt[7]_i_5_n_0 ;
  wire [0:0]\gen_axi.read_cnt_reg ;
  wire [7:0]\gen_axi.read_cnt_reg[7]_0 ;
  wire [7:1]\gen_axi.read_cnt_reg__0 ;
  wire \gen_axi.read_cs[0]_i_1_n_0 ;
  wire \gen_axi.s_axi_arready_i_i_1_n_0 ;
  wire \gen_axi.s_axi_arready_i_i_2_n_0 ;
  wire \gen_axi.s_axi_arready_i_reg_0 ;
  wire \gen_axi.s_axi_awready_i_i_1_n_0 ;
  wire \gen_axi.s_axi_awready_i_reg_0 ;
  wire \gen_axi.s_axi_awready_i_reg_1 ;
  wire \gen_axi.s_axi_awready_i_reg_2 ;
  wire \gen_axi.s_axi_bvalid_i_i_1_n_0 ;
  wire \gen_axi.s_axi_bvalid_i_reg_0 ;
  wire \gen_axi.s_axi_rid_i ;
  wire \gen_axi.s_axi_rlast_i_i_1_n_0 ;
  wire \gen_axi.s_axi_rlast_i_i_3_n_0 ;
  wire \gen_axi.s_axi_rlast_i_i_6_n_0 ;
  wire \gen_axi.s_axi_rlast_i_reg_0 ;
  wire \gen_axi.s_axi_rlast_i_reg_1 ;
  wire \gen_axi.s_axi_wready_i_i_1_n_0 ;
  wire \gen_axi.s_axi_wready_i_i_3_n_0 ;
  wire \gen_axi.s_axi_wready_i_reg_0 ;
  wire \gen_axi.s_axi_wready_i_reg_1 ;
  wire \gen_no_arbiter.m_grant_hot_i_reg[0]_inv ;
  wire \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ;
  wire [2:0]m_axi_arready;
  wire m_axi_arready_0_sn_1;
  wire [2:0]m_axi_awready;
  wire [2:0]m_axi_bvalid;
  wire [2:0]m_axi_rlast;
  wire [2:0]m_axi_rvalid;
  wire m_axi_rvalid_0_sn_1;
  wire [2:0]m_axi_wready;
  wire [2:0]m_ready_d;
  wire \m_ready_d_reg[1] ;
  wire m_valid_i;
  wire [0:0]mi_arready;
  wire [3:3]mi_awready;
  wire [3:3]mi_bvalid;
  wire [108:108]mi_rmesg;
  wire [0:0]mi_rvalid;
  wire [3:3]mi_wready;
  wire [7:0]p_0_in;
  wire [0:0]s_axi_wlast;
  wire [1:0]\skid_buffer_reg[0] ;

  assign m_axi_arready_0_sp_1 = m_axi_arready_0_sn_1;
  assign m_axi_rvalid_0_sp_1 = m_axi_rvalid_0_sn_1;
  LUT3 #(
    .INIT(8'hB8)) 
    \FSM_onehot_gen_axi.write_cs[0]_i_1 
       (.I0(\FSM_onehot_gen_axi.write_cs_reg[2]_0 ),
        .I1(\FSM_onehot_gen_axi.write_cs[2]_i_2_n_0 ),
        .I2(\FSM_onehot_gen_axi.write_cs_reg_n_0_[0] ),
        .O(\FSM_onehot_gen_axi.write_cs[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \FSM_onehot_gen_axi.write_cs[1]_i_1 
       (.I0(\FSM_onehot_gen_axi.write_cs_reg_n_0_[0] ),
        .I1(\FSM_onehot_gen_axi.write_cs[2]_i_2_n_0 ),
        .I2(\FSM_onehot_gen_axi.write_cs_reg_n_0_[1] ),
        .O(\FSM_onehot_gen_axi.write_cs[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \FSM_onehot_gen_axi.write_cs[2]_i_1 
       (.I0(\FSM_onehot_gen_axi.write_cs_reg_n_0_[1] ),
        .I1(\FSM_onehot_gen_axi.write_cs[2]_i_2_n_0 ),
        .I2(\FSM_onehot_gen_axi.write_cs_reg[2]_0 ),
        .O(\FSM_onehot_gen_axi.write_cs[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEFEEEEEEEEEEEEEE)) 
    \FSM_onehot_gen_axi.write_cs[2]_i_2 
       (.I0(\gen_axi.s_axi_wready_i_i_3_n_0 ),
        .I1(\gen_axi.s_axi_awready_i_reg_1 ),
        .I2(\gen_axi.s_axi_wready_i_reg_1 ),
        .I3(s_axi_wlast),
        .I4(\FSM_onehot_gen_axi.write_cs_reg_n_0_[1] ),
        .I5(Q),
        .O(\FSM_onehot_gen_axi.write_cs[2]_i_2_n_0 ));
  (* FSM_ENCODED_STATES = "P_WRITE_IDLE:001,P_WRITE_DATA:010,P_WRITE_RESP:100," *) 
  FDSE #(
    .INIT(1'b1)) 
    \FSM_onehot_gen_axi.write_cs_reg[0] 
       (.C(aclk),
        .CE(1'b1),
        .D(\FSM_onehot_gen_axi.write_cs[0]_i_1_n_0 ),
        .Q(\FSM_onehot_gen_axi.write_cs_reg_n_0_[0] ),
        .S(SR));
  (* FSM_ENCODED_STATES = "P_WRITE_IDLE:001,P_WRITE_DATA:010,P_WRITE_RESP:100," *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_gen_axi.write_cs_reg[1] 
       (.C(aclk),
        .CE(1'b1),
        .D(\FSM_onehot_gen_axi.write_cs[1]_i_1_n_0 ),
        .Q(\FSM_onehot_gen_axi.write_cs_reg_n_0_[1] ),
        .R(SR));
  (* FSM_ENCODED_STATES = "P_WRITE_IDLE:001,P_WRITE_DATA:010,P_WRITE_RESP:100," *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_gen_axi.write_cs_reg[2] 
       (.C(aclk),
        .CE(1'b1),
        .D(\FSM_onehot_gen_axi.write_cs[2]_i_1_n_0 ),
        .Q(\FSM_onehot_gen_axi.write_cs_reg[2]_0 ),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'h74)) 
    \gen_axi.read_cnt[0]_i_1 
       (.I0(\gen_axi.read_cnt_reg ),
        .I1(mi_rvalid),
        .I2(\gen_axi.read_cnt_reg[7]_0 [0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT4 #(
    .INIT(16'h9F90)) 
    \gen_axi.read_cnt[1]_i_1 
       (.I0(\gen_axi.read_cnt_reg__0 [1]),
        .I1(\gen_axi.read_cnt_reg ),
        .I2(mi_rvalid),
        .I3(\gen_axi.read_cnt_reg[7]_0 [1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT5 #(
    .INIT(32'hE1FFE100)) 
    \gen_axi.read_cnt[2]_i_1 
       (.I0(\gen_axi.read_cnt_reg__0 [1]),
        .I1(\gen_axi.read_cnt_reg ),
        .I2(\gen_axi.read_cnt_reg__0 [2]),
        .I3(mi_rvalid),
        .I4(\gen_axi.read_cnt_reg[7]_0 [2]),
        .O(p_0_in[2]));
  LUT6 #(
    .INIT(64'hFE01FFFFFE010000)) 
    \gen_axi.read_cnt[3]_i_1 
       (.I0(\gen_axi.read_cnt_reg__0 [2]),
        .I1(\gen_axi.read_cnt_reg ),
        .I2(\gen_axi.read_cnt_reg__0 [1]),
        .I3(\gen_axi.read_cnt_reg__0 [3]),
        .I4(mi_rvalid),
        .I5(\gen_axi.read_cnt_reg[7]_0 [3]),
        .O(p_0_in[3]));
  LUT5 #(
    .INIT(32'hE1FFE100)) 
    \gen_axi.read_cnt[4]_i_1 
       (.I0(\gen_axi.read_cnt_reg__0 [3]),
        .I1(\gen_axi.read_cnt[5]_i_2_n_0 ),
        .I2(\gen_axi.read_cnt_reg__0 [4]),
        .I3(mi_rvalid),
        .I4(\gen_axi.read_cnt_reg[7]_0 [4]),
        .O(p_0_in[4]));
  LUT6 #(
    .INIT(64'hFE01FFFFFE010000)) 
    \gen_axi.read_cnt[5]_i_1 
       (.I0(\gen_axi.read_cnt[5]_i_2_n_0 ),
        .I1(\gen_axi.read_cnt_reg__0 [3]),
        .I2(\gen_axi.read_cnt_reg__0 [4]),
        .I3(\gen_axi.read_cnt_reg__0 [5]),
        .I4(mi_rvalid),
        .I5(\gen_axi.read_cnt_reg[7]_0 [5]),
        .O(p_0_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \gen_axi.read_cnt[5]_i_2 
       (.I0(\gen_axi.read_cnt_reg__0 [2]),
        .I1(\gen_axi.read_cnt_reg ),
        .I2(\gen_axi.read_cnt_reg__0 [1]),
        .O(\gen_axi.read_cnt[5]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h9F90)) 
    \gen_axi.read_cnt[6]_i_1 
       (.I0(\gen_axi.read_cnt[7]_i_5_n_0 ),
        .I1(\gen_axi.read_cnt_reg__0 [6]),
        .I2(mi_rvalid),
        .I3(\gen_axi.read_cnt_reg[7]_0 [6]),
        .O(p_0_in[6]));
  LUT6 #(
    .INIT(64'h8F80808000000000)) 
    \gen_axi.read_cnt[7]_i_1 
       (.I0(\gen_axi.read_cnt[7]_i_3_n_0 ),
        .I1(aa_rready),
        .I2(mi_rvalid),
        .I3(mi_arready),
        .I4(\gen_axi.s_axi_arready_i_reg_0 ),
        .I5(Q),
        .O(\gen_axi.read_cnt[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT5 #(
    .INIT(32'hA9FFA900)) 
    \gen_axi.read_cnt[7]_i_2 
       (.I0(\gen_axi.read_cnt_reg__0 [7]),
        .I1(\gen_axi.read_cnt[7]_i_5_n_0 ),
        .I2(\gen_axi.read_cnt_reg__0 [6]),
        .I3(mi_rvalid),
        .I4(\gen_axi.read_cnt_reg[7]_0 [7]),
        .O(p_0_in[7]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \gen_axi.read_cnt[7]_i_3 
       (.I0(\gen_axi.read_cnt[7]_i_5_n_0 ),
        .I1(\gen_axi.read_cnt_reg__0 [6]),
        .I2(\gen_axi.read_cnt_reg__0 [7]),
        .O(\gen_axi.read_cnt[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \gen_axi.read_cnt[7]_i_5 
       (.I0(\gen_axi.read_cnt_reg__0 [5]),
        .I1(\gen_axi.read_cnt_reg__0 [4]),
        .I2(\gen_axi.read_cnt_reg__0 [3]),
        .I3(\gen_axi.read_cnt_reg__0 [2]),
        .I4(\gen_axi.read_cnt_reg ),
        .I5(\gen_axi.read_cnt_reg__0 [1]),
        .O(\gen_axi.read_cnt[7]_i_5_n_0 ));
  FDRE \gen_axi.read_cnt_reg[0] 
       (.C(aclk),
        .CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
        .D(p_0_in[0]),
        .Q(\gen_axi.read_cnt_reg ),
        .R(SR));
  FDRE \gen_axi.read_cnt_reg[1] 
       (.C(aclk),
        .CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
        .D(p_0_in[1]),
        .Q(\gen_axi.read_cnt_reg__0 [1]),
        .R(SR));
  FDRE \gen_axi.read_cnt_reg[2] 
       (.C(aclk),
        .CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
        .D(p_0_in[2]),
        .Q(\gen_axi.read_cnt_reg__0 [2]),
        .R(SR));
  FDRE \gen_axi.read_cnt_reg[3] 
       (.C(aclk),
        .CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
        .D(p_0_in[3]),
        .Q(\gen_axi.read_cnt_reg__0 [3]),
        .R(SR));
  FDRE \gen_axi.read_cnt_reg[4] 
       (.C(aclk),
        .CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
        .D(p_0_in[4]),
        .Q(\gen_axi.read_cnt_reg__0 [4]),
        .R(SR));
  FDRE \gen_axi.read_cnt_reg[5] 
       (.C(aclk),
        .CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
        .D(p_0_in[5]),
        .Q(\gen_axi.read_cnt_reg__0 [5]),
        .R(SR));
  FDRE \gen_axi.read_cnt_reg[6] 
       (.C(aclk),
        .CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
        .D(p_0_in[6]),
        .Q(\gen_axi.read_cnt_reg__0 [6]),
        .R(SR));
  FDRE \gen_axi.read_cnt_reg[7] 
       (.C(aclk),
        .CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
        .D(p_0_in[7]),
        .Q(\gen_axi.read_cnt_reg__0 [7]),
        .R(SR));
  LUT6 #(
    .INIT(64'hDFD0D0D0F0F0F0F0)) 
    \gen_axi.read_cs[0]_i_1 
       (.I0(aa_rready),
        .I1(\gen_axi.read_cnt[7]_i_3_n_0 ),
        .I2(mi_rvalid),
        .I3(mi_arready),
        .I4(\gen_axi.s_axi_arready_i_reg_0 ),
        .I5(Q),
        .O(\gen_axi.read_cs[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \gen_axi.read_cs_reg[0] 
       (.C(aclk),
        .CE(1'b1),
        .D(\gen_axi.read_cs[0]_i_1_n_0 ),
        .Q(mi_rvalid),
        .R(SR));
  LUT6 #(
    .INIT(64'hC088C888C888C888)) 
    \gen_axi.s_axi_arready_i_i_1 
       (.I0(\gen_axi.s_axi_arready_i_i_2_n_0 ),
        .I1(aresetn_d),
        .I2(mi_rvalid),
        .I3(mi_arready),
        .I4(\gen_axi.s_axi_arready_i_reg_0 ),
        .I5(Q),
        .O(\gen_axi.s_axi_arready_i_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h01000000FFFFFFFF)) 
    \gen_axi.s_axi_arready_i_i_2 
       (.I0(\gen_axi.read_cnt[7]_i_5_n_0 ),
        .I1(\gen_axi.read_cnt_reg__0 [6]),
        .I2(\gen_axi.read_cnt_reg__0 [7]),
        .I3(Q),
        .I4(aa_rready),
        .I5(mi_rvalid),
        .O(\gen_axi.s_axi_arready_i_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \gen_axi.s_axi_arready_i_reg 
       (.C(aclk),
        .CE(1'b1),
        .D(\gen_axi.s_axi_arready_i_i_1_n_0 ),
        .Q(mi_arready),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFDFFFFFFFF00)) 
    \gen_axi.s_axi_awready_i_i_1 
       (.I0(Q),
        .I1(\gen_axi.s_axi_awready_i_reg_2 ),
        .I2(\FSM_onehot_gen_axi.write_cs_reg_n_0_[1] ),
        .I3(\FSM_onehot_gen_axi.write_cs_reg_n_0_[0] ),
        .I4(\gen_axi.s_axi_awready_i_reg_1 ),
        .I5(mi_awready),
        .O(\gen_axi.s_axi_awready_i_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \gen_axi.s_axi_awready_i_reg 
       (.C(aclk),
        .CE(1'b1),
        .D(\gen_axi.s_axi_awready_i_i_1_n_0 ),
        .Q(mi_awready),
        .R(SR));
  LUT6 #(
    .INIT(64'h0080FFFF00800080)) 
    \gen_axi.s_axi_bvalid_i_i_1 
       (.I0(Q),
        .I1(\FSM_onehot_gen_axi.write_cs_reg_n_0_[1] ),
        .I2(s_axi_wlast),
        .I3(\gen_axi.s_axi_wready_i_reg_1 ),
        .I4(\gen_axi.s_axi_awready_i_reg_1 ),
        .I5(mi_bvalid),
        .O(\gen_axi.s_axi_bvalid_i_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \gen_axi.s_axi_bvalid_i_reg 
       (.C(aclk),
        .CE(1'b1),
        .D(\gen_axi.s_axi_bvalid_i_i_1_n_0 ),
        .Q(mi_bvalid),
        .R(SR));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \gen_axi.s_axi_rlast_i_i_1 
       (.I0(\gen_axi.read_cnt[7]_i_3_n_0 ),
        .I1(mi_rvalid),
        .I2(\gen_axi.s_axi_rlast_i_reg_1 ),
        .I3(\gen_axi.s_axi_rlast_i_i_3_n_0 ),
        .I4(mi_rmesg),
        .O(\gen_axi.s_axi_rlast_i_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAABAA)) 
    \gen_axi.s_axi_rlast_i_i_3 
       (.I0(\gen_axi.s_axi_rid_i ),
        .I1(\gen_axi.s_axi_rlast_i_i_6_n_0 ),
        .I2(\gen_axi.read_cnt_reg__0 [1]),
        .I3(mi_rvalid),
        .I4(\gen_axi.read_cnt_reg__0 [5]),
        .I5(\gen_axi.read_cnt_reg__0 [2]),
        .O(\gen_axi.s_axi_rlast_i_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFFFFFFFFFF)) 
    \gen_axi.s_axi_rlast_i_i_6 
       (.I0(\gen_axi.read_cnt_reg__0 [7]),
        .I1(\gen_axi.read_cnt_reg__0 [6]),
        .I2(\gen_axi.read_cnt_reg__0 [4]),
        .I3(\gen_axi.read_cnt_reg__0 [3]),
        .I4(aa_rready),
        .I5(Q),
        .O(\gen_axi.s_axi_rlast_i_i_6_n_0 ));
  FDRE \gen_axi.s_axi_rlast_i_reg 
       (.C(aclk),
        .CE(1'b1),
        .D(\gen_axi.s_axi_rlast_i_i_1_n_0 ),
        .Q(mi_rmesg),
        .R(SR));
  LUT6 #(
    .INIT(64'hFFFFFF7FFFFF0000)) 
    \gen_axi.s_axi_wready_i_i_1 
       (.I0(Q),
        .I1(\FSM_onehot_gen_axi.write_cs_reg_n_0_[1] ),
        .I2(s_axi_wlast),
        .I3(\gen_axi.s_axi_wready_i_reg_1 ),
        .I4(\gen_axi.s_axi_wready_i_i_3_n_0 ),
        .I5(mi_wready),
        .O(\gen_axi.s_axi_wready_i_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000800000)) 
    \gen_axi.s_axi_wready_i_i_3 
       (.I0(\FSM_onehot_gen_axi.write_cs_reg_n_0_[0] ),
        .I1(Q),
        .I2(mi_awready),
        .I3(m_ready_d[2]),
        .I4(m_valid_i),
        .I5(aa_grant_rnw),
        .O(\gen_axi.s_axi_wready_i_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \gen_axi.s_axi_wready_i_reg 
       (.C(aclk),
        .CE(1'b1),
        .D(\gen_axi.s_axi_wready_i_i_1_n_0 ),
        .Q(mi_wready),
        .R(SR));
  LUT6 #(
    .INIT(64'h07070707FFFF07FF)) 
    \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2 
       (.I0(\gen_axi.s_axi_wready_i_reg_0 ),
        .I1(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv ),
        .I2(m_ready_d[1]),
        .I3(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ),
        .I4(\gen_axi.s_axi_bvalid_i_reg_0 ),
        .I5(m_ready_d[0]),
        .O(\m_ready_d_reg[1] ));
  LUT6 #(
    .INIT(64'h00330F55FF330F55)) 
    \m_ready_d[1]_i_2 
       (.I0(m_axi_arready[0]),
        .I1(m_axi_arready[2]),
        .I2(m_axi_arready[1]),
        .I3(\skid_buffer_reg[0] [0]),
        .I4(\skid_buffer_reg[0] [1]),
        .I5(mi_arready),
        .O(m_axi_arready_0_sn_1));
  LUT6 #(
    .INIT(64'hAAFFCCF0AA00CCF0)) 
    \m_ready_d[2]_i_5 
       (.I0(mi_awready),
        .I1(m_axi_awready[2]),
        .I2(m_axi_awready[0]),
        .I3(\skid_buffer_reg[0] [1]),
        .I4(\skid_buffer_reg[0] [0]),
        .I5(m_axi_awready[1]),
        .O(\gen_axi.s_axi_awready_i_reg_0 ));
  LUT6 #(
    .INIT(64'hFFCCF0AA00CCF0AA)) 
    m_valid_i_i_3
       (.I0(m_axi_rvalid[0]),
        .I1(m_axi_rvalid[1]),
        .I2(m_axi_rvalid[2]),
        .I3(\skid_buffer_reg[0] [1]),
        .I4(\skid_buffer_reg[0] [0]),
        .I5(mi_rvalid),
        .O(m_axi_rvalid_0_sn_1));
  LUT6 #(
    .INIT(64'h55000F3355FF0F33)) 
    \s_axi_bvalid[0]_INST_0_i_1 
       (.I0(mi_bvalid),
        .I1(m_axi_bvalid[0]),
        .I2(m_axi_bvalid[1]),
        .I3(\skid_buffer_reg[0] [0]),
        .I4(\skid_buffer_reg[0] [1]),
        .I5(m_axi_bvalid[2]),
        .O(\gen_axi.s_axi_bvalid_i_reg_0 ));
  LUT6 #(
    .INIT(64'hAAFFF0CCAA00F0CC)) 
    \s_axi_wready[0]_INST_0_i_1 
       (.I0(mi_wready),
        .I1(m_axi_wready[0]),
        .I2(m_axi_wready[1]),
        .I3(\skid_buffer_reg[0] [0]),
        .I4(\skid_buffer_reg[0] [1]),
        .I5(m_axi_wready[2]),
        .O(\gen_axi.s_axi_wready_i_reg_0 ));
  LUT6 #(
    .INIT(64'hAAFFF0CCAA00F0CC)) 
    \skid_buffer[0]_i_1 
       (.I0(mi_rmesg),
        .I1(m_axi_rlast[0]),
        .I2(m_axi_rlast[2]),
        .I3(\skid_buffer_reg[0] [1]),
        .I4(\skid_buffer_reg[0] [0]),
        .I5(m_axi_rlast[1]),
        .O(\gen_axi.s_axi_rlast_i_reg_0 ));
endmodule

(* ORIG_REF_NAME = "axi_crossbar_v2_1_23_splitter" *) 
module blok_xbar_0_axi_crossbar_v2_1_23_splitter
   (m_ready_d,
    aresetn_d,
    m_ready_d0,
    \m_ready_d_reg[2]_0 ,
    \m_ready_d_reg[2]_1 ,
    \m_ready_d_reg[2]_2 ,
    aclk);
  output [2:0]m_ready_d;
  input aresetn_d;
  input [0:0]m_ready_d0;
  input \m_ready_d_reg[2]_0 ;
  input \m_ready_d_reg[2]_1 ;
  input \m_ready_d_reg[2]_2 ;
  input aclk;

  wire aclk;
  wire aresetn_d;
  wire [2:0]m_ready_d;
  wire [0:0]m_ready_d0;
  wire \m_ready_d[0]_i_1_n_0 ;
  wire \m_ready_d[1]_i_1_n_0 ;
  wire \m_ready_d[2]_i_1_n_0 ;
  wire \m_ready_d_reg[2]_0 ;
  wire \m_ready_d_reg[2]_1 ;
  wire \m_ready_d_reg[2]_2 ;

  LUT6 #(
    .INIT(64'hA0AAA0A020222020)) 
    \m_ready_d[0]_i_1 
       (.I0(aresetn_d),
        .I1(m_ready_d0),
        .I2(m_ready_d[0]),
        .I3(\m_ready_d_reg[2]_0 ),
        .I4(\m_ready_d_reg[2]_1 ),
        .I5(\m_ready_d_reg[2]_2 ),
        .O(\m_ready_d[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000002A222A2A)) 
    \m_ready_d[1]_i_1 
       (.I0(aresetn_d),
        .I1(m_ready_d0),
        .I2(m_ready_d[0]),
        .I3(\m_ready_d_reg[2]_0 ),
        .I4(\m_ready_d_reg[2]_1 ),
        .I5(\m_ready_d_reg[2]_2 ),
        .O(\m_ready_d[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8888888808000808)) 
    \m_ready_d[2]_i_1 
       (.I0(aresetn_d),
        .I1(m_ready_d0),
        .I2(m_ready_d[0]),
        .I3(\m_ready_d_reg[2]_0 ),
        .I4(\m_ready_d_reg[2]_1 ),
        .I5(\m_ready_d_reg[2]_2 ),
        .O(\m_ready_d[2]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \m_ready_d_reg[0] 
       (.C(aclk),
        .CE(1'b1),
        .D(\m_ready_d[0]_i_1_n_0 ),
        .Q(m_ready_d[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \m_ready_d_reg[1] 
       (.C(aclk),
        .CE(1'b1),
        .D(\m_ready_d[1]_i_1_n_0 ),
        .Q(m_ready_d[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \m_ready_d_reg[2] 
       (.C(aclk),
        .CE(1'b1),
        .D(\m_ready_d[2]_i_1_n_0 ),
        .Q(m_ready_d[2]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "axi_crossbar_v2_1_23_splitter" *) 
module blok_xbar_0_axi_crossbar_v2_1_23_splitter__parameterized0
   (m_ready_d,
    m_valid_i,
    aa_grant_rnw,
    \m_ready_d_reg[1]_0 ,
    m_ready_d0,
    aresetn_d,
    aclk);
  output [1:0]m_ready_d;
  input m_valid_i;
  input aa_grant_rnw;
  input \m_ready_d_reg[1]_0 ;
  input [0:0]m_ready_d0;
  input aresetn_d;
  input aclk;

  wire aa_grant_rnw;
  wire aclk;
  wire aresetn_d;
  wire [1:0]m_ready_d;
  wire [0:0]m_ready_d0;
  wire \m_ready_d[0]_i_1_n_0 ;
  wire \m_ready_d[1]_i_1_n_0 ;
  wire \m_ready_d_reg[1]_0 ;
  wire m_valid_i;

  LUT6 #(
    .INIT(64'h0F07000000000000)) 
    \m_ready_d[0]_i_1 
       (.I0(m_valid_i),
        .I1(aa_grant_rnw),
        .I2(m_ready_d[1]),
        .I3(\m_ready_d_reg[1]_0 ),
        .I4(m_ready_d0),
        .I5(aresetn_d),
        .O(\m_ready_d[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000F0F800000000)) 
    \m_ready_d[1]_i_1 
       (.I0(m_valid_i),
        .I1(aa_grant_rnw),
        .I2(m_ready_d[1]),
        .I3(\m_ready_d_reg[1]_0 ),
        .I4(m_ready_d0),
        .I5(aresetn_d),
        .O(\m_ready_d[1]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \m_ready_d_reg[0] 
       (.C(aclk),
        .CE(1'b1),
        .D(\m_ready_d[0]_i_1_n_0 ),
        .Q(m_ready_d[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \m_ready_d_reg[1] 
       (.C(aclk),
        .CE(1'b1),
        .D(\m_ready_d[1]_i_1_n_0 ),
        .Q(m_ready_d[1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "axi_register_slice_v2_1_22_axic_register_slice" *) 
module blok_xbar_0_axi_register_slice_v2_1_22_axic_register_slice
   (sr_rvalid,
    aa_rready,
    m_ready_d0,
    \m_payload_i_reg[34]_0 ,
    s_axi_rvalid,
    m_axi_rready,
    \aresetn_d_reg[1]_0 ,
    m_valid_i_reg_0,
    aclk,
    s_ready_i_reg_0,
    s_axi_rready,
    m_valid_i,
    aa_grant_rnw,
    m_ready_d,
    \skid_buffer_reg[0]_0 ,
    m_axi_rresp,
    Q,
    m_axi_rdata,
    p_0_in1_in,
    \m_axi_rready[2] ,
    SR,
    E);
  output sr_rvalid;
  output aa_rready;
  output [0:0]m_ready_d0;
  output [34:0]\m_payload_i_reg[34]_0 ;
  output [0:0]s_axi_rvalid;
  output [2:0]m_axi_rready;
  output [1:0]\aresetn_d_reg[1]_0 ;
  input m_valid_i_reg_0;
  input aclk;
  input s_ready_i_reg_0;
  input [0:0]s_axi_rready;
  input m_valid_i;
  input aa_grant_rnw;
  input [0:0]m_ready_d;
  input \skid_buffer_reg[0]_0 ;
  input [5:0]m_axi_rresp;
  input [1:0]Q;
  input [95:0]m_axi_rdata;
  input p_0_in1_in;
  input [2:0]\m_axi_rready[2] ;
  input [0:0]SR;
  input [0:0]E;

  wire [0:0]E;
  wire [1:0]Q;
  wire [0:0]SR;
  wire aa_grant_rnw;
  wire aa_rready;
  wire aclk;
  wire [1:0]\aresetn_d_reg[1]_0 ;
  wire [95:0]m_axi_rdata;
  wire [2:0]m_axi_rready;
  wire [2:0]\m_axi_rready[2] ;
  wire [5:0]m_axi_rresp;
  wire \m_payload_i[12]_i_2_n_0 ;
  wire \m_payload_i[13]_i_2_n_0 ;
  wire \m_payload_i[14]_i_2_n_0 ;
  wire \m_payload_i[15]_i_2_n_0 ;
  wire \m_payload_i[17]_i_2_n_0 ;
  wire \m_payload_i[18]_i_2_n_0 ;
  wire \m_payload_i[1]_i_2_n_0 ;
  wire \m_payload_i[25]_i_2_n_0 ;
  wire \m_payload_i[26]_i_2_n_0 ;
  wire \m_payload_i[28]_i_2_n_0 ;
  wire \m_payload_i[29]_i_2_n_0 ;
  wire \m_payload_i[2]_i_2_n_0 ;
  wire \m_payload_i[30]_i_2_n_0 ;
  wire \m_payload_i[31]_i_2_n_0 ;
  wire \m_payload_i[33]_i_2_n_0 ;
  wire \m_payload_i[34]_i_3_n_0 ;
  wire \m_payload_i[5]_i_2_n_0 ;
  wire \m_payload_i[6]_i_2_n_0 ;
  wire \m_payload_i[7]_i_2_n_0 ;
  wire [34:0]\m_payload_i_reg[34]_0 ;
  wire [0:0]m_ready_d;
  wire [0:0]m_ready_d0;
  wire m_valid_i;
  wire m_valid_i_reg_0;
  wire p_0_in1_in;
  wire [0:0]s_axi_rready;
  wire [0:0]s_axi_rvalid;
  wire s_ready_i_reg_0;
  wire [34:0]skid_buffer;
  wire \skid_buffer[10]_i_1_n_0 ;
  wire \skid_buffer[11]_i_1_n_0 ;
  wire \skid_buffer[16]_i_1_n_0 ;
  wire \skid_buffer[19]_i_1_n_0 ;
  wire \skid_buffer[20]_i_1_n_0 ;
  wire \skid_buffer[21]_i_1_n_0 ;
  wire \skid_buffer[22]_i_1_n_0 ;
  wire \skid_buffer[23]_i_1_n_0 ;
  wire \skid_buffer[24]_i_1_n_0 ;
  wire \skid_buffer[27]_i_1_n_0 ;
  wire \skid_buffer[32]_i_1_n_0 ;
  wire \skid_buffer[3]_i_1_n_0 ;
  wire \skid_buffer[4]_i_1_n_0 ;
  wire \skid_buffer[8]_i_1_n_0 ;
  wire \skid_buffer[9]_i_1_n_0 ;
  wire \skid_buffer_reg[0]_0 ;
  wire \skid_buffer_reg_n_0_[0] ;
  wire \skid_buffer_reg_n_0_[10] ;
  wire \skid_buffer_reg_n_0_[11] ;
  wire \skid_buffer_reg_n_0_[12] ;
  wire \skid_buffer_reg_n_0_[13] ;
  wire \skid_buffer_reg_n_0_[14] ;
  wire \skid_buffer_reg_n_0_[15] ;
  wire \skid_buffer_reg_n_0_[16] ;
  wire \skid_buffer_reg_n_0_[17] ;
  wire \skid_buffer_reg_n_0_[18] ;
  wire \skid_buffer_reg_n_0_[19] ;
  wire \skid_buffer_reg_n_0_[1] ;
  wire \skid_buffer_reg_n_0_[20] ;
  wire \skid_buffer_reg_n_0_[21] ;
  wire \skid_buffer_reg_n_0_[22] ;
  wire \skid_buffer_reg_n_0_[23] ;
  wire \skid_buffer_reg_n_0_[24] ;
  wire \skid_buffer_reg_n_0_[25] ;
  wire \skid_buffer_reg_n_0_[26] ;
  wire \skid_buffer_reg_n_0_[27] ;
  wire \skid_buffer_reg_n_0_[28] ;
  wire \skid_buffer_reg_n_0_[29] ;
  wire \skid_buffer_reg_n_0_[2] ;
  wire \skid_buffer_reg_n_0_[30] ;
  wire \skid_buffer_reg_n_0_[31] ;
  wire \skid_buffer_reg_n_0_[32] ;
  wire \skid_buffer_reg_n_0_[33] ;
  wire \skid_buffer_reg_n_0_[34] ;
  wire \skid_buffer_reg_n_0_[3] ;
  wire \skid_buffer_reg_n_0_[4] ;
  wire \skid_buffer_reg_n_0_[5] ;
  wire \skid_buffer_reg_n_0_[6] ;
  wire \skid_buffer_reg_n_0_[7] ;
  wire \skid_buffer_reg_n_0_[8] ;
  wire \skid_buffer_reg_n_0_[9] ;
  wire sr_rvalid;

  FDRE #(
    .INIT(1'b0)) 
    \aresetn_d_reg[0] 
       (.C(aclk),
        .CE(1'b1),
        .D(1'b1),
        .Q(\aresetn_d_reg[1]_0 [0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \aresetn_d_reg[1] 
       (.C(aclk),
        .CE(1'b1),
        .D(\aresetn_d_reg[1]_0 [0]),
        .Q(\aresetn_d_reg[1]_0 [1]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_rready[0]_INST_0 
       (.I0(aa_rready),
        .I1(\m_axi_rready[2] [0]),
        .O(m_axi_rready[0]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_rready[1]_INST_0 
       (.I0(aa_rready),
        .I1(\m_axi_rready[2] [1]),
        .O(m_axi_rready[1]));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_rready[2]_INST_0 
       (.I0(aa_rready),
        .I1(\m_axi_rready[2] [2]),
        .O(m_axi_rready[2]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_payload_i[0]_i_1 
       (.I0(\skid_buffer_reg[0]_0 ),
        .I1(aa_rready),
        .I2(\skid_buffer_reg_n_0_[0] ),
        .O(skid_buffer[0]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_payload_i[10]_i_1 
       (.I0(\skid_buffer[10]_i_1_n_0 ),
        .I1(aa_rready),
        .I2(\skid_buffer_reg_n_0_[10] ),
        .O(skid_buffer[10]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_payload_i[11]_i_1 
       (.I0(\skid_buffer[11]_i_1_n_0 ),
        .I1(aa_rready),
        .I2(\skid_buffer_reg_n_0_[11] ),
        .O(skid_buffer[11]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[12]_i_1 
       (.I0(\skid_buffer_reg_n_0_[12] ),
        .I1(aa_rready),
        .I2(\m_payload_i[12]_i_2_n_0 ),
        .O(skid_buffer[12]));
  LUT6 #(
    .INIT(64'h0000440C00CC440C)) 
    \m_payload_i[12]_i_2 
       (.I0(m_axi_rdata[73]),
        .I1(aa_rready),
        .I2(m_axi_rdata[9]),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(m_axi_rdata[41]),
        .O(\m_payload_i[12]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[13]_i_1 
       (.I0(\skid_buffer_reg_n_0_[13] ),
        .I1(aa_rready),
        .I2(\m_payload_i[13]_i_2_n_0 ),
        .O(skid_buffer[13]));
  LUT6 #(
    .INIT(64'h0000440C00CC440C)) 
    \m_payload_i[13]_i_2 
       (.I0(m_axi_rdata[74]),
        .I1(aa_rready),
        .I2(m_axi_rdata[10]),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(m_axi_rdata[42]),
        .O(\m_payload_i[13]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[14]_i_1 
       (.I0(\skid_buffer_reg_n_0_[14] ),
        .I1(aa_rready),
        .I2(\m_payload_i[14]_i_2_n_0 ),
        .O(skid_buffer[14]));
  LUT6 #(
    .INIT(64'h030503F500000000)) 
    \m_payload_i[14]_i_2 
       (.I0(m_axi_rdata[11]),
        .I1(m_axi_rdata[43]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(m_axi_rdata[75]),
        .I5(aa_rready),
        .O(\m_payload_i[14]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[15]_i_1 
       (.I0(\skid_buffer_reg_n_0_[15] ),
        .I1(aa_rready),
        .I2(\m_payload_i[15]_i_2_n_0 ),
        .O(skid_buffer[15]));
  LUT6 #(
    .INIT(64'h00000C4400CC0C44)) 
    \m_payload_i[15]_i_2 
       (.I0(m_axi_rdata[12]),
        .I1(aa_rready),
        .I2(m_axi_rdata[44]),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(m_axi_rdata[76]),
        .O(\m_payload_i[15]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_payload_i[16]_i_1 
       (.I0(\skid_buffer[16]_i_1_n_0 ),
        .I1(aa_rready),
        .I2(\skid_buffer_reg_n_0_[16] ),
        .O(skid_buffer[16]));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[17]_i_1 
       (.I0(\skid_buffer_reg_n_0_[17] ),
        .I1(aa_rready),
        .I2(\m_payload_i[17]_i_2_n_0 ),
        .O(skid_buffer[17]));
  LUT6 #(
    .INIT(64'h00000C4400CC0C44)) 
    \m_payload_i[17]_i_2 
       (.I0(m_axi_rdata[14]),
        .I1(aa_rready),
        .I2(m_axi_rdata[46]),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(m_axi_rdata[78]),
        .O(\m_payload_i[17]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[18]_i_1 
       (.I0(\skid_buffer_reg_n_0_[18] ),
        .I1(aa_rready),
        .I2(\m_payload_i[18]_i_2_n_0 ),
        .O(skid_buffer[18]));
  LUT6 #(
    .INIT(64'h00000C4400CC0C44)) 
    \m_payload_i[18]_i_2 
       (.I0(m_axi_rdata[15]),
        .I1(aa_rready),
        .I2(m_axi_rdata[47]),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(m_axi_rdata[79]),
        .O(\m_payload_i[18]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_payload_i[19]_i_1 
       (.I0(\skid_buffer[19]_i_1_n_0 ),
        .I1(aa_rready),
        .I2(\skid_buffer_reg_n_0_[19] ),
        .O(skid_buffer[19]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[1]_i_1 
       (.I0(\skid_buffer_reg_n_0_[1] ),
        .I1(aa_rready),
        .I2(\m_payload_i[1]_i_2_n_0 ),
        .O(skid_buffer[1]));
  LUT6 #(
    .INIT(64'h0000440C00CC440C)) 
    \m_payload_i[1]_i_2 
       (.I0(m_axi_rresp[4]),
        .I1(aa_rready),
        .I2(m_axi_rresp[0]),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(m_axi_rresp[2]),
        .O(\m_payload_i[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_payload_i[20]_i_1 
       (.I0(\skid_buffer[20]_i_1_n_0 ),
        .I1(aa_rready),
        .I2(\skid_buffer_reg_n_0_[20] ),
        .O(skid_buffer[20]));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_payload_i[21]_i_1 
       (.I0(\skid_buffer[21]_i_1_n_0 ),
        .I1(aa_rready),
        .I2(\skid_buffer_reg_n_0_[21] ),
        .O(skid_buffer[21]));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_payload_i[22]_i_1 
       (.I0(\skid_buffer[22]_i_1_n_0 ),
        .I1(aa_rready),
        .I2(\skid_buffer_reg_n_0_[22] ),
        .O(skid_buffer[22]));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_payload_i[23]_i_1 
       (.I0(\skid_buffer[23]_i_1_n_0 ),
        .I1(aa_rready),
        .I2(\skid_buffer_reg_n_0_[23] ),
        .O(skid_buffer[23]));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_payload_i[24]_i_1 
       (.I0(\skid_buffer[24]_i_1_n_0 ),
        .I1(aa_rready),
        .I2(\skid_buffer_reg_n_0_[24] ),
        .O(skid_buffer[24]));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[25]_i_1 
       (.I0(\skid_buffer_reg_n_0_[25] ),
        .I1(aa_rready),
        .I2(\m_payload_i[25]_i_2_n_0 ),
        .O(skid_buffer[25]));
  LUT6 #(
    .INIT(64'h00000C4400CC0C44)) 
    \m_payload_i[25]_i_2 
       (.I0(m_axi_rdata[22]),
        .I1(aa_rready),
        .I2(m_axi_rdata[54]),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(m_axi_rdata[86]),
        .O(\m_payload_i[25]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[26]_i_1 
       (.I0(\skid_buffer_reg_n_0_[26] ),
        .I1(aa_rready),
        .I2(\m_payload_i[26]_i_2_n_0 ),
        .O(skid_buffer[26]));
  LUT6 #(
    .INIT(64'h0530053F00000000)) 
    \m_payload_i[26]_i_2 
       (.I0(m_axi_rdata[55]),
        .I1(m_axi_rdata[87]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(m_axi_rdata[23]),
        .I5(aa_rready),
        .O(\m_payload_i[26]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_payload_i[27]_i_1 
       (.I0(\skid_buffer[27]_i_1_n_0 ),
        .I1(aa_rready),
        .I2(\skid_buffer_reg_n_0_[27] ),
        .O(skid_buffer[27]));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[28]_i_1 
       (.I0(\skid_buffer_reg_n_0_[28] ),
        .I1(aa_rready),
        .I2(\m_payload_i[28]_i_2_n_0 ),
        .O(skid_buffer[28]));
  LUT6 #(
    .INIT(64'h0530053F00000000)) 
    \m_payload_i[28]_i_2 
       (.I0(m_axi_rdata[57]),
        .I1(m_axi_rdata[89]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(m_axi_rdata[25]),
        .I5(aa_rready),
        .O(\m_payload_i[28]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[29]_i_1 
       (.I0(\skid_buffer_reg_n_0_[29] ),
        .I1(aa_rready),
        .I2(\m_payload_i[29]_i_2_n_0 ),
        .O(skid_buffer[29]));
  LUT6 #(
    .INIT(64'h0000440C00CC440C)) 
    \m_payload_i[29]_i_2 
       (.I0(m_axi_rdata[90]),
        .I1(aa_rready),
        .I2(m_axi_rdata[26]),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(m_axi_rdata[58]),
        .O(\m_payload_i[29]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[2]_i_1 
       (.I0(\skid_buffer_reg_n_0_[2] ),
        .I1(aa_rready),
        .I2(\m_payload_i[2]_i_2_n_0 ),
        .O(skid_buffer[2]));
  LUT6 #(
    .INIT(64'h0000440C00CC440C)) 
    \m_payload_i[2]_i_2 
       (.I0(m_axi_rresp[5]),
        .I1(aa_rready),
        .I2(m_axi_rresp[1]),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(m_axi_rresp[3]),
        .O(\m_payload_i[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[30]_i_1 
       (.I0(\skid_buffer_reg_n_0_[30] ),
        .I1(aa_rready),
        .I2(\m_payload_i[30]_i_2_n_0 ),
        .O(skid_buffer[30]));
  LUT6 #(
    .INIT(64'h030503F500000000)) 
    \m_payload_i[30]_i_2 
       (.I0(m_axi_rdata[27]),
        .I1(m_axi_rdata[59]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(m_axi_rdata[91]),
        .I5(aa_rready),
        .O(\m_payload_i[30]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[31]_i_1 
       (.I0(\skid_buffer_reg_n_0_[31] ),
        .I1(aa_rready),
        .I2(\m_payload_i[31]_i_2_n_0 ),
        .O(skid_buffer[31]));
  LUT6 #(
    .INIT(64'h00000C4400CC0C44)) 
    \m_payload_i[31]_i_2 
       (.I0(m_axi_rdata[28]),
        .I1(aa_rready),
        .I2(m_axi_rdata[60]),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(m_axi_rdata[92]),
        .O(\m_payload_i[31]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_payload_i[32]_i_1 
       (.I0(\skid_buffer[32]_i_1_n_0 ),
        .I1(aa_rready),
        .I2(\skid_buffer_reg_n_0_[32] ),
        .O(skid_buffer[32]));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[33]_i_1 
       (.I0(\skid_buffer_reg_n_0_[33] ),
        .I1(aa_rready),
        .I2(\m_payload_i[33]_i_2_n_0 ),
        .O(skid_buffer[33]));
  LUT6 #(
    .INIT(64'h0000440C00CC440C)) 
    \m_payload_i[33]_i_2 
       (.I0(m_axi_rdata[94]),
        .I1(aa_rready),
        .I2(m_axi_rdata[30]),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(m_axi_rdata[62]),
        .O(\m_payload_i[33]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[34]_i_2 
       (.I0(\skid_buffer_reg_n_0_[34] ),
        .I1(aa_rready),
        .I2(\m_payload_i[34]_i_3_n_0 ),
        .O(skid_buffer[34]));
  LUT6 #(
    .INIT(64'h0000440C00CC440C)) 
    \m_payload_i[34]_i_3 
       (.I0(m_axi_rdata[95]),
        .I1(aa_rready),
        .I2(m_axi_rdata[31]),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(m_axi_rdata[63]),
        .O(\m_payload_i[34]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_payload_i[3]_i_1 
       (.I0(\skid_buffer[3]_i_1_n_0 ),
        .I1(aa_rready),
        .I2(\skid_buffer_reg_n_0_[3] ),
        .O(skid_buffer[3]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_payload_i[4]_i_1 
       (.I0(\skid_buffer[4]_i_1_n_0 ),
        .I1(aa_rready),
        .I2(\skid_buffer_reg_n_0_[4] ),
        .O(skid_buffer[4]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[5]_i_1 
       (.I0(\skid_buffer_reg_n_0_[5] ),
        .I1(aa_rready),
        .I2(\m_payload_i[5]_i_2_n_0 ),
        .O(skid_buffer[5]));
  LUT6 #(
    .INIT(64'h0000440C00CC440C)) 
    \m_payload_i[5]_i_2 
       (.I0(m_axi_rdata[66]),
        .I1(aa_rready),
        .I2(m_axi_rdata[2]),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(m_axi_rdata[34]),
        .O(\m_payload_i[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[6]_i_1 
       (.I0(\skid_buffer_reg_n_0_[6] ),
        .I1(aa_rready),
        .I2(\m_payload_i[6]_i_2_n_0 ),
        .O(skid_buffer[6]));
  LUT6 #(
    .INIT(64'h0000440C00CC440C)) 
    \m_payload_i[6]_i_2 
       (.I0(m_axi_rdata[67]),
        .I1(aa_rready),
        .I2(m_axi_rdata[3]),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(m_axi_rdata[35]),
        .O(\m_payload_i[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \m_payload_i[7]_i_1 
       (.I0(\skid_buffer_reg_n_0_[7] ),
        .I1(aa_rready),
        .I2(\m_payload_i[7]_i_2_n_0 ),
        .O(skid_buffer[7]));
  LUT6 #(
    .INIT(64'h0000440C00CC440C)) 
    \m_payload_i[7]_i_2 
       (.I0(m_axi_rdata[68]),
        .I1(aa_rready),
        .I2(m_axi_rdata[4]),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(m_axi_rdata[36]),
        .O(\m_payload_i[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_payload_i[8]_i_1 
       (.I0(\skid_buffer[8]_i_1_n_0 ),
        .I1(aa_rready),
        .I2(\skid_buffer_reg_n_0_[8] ),
        .O(skid_buffer[8]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_payload_i[9]_i_1 
       (.I0(\skid_buffer[9]_i_1_n_0 ),
        .I1(aa_rready),
        .I2(\skid_buffer_reg_n_0_[9] ),
        .O(skid_buffer[9]));
  FDRE \m_payload_i_reg[0] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[0]),
        .Q(\m_payload_i_reg[34]_0 [0]),
        .R(1'b0));
  FDRE \m_payload_i_reg[10] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[10]),
        .Q(\m_payload_i_reg[34]_0 [10]),
        .R(1'b0));
  FDRE \m_payload_i_reg[11] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[11]),
        .Q(\m_payload_i_reg[34]_0 [11]),
        .R(1'b0));
  FDRE \m_payload_i_reg[12] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[12]),
        .Q(\m_payload_i_reg[34]_0 [12]),
        .R(1'b0));
  FDRE \m_payload_i_reg[13] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[13]),
        .Q(\m_payload_i_reg[34]_0 [13]),
        .R(1'b0));
  FDRE \m_payload_i_reg[14] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[14]),
        .Q(\m_payload_i_reg[34]_0 [14]),
        .R(1'b0));
  FDRE \m_payload_i_reg[15] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[15]),
        .Q(\m_payload_i_reg[34]_0 [15]),
        .R(1'b0));
  FDRE \m_payload_i_reg[16] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[16]),
        .Q(\m_payload_i_reg[34]_0 [16]),
        .R(1'b0));
  FDRE \m_payload_i_reg[17] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[17]),
        .Q(\m_payload_i_reg[34]_0 [17]),
        .R(1'b0));
  FDRE \m_payload_i_reg[18] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[18]),
        .Q(\m_payload_i_reg[34]_0 [18]),
        .R(1'b0));
  FDRE \m_payload_i_reg[19] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[19]),
        .Q(\m_payload_i_reg[34]_0 [19]),
        .R(1'b0));
  FDRE \m_payload_i_reg[1] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[1]),
        .Q(\m_payload_i_reg[34]_0 [1]),
        .R(1'b0));
  FDRE \m_payload_i_reg[20] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[20]),
        .Q(\m_payload_i_reg[34]_0 [20]),
        .R(1'b0));
  FDRE \m_payload_i_reg[21] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[21]),
        .Q(\m_payload_i_reg[34]_0 [21]),
        .R(1'b0));
  FDRE \m_payload_i_reg[22] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[22]),
        .Q(\m_payload_i_reg[34]_0 [22]),
        .R(1'b0));
  FDRE \m_payload_i_reg[23] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[23]),
        .Q(\m_payload_i_reg[34]_0 [23]),
        .R(1'b0));
  FDRE \m_payload_i_reg[24] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[24]),
        .Q(\m_payload_i_reg[34]_0 [24]),
        .R(1'b0));
  FDRE \m_payload_i_reg[25] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[25]),
        .Q(\m_payload_i_reg[34]_0 [25]),
        .R(1'b0));
  FDRE \m_payload_i_reg[26] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[26]),
        .Q(\m_payload_i_reg[34]_0 [26]),
        .R(1'b0));
  FDRE \m_payload_i_reg[27] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[27]),
        .Q(\m_payload_i_reg[34]_0 [27]),
        .R(1'b0));
  FDRE \m_payload_i_reg[28] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[28]),
        .Q(\m_payload_i_reg[34]_0 [28]),
        .R(1'b0));
  FDRE \m_payload_i_reg[29] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[29]),
        .Q(\m_payload_i_reg[34]_0 [29]),
        .R(1'b0));
  FDRE \m_payload_i_reg[2] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[2]),
        .Q(\m_payload_i_reg[34]_0 [2]),
        .R(1'b0));
  FDRE \m_payload_i_reg[30] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[30]),
        .Q(\m_payload_i_reg[34]_0 [30]),
        .R(1'b0));
  FDRE \m_payload_i_reg[31] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[31]),
        .Q(\m_payload_i_reg[34]_0 [31]),
        .R(1'b0));
  FDRE \m_payload_i_reg[32] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[32]),
        .Q(\m_payload_i_reg[34]_0 [32]),
        .R(1'b0));
  FDRE \m_payload_i_reg[33] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[33]),
        .Q(\m_payload_i_reg[34]_0 [33]),
        .R(1'b0));
  FDRE \m_payload_i_reg[34] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[34]),
        .Q(\m_payload_i_reg[34]_0 [34]),
        .R(1'b0));
  FDRE \m_payload_i_reg[3] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[3]),
        .Q(\m_payload_i_reg[34]_0 [3]),
        .R(1'b0));
  FDRE \m_payload_i_reg[4] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[4]),
        .Q(\m_payload_i_reg[34]_0 [4]),
        .R(1'b0));
  FDRE \m_payload_i_reg[5] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[5]),
        .Q(\m_payload_i_reg[34]_0 [5]),
        .R(1'b0));
  FDRE \m_payload_i_reg[6] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[6]),
        .Q(\m_payload_i_reg[34]_0 [6]),
        .R(1'b0));
  FDRE \m_payload_i_reg[7] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[7]),
        .Q(\m_payload_i_reg[34]_0 [7]),
        .R(1'b0));
  FDRE \m_payload_i_reg[8] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[8]),
        .Q(\m_payload_i_reg[34]_0 [8]),
        .R(1'b0));
  FDRE \m_payload_i_reg[9] 
       (.C(aclk),
        .CE(E),
        .D(skid_buffer[9]),
        .Q(\m_payload_i_reg[34]_0 [9]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \m_ready_d[1]_i_3 
       (.I0(\m_payload_i_reg[34]_0 [0]),
        .I1(sr_rvalid),
        .I2(s_axi_rready),
        .I3(m_valid_i),
        .I4(aa_grant_rnw),
        .I5(m_ready_d),
        .O(m_ready_d0));
  FDRE #(
    .INIT(1'b0)) 
    m_valid_i_reg
       (.C(aclk),
        .CE(1'b1),
        .D(m_valid_i_reg_0),
        .Q(sr_rvalid),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    \s_axi_rvalid[0]_INST_0 
       (.I0(sr_rvalid),
        .I1(p_0_in1_in),
        .O(s_axi_rvalid));
  FDRE #(
    .INIT(1'b0)) 
    s_ready_i_reg
       (.C(aclk),
        .CE(1'b1),
        .D(s_ready_i_reg_0),
        .Q(aa_rready),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0CAF0CA0)) 
    \skid_buffer[10]_i_1 
       (.I0(m_axi_rdata[39]),
        .I1(m_axi_rdata[71]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(m_axi_rdata[7]),
        .O(\skid_buffer[10]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0FCA00CA)) 
    \skid_buffer[11]_i_1 
       (.I0(m_axi_rdata[8]),
        .I1(m_axi_rdata[72]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(m_axi_rdata[40]),
        .O(\skid_buffer[11]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0FCA00CA)) 
    \skid_buffer[16]_i_1 
       (.I0(m_axi_rdata[13]),
        .I1(m_axi_rdata[77]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(m_axi_rdata[45]),
        .O(\skid_buffer[16]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0CAF0CA0)) 
    \skid_buffer[19]_i_1 
       (.I0(m_axi_rdata[48]),
        .I1(m_axi_rdata[80]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(m_axi_rdata[16]),
        .O(\skid_buffer[19]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0FCA00CA)) 
    \skid_buffer[20]_i_1 
       (.I0(m_axi_rdata[17]),
        .I1(m_axi_rdata[81]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(m_axi_rdata[49]),
        .O(\skid_buffer[20]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0FCA00CA)) 
    \skid_buffer[21]_i_1 
       (.I0(m_axi_rdata[18]),
        .I1(m_axi_rdata[82]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(m_axi_rdata[50]),
        .O(\skid_buffer[21]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0FCA00CA)) 
    \skid_buffer[22]_i_1 
       (.I0(m_axi_rdata[19]),
        .I1(m_axi_rdata[83]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(m_axi_rdata[51]),
        .O(\skid_buffer[22]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0FCA00CA)) 
    \skid_buffer[23]_i_1 
       (.I0(m_axi_rdata[20]),
        .I1(m_axi_rdata[84]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(m_axi_rdata[52]),
        .O(\skid_buffer[23]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0FCA00CA)) 
    \skid_buffer[24]_i_1 
       (.I0(m_axi_rdata[21]),
        .I1(m_axi_rdata[53]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(m_axi_rdata[85]),
        .O(\skid_buffer[24]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0FCA00CA)) 
    \skid_buffer[27]_i_1 
       (.I0(m_axi_rdata[24]),
        .I1(m_axi_rdata[88]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(m_axi_rdata[56]),
        .O(\skid_buffer[27]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0FCA00CA)) 
    \skid_buffer[32]_i_1 
       (.I0(m_axi_rdata[29]),
        .I1(m_axi_rdata[93]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(m_axi_rdata[61]),
        .O(\skid_buffer[32]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0FCA00CA)) 
    \skid_buffer[3]_i_1 
       (.I0(m_axi_rdata[0]),
        .I1(m_axi_rdata[32]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(m_axi_rdata[64]),
        .O(\skid_buffer[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0FCA00CA)) 
    \skid_buffer[4]_i_1 
       (.I0(m_axi_rdata[1]),
        .I1(m_axi_rdata[65]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(m_axi_rdata[33]),
        .O(\skid_buffer[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0ACF0AC0)) 
    \skid_buffer[8]_i_1 
       (.I0(m_axi_rdata[69]),
        .I1(m_axi_rdata[37]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(m_axi_rdata[5]),
        .O(\skid_buffer[8]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0FCA00CA)) 
    \skid_buffer[9]_i_1 
       (.I0(m_axi_rdata[6]),
        .I1(m_axi_rdata[70]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(m_axi_rdata[38]),
        .O(\skid_buffer[9]_i_1_n_0 ));
  FDRE \skid_buffer_reg[0] 
       (.C(aclk),
        .CE(aa_rready),
        .D(\skid_buffer_reg[0]_0 ),
        .Q(\skid_buffer_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[10] 
       (.C(aclk),
        .CE(aa_rready),
        .D(\skid_buffer[10]_i_1_n_0 ),
        .Q(\skid_buffer_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[11] 
       (.C(aclk),
        .CE(aa_rready),
        .D(\skid_buffer[11]_i_1_n_0 ),
        .Q(\skid_buffer_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[12] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[12]),
        .Q(\skid_buffer_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[13] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[13]),
        .Q(\skid_buffer_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[14] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[14]),
        .Q(\skid_buffer_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[15] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[15]),
        .Q(\skid_buffer_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[16] 
       (.C(aclk),
        .CE(aa_rready),
        .D(\skid_buffer[16]_i_1_n_0 ),
        .Q(\skid_buffer_reg_n_0_[16] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[17] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[17]),
        .Q(\skid_buffer_reg_n_0_[17] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[18] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[18]),
        .Q(\skid_buffer_reg_n_0_[18] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[19] 
       (.C(aclk),
        .CE(aa_rready),
        .D(\skid_buffer[19]_i_1_n_0 ),
        .Q(\skid_buffer_reg_n_0_[19] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[1] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[1]),
        .Q(\skid_buffer_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[20] 
       (.C(aclk),
        .CE(aa_rready),
        .D(\skid_buffer[20]_i_1_n_0 ),
        .Q(\skid_buffer_reg_n_0_[20] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[21] 
       (.C(aclk),
        .CE(aa_rready),
        .D(\skid_buffer[21]_i_1_n_0 ),
        .Q(\skid_buffer_reg_n_0_[21] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[22] 
       (.C(aclk),
        .CE(aa_rready),
        .D(\skid_buffer[22]_i_1_n_0 ),
        .Q(\skid_buffer_reg_n_0_[22] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[23] 
       (.C(aclk),
        .CE(aa_rready),
        .D(\skid_buffer[23]_i_1_n_0 ),
        .Q(\skid_buffer_reg_n_0_[23] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[24] 
       (.C(aclk),
        .CE(aa_rready),
        .D(\skid_buffer[24]_i_1_n_0 ),
        .Q(\skid_buffer_reg_n_0_[24] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[25] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[25]),
        .Q(\skid_buffer_reg_n_0_[25] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[26] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[26]),
        .Q(\skid_buffer_reg_n_0_[26] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[27] 
       (.C(aclk),
        .CE(aa_rready),
        .D(\skid_buffer[27]_i_1_n_0 ),
        .Q(\skid_buffer_reg_n_0_[27] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[28] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[28]),
        .Q(\skid_buffer_reg_n_0_[28] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[29] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[29]),
        .Q(\skid_buffer_reg_n_0_[29] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[2] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[2]),
        .Q(\skid_buffer_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[30] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[30]),
        .Q(\skid_buffer_reg_n_0_[30] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[31] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[31]),
        .Q(\skid_buffer_reg_n_0_[31] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[32] 
       (.C(aclk),
        .CE(aa_rready),
        .D(\skid_buffer[32]_i_1_n_0 ),
        .Q(\skid_buffer_reg_n_0_[32] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[33] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[33]),
        .Q(\skid_buffer_reg_n_0_[33] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[34] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[34]),
        .Q(\skid_buffer_reg_n_0_[34] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[3] 
       (.C(aclk),
        .CE(aa_rready),
        .D(\skid_buffer[3]_i_1_n_0 ),
        .Q(\skid_buffer_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[4] 
       (.C(aclk),
        .CE(aa_rready),
        .D(\skid_buffer[4]_i_1_n_0 ),
        .Q(\skid_buffer_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[5] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[5]),
        .Q(\skid_buffer_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[6] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[6]),
        .Q(\skid_buffer_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[7] 
       (.C(aclk),
        .CE(1'b1),
        .D(skid_buffer[7]),
        .Q(\skid_buffer_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[8] 
       (.C(aclk),
        .CE(aa_rready),
        .D(\skid_buffer[8]_i_1_n_0 ),
        .Q(\skid_buffer_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \skid_buffer_reg[9] 
       (.C(aclk),
        .CE(aa_rready),
        .D(\skid_buffer[9]_i_1_n_0 ),
        .Q(\skid_buffer_reg_n_0_[9] ),
        .R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
