-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
-- Date        : Fri May 14 16:50:17 2021
-- Host        : zz-Latitude-7490 running 64-bit Ubuntu 20.04.2 LTS
-- Command     : write_vhdl -force -mode funcsim
--               /home/zz/phpix/phpix-vivado-peta/hw_linux/clean_hw/clean_hw.gen/sources_1/bd/blok/ip/blok_xbar_0/blok_xbar_0_sim_netlist.vhdl
-- Design      : blok_xbar_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blok_xbar_0_axi_crossbar_v2_1_23_addr_arbiter_sasd is
  port (
    p_0_in1_in : out STD_LOGIC;
    m_valid_i : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    aa_grant_rnw : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_no_arbiter.m_amesg_i_reg[34]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
    \m_ready_d_reg[1]\ : out STD_LOGIC;
    m_ready_d0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_no_arbiter.m_amesg_i_reg[27]_0\ : out STD_LOGIC;
    \gen_axi.s_axi_rid_i\ : out STD_LOGIC;
    m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \aresetn_d_reg[1]\ : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \aresetn_d_reg[0]\ : out STD_LOGIC;
    m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \m_ready_d_reg[2]\ : out STD_LOGIC;
    s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_wlast_0_sp_1 : out STD_LOGIC;
    \s_axi_wlast[0]_0\ : out STD_LOGIC;
    \gen_no_arbiter.grant_rnw_reg_0\ : out STD_LOGIC;
    s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \m_ready_d_reg[0]\ : out STD_LOGIC;
    s_axi_bready_0_sp_1 : out STD_LOGIC;
    s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_no_arbiter.m_amesg_i_reg[47]_0\ : out STD_LOGIC;
    aclk : in STD_LOGIC;
    m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_ready_i_reg : in STD_LOGIC;
    aa_rready : in STD_LOGIC;
    aresetn_d : in STD_LOGIC;
    \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\ : in STD_LOGIC;
    s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_axi.s_axi_awready_i_reg\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    mi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
    mi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_no_arbiter.m_valid_i_reg_0\ : in STD_LOGIC;
    m_ready_d0_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_valid_i_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    sr_rvalid : in STD_LOGIC;
    m_ready_d_1 : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1\ : in STD_LOGIC;
    s_axi_wready_0_sp_1 : in STD_LOGIC;
    s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_bvalid_0_sp_1 : in STD_LOGIC;
    s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_axi.s_axi_awready_i_reg_0\ : in STD_LOGIC;
    s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
    s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of blok_xbar_0_axi_crossbar_v2_1_23_addr_arbiter_sasd : entity is "axi_crossbar_v2_1_23_addr_arbiter_sasd";
end blok_xbar_0_axi_crossbar_v2_1_23_addr_arbiter_sasd;

architecture STRUCTURE of blok_xbar_0_axi_crossbar_v2_1_23_addr_arbiter_sasd is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 68 downto 0 );
  signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^aa_grant_rnw\ : STD_LOGIC;
  signal any_error : STD_LOGIC;
  signal \gen_axi.s_axi_rlast_i_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_arbiter.grant_rnw_i_1_n_0\ : STD_LOGIC;
  signal \^gen_no_arbiter.m_amesg_i_reg[34]_0\ : STD_LOGIC;
  signal \gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0\ : STD_LOGIC;
  signal \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0\ : STD_LOGIC;
  signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
  signal \gen_no_arbiter.s_ready_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \m_atarget_hot[0]_i_2_n_0\ : STD_LOGIC;
  signal \m_atarget_hot[1]_i_3_n_0\ : STD_LOGIC;
  signal \m_atarget_hot[3]_i_3_n_0\ : STD_LOGIC;
  signal \m_atarget_hot[3]_i_4_n_0\ : STD_LOGIC;
  signal \m_atarget_hot[3]_i_5_n_0\ : STD_LOGIC;
  signal \^m_ready_d0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^m_valid_i\ : STD_LOGIC;
  signal m_valid_i_i_2_n_0 : STD_LOGIC;
  signal \^p_0_in1_in\ : STD_LOGIC;
  signal s_amesg : STD_LOGIC_VECTOR ( 69 downto 0 );
  signal \s_arvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal \s_arvalid_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal s_awvalid_reg : STD_LOGIC;
  signal \s_awvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal s_axi_bready_0_sn_1 : STD_LOGIC;
  signal s_axi_bvalid_0_sn_1 : STD_LOGIC;
  signal s_axi_wlast_0_sn_1 : STD_LOGIC;
  signal s_axi_wready_0_sn_1 : STD_LOGIC;
  signal s_ready_i : STD_LOGIC;
  signal target_mi_enc : STD_LOGIC_VECTOR ( 1 to 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gen_axi.read_cnt[7]_i_4\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \gen_axi.s_axi_awready_i_i_2\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \gen_axi.s_axi_wready_i_i_2\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \gen_no_arbiter.m_grant_hot_i[0]_inv_i_5\ : label is "soft_lutpair2";
  attribute inverted : string;
  attribute inverted of \gen_no_arbiter.m_grant_hot_i_reg[0]_inv\ : label is "yes";
  attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \m_atarget_enc[1]_i_2\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \m_atarget_hot[0]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \m_atarget_hot[1]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \m_atarget_hot[2]_i_1\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \m_atarget_hot[3]_i_1\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \m_atarget_hot[3]_i_5\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \m_axi_bready[0]_INST_0\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \m_ready_d[2]_i_2\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \m_ready_d[2]_i_3\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of m_valid_i_i_1 : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \s_arvalid_reg[0]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair11";
begin
  E(0) <= \^e\(0);
  Q(68 downto 0) <= \^q\(68 downto 0);
  SR(0) <= \^sr\(0);
  aa_grant_rnw <= \^aa_grant_rnw\;
  \gen_no_arbiter.m_amesg_i_reg[34]_0\ <= \^gen_no_arbiter.m_amesg_i_reg[34]_0\;
  m_ready_d0(0) <= \^m_ready_d0\(0);
  m_valid_i <= \^m_valid_i\;
  p_0_in1_in <= \^p_0_in1_in\;
  s_axi_bready_0_sp_1 <= s_axi_bready_0_sn_1;
  s_axi_bvalid_0_sn_1 <= s_axi_bvalid_0_sp_1;
  s_axi_wlast_0_sp_1 <= s_axi_wlast_0_sn_1;
  s_axi_wready_0_sn_1 <= s_axi_wready_0_sp_1;
\gen_axi.read_cnt[7]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => m_ready_d(1),
      I1 => \^aa_grant_rnw\,
      I2 => \^m_valid_i\,
      O => \m_ready_d_reg[1]\
    );
\gen_axi.s_axi_awready_i_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => m_ready_d_1(2),
      I1 => \^m_valid_i\,
      I2 => \^aa_grant_rnw\,
      O => \m_ready_d_reg[2]\
    );
\gen_axi.s_axi_awready_i_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400000000000000"
    )
        port map (
      I0 => m_ready_d_1(0),
      I1 => \^m_valid_i\,
      I2 => \^aa_grant_rnw\,
      I3 => s_axi_bready(0),
      I4 => \gen_axi.s_axi_awready_i_reg_0\,
      I5 => \gen_axi.s_axi_awready_i_reg\(3),
      O => \m_ready_d_reg[0]\
    );
\gen_axi.s_axi_rlast_i_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^q\(47),
      I1 => \^q\(44),
      I2 => \^q\(46),
      I3 => \^q\(45),
      I4 => \gen_axi.s_axi_rlast_i_i_4_n_0\,
      O => \gen_no_arbiter.m_amesg_i_reg[47]_0\
    );
\gen_axi.s_axi_rlast_i_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^q\(50),
      I1 => \^q\(51),
      I2 => \^q\(48),
      I3 => \^q\(49),
      O => \gen_axi.s_axi_rlast_i_i_4_n_0\
    );
\gen_axi.s_axi_rlast_i_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000800000"
    )
        port map (
      I0 => \gen_axi.s_axi_awready_i_reg\(3),
      I1 => \^m_valid_i\,
      I2 => \^aa_grant_rnw\,
      I3 => m_ready_d(1),
      I4 => mi_arready(0),
      I5 => mi_rvalid(0),
      O => \gen_axi.s_axi_rid_i\
    );
\gen_axi.s_axi_wready_i_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => \^aa_grant_rnw\,
      I1 => \^m_valid_i\,
      I2 => m_ready_d_1(1),
      I3 => s_axi_wvalid(0),
      O => \gen_no_arbiter.grant_rnw_reg_0\
    );
\gen_no_arbiter.grant_rnw_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF47FF00004400"
    )
        port map (
      I0 => s_awvalid_reg,
      I1 => s_axi_arvalid(0),
      I2 => s_axi_awvalid(0),
      I3 => \^p_0_in1_in\,
      I4 => \^m_valid_i\,
      I5 => \^aa_grant_rnw\,
      O => \gen_no_arbiter.grant_rnw_i_1_n_0\
    );
\gen_no_arbiter.grant_rnw_reg\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => \gen_no_arbiter.grant_rnw_i_1_n_0\,
      Q => \^aa_grant_rnw\,
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arid(0),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awid(0),
      O => s_amesg(0)
    );
\gen_no_arbiter.m_amesg_i[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arid(10),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awid(10),
      O => s_amesg(10)
    );
\gen_no_arbiter.m_amesg_i[11]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => aresetn_d,
      O => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i[11]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arid(11),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awid(11),
      O => s_amesg(11)
    );
\gen_no_arbiter.m_amesg_i[12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(0),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(0),
      O => s_amesg(12)
    );
\gen_no_arbiter.m_amesg_i[13]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(1),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(1),
      O => s_amesg(13)
    );
\gen_no_arbiter.m_amesg_i[14]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(2),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(2),
      O => s_amesg(14)
    );
\gen_no_arbiter.m_amesg_i[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(3),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(3),
      O => s_amesg(15)
    );
\gen_no_arbiter.m_amesg_i[16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(4),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(4),
      O => s_amesg(16)
    );
\gen_no_arbiter.m_amesg_i[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(5),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(5),
      O => s_amesg(17)
    );
\gen_no_arbiter.m_amesg_i[18]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(6),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(6),
      O => s_amesg(18)
    );
\gen_no_arbiter.m_amesg_i[19]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(7),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(7),
      O => s_amesg(19)
    );
\gen_no_arbiter.m_amesg_i[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arid(1),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awid(1),
      O => s_amesg(1)
    );
\gen_no_arbiter.m_amesg_i[20]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(8),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(8),
      O => s_amesg(20)
    );
\gen_no_arbiter.m_amesg_i[21]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(9),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(9),
      O => s_amesg(21)
    );
\gen_no_arbiter.m_amesg_i[22]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(10),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(10),
      O => s_amesg(22)
    );
\gen_no_arbiter.m_amesg_i[23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(11),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(11),
      O => s_amesg(23)
    );
\gen_no_arbiter.m_amesg_i[24]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(12),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(12),
      O => s_amesg(24)
    );
\gen_no_arbiter.m_amesg_i[25]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(13),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(13),
      O => s_amesg(25)
    );
\gen_no_arbiter.m_amesg_i[26]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(14),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(14),
      O => s_amesg(26)
    );
\gen_no_arbiter.m_amesg_i[27]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(15),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(15),
      O => s_amesg(27)
    );
\gen_no_arbiter.m_amesg_i[28]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(16),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(16),
      O => s_amesg(28)
    );
\gen_no_arbiter.m_amesg_i[29]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(17),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(17),
      O => s_amesg(29)
    );
\gen_no_arbiter.m_amesg_i[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arid(2),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awid(2),
      O => s_amesg(2)
    );
\gen_no_arbiter.m_amesg_i[30]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(18),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(18),
      O => s_amesg(30)
    );
\gen_no_arbiter.m_amesg_i[31]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(19),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(19),
      O => s_amesg(31)
    );
\gen_no_arbiter.m_amesg_i[32]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(20),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(20),
      O => s_amesg(32)
    );
\gen_no_arbiter.m_amesg_i[33]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(21),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(21),
      O => s_amesg(33)
    );
\gen_no_arbiter.m_amesg_i[34]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(22),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(22),
      O => s_amesg(34)
    );
\gen_no_arbiter.m_amesg_i[35]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(23),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(23),
      O => s_amesg(35)
    );
\gen_no_arbiter.m_amesg_i[36]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(24),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(24),
      O => s_amesg(36)
    );
\gen_no_arbiter.m_amesg_i[37]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(25),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(25),
      O => s_amesg(37)
    );
\gen_no_arbiter.m_amesg_i[38]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(26),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(26),
      O => s_amesg(38)
    );
\gen_no_arbiter.m_amesg_i[39]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(27),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(27),
      O => s_amesg(39)
    );
\gen_no_arbiter.m_amesg_i[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arid(3),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awid(3),
      O => s_amesg(3)
    );
\gen_no_arbiter.m_amesg_i[40]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(28),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(28),
      O => s_amesg(40)
    );
\gen_no_arbiter.m_amesg_i[41]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(29),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(29),
      O => s_amesg(41)
    );
\gen_no_arbiter.m_amesg_i[42]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(30),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(30),
      O => s_amesg(42)
    );
\gen_no_arbiter.m_amesg_i[43]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(31),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(31),
      O => s_amesg(43)
    );
\gen_no_arbiter.m_amesg_i[44]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arlen(0),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awlen(0),
      O => s_amesg(44)
    );
\gen_no_arbiter.m_amesg_i[45]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arlen(1),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awlen(1),
      O => s_amesg(45)
    );
\gen_no_arbiter.m_amesg_i[46]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arlen(2),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awlen(2),
      O => s_amesg(46)
    );
\gen_no_arbiter.m_amesg_i[47]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arlen(3),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awlen(3),
      O => s_amesg(47)
    );
\gen_no_arbiter.m_amesg_i[48]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arlen(4),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awlen(4),
      O => s_amesg(48)
    );
\gen_no_arbiter.m_amesg_i[49]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arlen(5),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awlen(5),
      O => s_amesg(49)
    );
\gen_no_arbiter.m_amesg_i[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arid(4),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awid(4),
      O => s_amesg(4)
    );
\gen_no_arbiter.m_amesg_i[50]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arlen(6),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awlen(6),
      O => s_amesg(50)
    );
\gen_no_arbiter.m_amesg_i[51]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arlen(7),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awlen(7),
      O => s_amesg(51)
    );
\gen_no_arbiter.m_amesg_i[52]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arsize(0),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awsize(0),
      O => s_amesg(52)
    );
\gen_no_arbiter.m_amesg_i[53]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arsize(1),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awsize(1),
      O => s_amesg(53)
    );
\gen_no_arbiter.m_amesg_i[54]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arsize(2),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awsize(2),
      O => s_amesg(54)
    );
\gen_no_arbiter.m_amesg_i[55]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arlock(0),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awlock(0),
      O => s_amesg(55)
    );
\gen_no_arbiter.m_amesg_i[57]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arprot(0),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awprot(0),
      O => s_amesg(57)
    );
\gen_no_arbiter.m_amesg_i[58]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arprot(1),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awprot(1),
      O => s_amesg(58)
    );
\gen_no_arbiter.m_amesg_i[59]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arprot(2),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awprot(2),
      O => s_amesg(59)
    );
\gen_no_arbiter.m_amesg_i[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arid(5),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awid(5),
      O => s_amesg(5)
    );
\gen_no_arbiter.m_amesg_i[60]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arburst(0),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awburst(0),
      O => s_amesg(60)
    );
\gen_no_arbiter.m_amesg_i[61]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arburst(1),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awburst(1),
      O => s_amesg(61)
    );
\gen_no_arbiter.m_amesg_i[62]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arcache(0),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awcache(0),
      O => s_amesg(62)
    );
\gen_no_arbiter.m_amesg_i[63]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arcache(1),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awcache(1),
      O => s_amesg(63)
    );
\gen_no_arbiter.m_amesg_i[64]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arcache(2),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awcache(2),
      O => s_amesg(64)
    );
\gen_no_arbiter.m_amesg_i[65]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arcache(3),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awcache(3),
      O => s_amesg(65)
    );
\gen_no_arbiter.m_amesg_i[66]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arqos(0),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awqos(0),
      O => s_amesg(66)
    );
\gen_no_arbiter.m_amesg_i[67]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arqos(1),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awqos(1),
      O => s_amesg(67)
    );
\gen_no_arbiter.m_amesg_i[68]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arqos(2),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awqos(2),
      O => s_amesg(68)
    );
\gen_no_arbiter.m_amesg_i[69]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arqos(3),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awqos(3),
      O => s_amesg(69)
    );
\gen_no_arbiter.m_amesg_i[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arid(6),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awid(6),
      O => s_amesg(6)
    );
\gen_no_arbiter.m_amesg_i[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arid(7),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awid(7),
      O => s_amesg(7)
    );
\gen_no_arbiter.m_amesg_i[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arid(8),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awid(8),
      O => s_amesg(8)
    );
\gen_no_arbiter.m_amesg_i[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_arid(9),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awid(9),
      O => s_amesg(9)
    );
\gen_no_arbiter.m_amesg_i_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(0),
      Q => \^q\(0),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(10),
      Q => \^q\(10),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(11),
      Q => \^q\(11),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(12),
      Q => \^q\(12),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(13),
      Q => \^q\(13),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(14),
      Q => \^q\(14),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(15),
      Q => \^q\(15),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(16),
      Q => \^q\(16),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(17),
      Q => \^q\(17),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(18),
      Q => \^q\(18),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(19),
      Q => \^q\(19),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(1),
      Q => \^q\(1),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(20),
      Q => \^q\(20),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(21),
      Q => \^q\(21),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(22),
      Q => \^q\(22),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(23),
      Q => \^q\(23),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(24),
      Q => \^q\(24),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(25),
      Q => \^q\(25),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(26),
      Q => \^q\(26),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(27),
      Q => \^q\(27),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(28),
      Q => \^q\(28),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(29),
      Q => \^q\(29),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(2),
      Q => \^q\(2),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(30),
      Q => \^q\(30),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(31),
      Q => \^q\(31),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(32),
      Q => \^q\(32),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(33),
      Q => \^q\(33),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(34),
      Q => \^q\(34),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(35),
      Q => \^q\(35),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(36),
      Q => \^q\(36),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(37),
      Q => \^q\(37),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(38),
      Q => \^q\(38),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(39),
      Q => \^q\(39),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(3),
      Q => \^q\(3),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(40),
      Q => \^q\(40),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(41),
      Q => \^q\(41),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(42),
      Q => \^q\(42),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(43),
      Q => \^q\(43),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(44),
      Q => \^q\(44),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(45),
      Q => \^q\(45),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(46),
      Q => \^q\(46),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(47),
      Q => \^q\(47),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(48),
      Q => \^q\(48),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(49),
      Q => \^q\(49),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(4),
      Q => \^q\(4),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(50),
      Q => \^q\(50),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(51),
      Q => \^q\(51),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(52),
      Q => \^q\(52),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(53),
      Q => \^q\(53),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(54),
      Q => \^q\(54),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(55),
      Q => \^q\(55),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(57),
      Q => \^q\(56),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(58),
      Q => \^q\(57),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(59),
      Q => \^q\(58),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(5),
      Q => \^q\(5),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(60),
      Q => \^q\(59),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(61),
      Q => \^q\(60),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(62),
      Q => \^q\(61),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(63),
      Q => \^q\(62),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(64),
      Q => \^q\(63),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(65),
      Q => \^q\(64),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(66),
      Q => \^q\(65),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(67),
      Q => \^q\(66),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(68),
      Q => \^q\(67),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(69),
      Q => \^q\(68),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(6),
      Q => \^q\(6),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(7),
      Q => \^q\(7),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(8),
      Q => \^q\(8),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^p_0_in1_in\,
      D => s_amesg(9),
      Q => \^q\(9),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_grant_hot_i[0]_inv_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0040F040"
    )
        port map (
      I0 => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\,
      I1 => \^m_ready_d0\(0),
      I2 => \^m_valid_i\,
      I3 => \^aa_grant_rnw\,
      I4 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3_n_0\,
      I5 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0\,
      O => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0\
    );
\gen_no_arbiter.m_grant_hot_i[0]_inv_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0F07FFFF"
    )
        port map (
      I0 => \^m_valid_i\,
      I1 => \^aa_grant_rnw\,
      I2 => m_ready_d(1),
      I3 => \gen_no_arbiter.m_valid_i_reg_0\,
      I4 => m_ready_d0_0(0),
      O => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3_n_0\
    );
\gen_no_arbiter.m_grant_hot_i[0]_inv_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D5D5D5F5"
    )
        port map (
      I0 => aresetn_d,
      I1 => \^m_valid_i\,
      I2 => \^p_0_in1_in\,
      I3 => s_axi_awvalid(0),
      I4 => s_axi_arvalid(0),
      O => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0\
    );
\gen_no_arbiter.m_grant_hot_i[0]_inv_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000800"
    )
        port map (
      I0 => s_axi_wlast(0),
      I1 => s_axi_wvalid(0),
      I2 => m_ready_d_1(1),
      I3 => \^m_valid_i\,
      I4 => \^aa_grant_rnw\,
      O => \s_axi_wlast[0]_0\
    );
\gen_no_arbiter.m_grant_hot_i_reg[0]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0\,
      Q => \^p_0_in1_in\,
      R => '0'
    );
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF55CF550055CF55"
    )
        port map (
      I0 => \^p_0_in1_in\,
      I1 => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\,
      I2 => \^m_ready_d0\(0),
      I3 => \^m_valid_i\,
      I4 => \^aa_grant_rnw\,
      I5 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3_n_0\,
      O => \gen_no_arbiter.m_valid_i_i_1_n_0\
    );
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
      Q => \^m_valid_i\,
      R => \^sr\(0)
    );
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^m_valid_i\,
      I1 => \^p_0_in1_in\,
      I2 => aresetn_d,
      O => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\
    );
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\,
      Q => s_ready_i,
      R => '0'
    );
\m_atarget_enc[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^q\(27),
      I1 => \^q\(28),
      I2 => \^q\(43),
      I3 => \^q\(30),
      I4 => \m_atarget_hot[3]_i_4_n_0\,
      O => \gen_no_arbiter.m_amesg_i_reg[27]_0\
    );
\m_atarget_hot[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \m_atarget_hot[1]_i_3_n_0\,
      I1 => \^p_0_in1_in\,
      I2 => \m_atarget_hot[0]_i_2_n_0\,
      O => D(0)
    );
\m_atarget_hot[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \^q\(37),
      I1 => \^q\(32),
      I2 => \^q\(33),
      I3 => \^q\(36),
      I4 => \^q\(35),
      I5 => \^q\(34),
      O => \m_atarget_hot[0]_i_2_n_0\
    );
\m_atarget_hot[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^gen_no_arbiter.m_amesg_i_reg[34]_0\,
      I1 => \m_atarget_hot[1]_i_3_n_0\,
      I2 => \^q\(37),
      I3 => \^p_0_in1_in\,
      O => D(1)
    );
\m_atarget_hot[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^q\(34),
      I1 => \^q\(35),
      I2 => \^q\(36),
      I3 => \^q\(33),
      I4 => \^q\(32),
      O => \^gen_no_arbiter.m_amesg_i_reg[34]_0\
    );
\m_atarget_hot[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \^q\(38),
      I1 => \m_atarget_hot[3]_i_4_n_0\,
      I2 => \^q\(30),
      I3 => \^q\(43),
      I4 => \^q\(28),
      I5 => \^q\(27),
      O => \m_atarget_hot[1]_i_3_n_0\
    );
\m_atarget_hot[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => target_mi_enc(1),
      I1 => \^p_0_in1_in\,
      O => D(2)
    );
\m_atarget_hot[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \m_atarget_hot[3]_i_4_n_0\,
      I1 => \m_atarget_hot[3]_i_5_n_0\,
      I2 => \^q\(26),
      I3 => \^q\(38),
      I4 => \^q\(25),
      I5 => \m_atarget_hot[0]_i_2_n_0\,
      O => target_mi_enc(1)
    );
\m_atarget_hot[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => any_error,
      I1 => \^p_0_in1_in\,
      O => D(3)
    );
\m_atarget_hot[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFE0"
    )
        port map (
      I0 => \^q\(37),
      I1 => \m_atarget_hot[3]_i_3_n_0\,
      I2 => \^q\(38),
      I3 => \m_atarget_hot[3]_i_4_n_0\,
      I4 => \m_atarget_hot[3]_i_5_n_0\,
      I5 => \^gen_no_arbiter.m_amesg_i_reg[34]_0\,
      O => any_error
    );
\m_atarget_hot[3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \^q\(26),
      I1 => \^q\(38),
      I2 => \^q\(25),
      O => \m_atarget_hot[3]_i_3_n_0\
    );
\m_atarget_hot[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => \^q\(31),
      I1 => \^q\(40),
      I2 => \^q\(41),
      I3 => \^q\(42),
      I4 => \^q\(39),
      I5 => \^q\(29),
      O => \m_atarget_hot[3]_i_4_n_0\
    );
\m_atarget_hot[3]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^q\(30),
      I1 => \^q\(43),
      I2 => \^q\(28),
      I3 => \^q\(27),
      O => \m_atarget_hot[3]_i_5_n_0\
    );
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \gen_axi.s_axi_awready_i_reg\(0),
      I1 => \^m_valid_i\,
      I2 => \^aa_grant_rnw\,
      I3 => m_ready_d(1),
      O => m_axi_arvalid(0)
    );
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \gen_axi.s_axi_awready_i_reg\(1),
      I1 => \^m_valid_i\,
      I2 => \^aa_grant_rnw\,
      I3 => m_ready_d(1),
      O => m_axi_arvalid(1)
    );
\m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \gen_axi.s_axi_awready_i_reg\(2),
      I1 => \^m_valid_i\,
      I2 => \^aa_grant_rnw\,
      I3 => m_ready_d(1),
      O => m_axi_arvalid(2)
    );
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \gen_axi.s_axi_awready_i_reg\(0),
      I1 => \^aa_grant_rnw\,
      I2 => \^m_valid_i\,
      I3 => m_ready_d_1(2),
      O => m_axi_awvalid(0)
    );
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \gen_axi.s_axi_awready_i_reg\(1),
      I1 => \^aa_grant_rnw\,
      I2 => \^m_valid_i\,
      I3 => m_ready_d_1(2),
      O => m_axi_awvalid(1)
    );
\m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \gen_axi.s_axi_awready_i_reg\(2),
      I1 => \^aa_grant_rnw\,
      I2 => \^m_valid_i\,
      I3 => m_ready_d_1(2),
      O => m_axi_awvalid(2)
    );
\m_axi_bready[0]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00200000"
    )
        port map (
      I0 => \gen_axi.s_axi_awready_i_reg\(0),
      I1 => m_ready_d_1(0),
      I2 => \^m_valid_i\,
      I3 => \^aa_grant_rnw\,
      I4 => s_axi_bready(0),
      O => m_axi_bready(0)
    );
\m_axi_bready[1]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00200000"
    )
        port map (
      I0 => \gen_axi.s_axi_awready_i_reg\(1),
      I1 => m_ready_d_1(0),
      I2 => \^m_valid_i\,
      I3 => \^aa_grant_rnw\,
      I4 => s_axi_bready(0),
      O => m_axi_bready(1)
    );
\m_axi_bready[2]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00200000"
    )
        port map (
      I0 => \gen_axi.s_axi_awready_i_reg\(2),
      I1 => m_ready_d_1(0),
      I2 => \^m_valid_i\,
      I3 => \^aa_grant_rnw\,
      I4 => s_axi_bready(0),
      O => m_axi_bready(2)
    );
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000800"
    )
        port map (
      I0 => \gen_axi.s_axi_awready_i_reg\(0),
      I1 => s_axi_wvalid(0),
      I2 => m_ready_d_1(1),
      I3 => \^m_valid_i\,
      I4 => \^aa_grant_rnw\,
      O => m_axi_wvalid(0)
    );
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000800"
    )
        port map (
      I0 => \gen_axi.s_axi_awready_i_reg\(1),
      I1 => s_axi_wvalid(0),
      I2 => m_ready_d_1(1),
      I3 => \^m_valid_i\,
      I4 => \^aa_grant_rnw\,
      O => m_axi_wvalid(1)
    );
\m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000800"
    )
        port map (
      I0 => \gen_axi.s_axi_awready_i_reg\(2),
      I1 => s_axi_wvalid(0),
      I2 => m_ready_d_1(1),
      I3 => \^m_valid_i\,
      I4 => \^aa_grant_rnw\,
      O => m_axi_wvalid(2)
    );
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4000FFFF"
    )
        port map (
      I0 => m_ready_d(0),
      I1 => \^aa_grant_rnw\,
      I2 => \^m_valid_i\,
      I3 => s_axi_rready(0),
      I4 => sr_rvalid,
      O => \^e\(0)
    );
\m_ready_d[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BAAA"
    )
        port map (
      I0 => m_ready_d_1(2),
      I1 => \^aa_grant_rnw\,
      I2 => \^m_valid_i\,
      I3 => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1\,
      O => \^m_ready_d0\(0)
    );
\m_ready_d[2]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => s_axi_bready(0),
      I1 => \^aa_grant_rnw\,
      I2 => \^m_valid_i\,
      I3 => m_ready_d_1(0),
      O => s_axi_bready_0_sn_1
    );
\m_ready_d[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F070F0F0F0F0F"
    )
        port map (
      I0 => s_axi_wlast(0),
      I1 => s_axi_wvalid(0),
      I2 => m_ready_d_1(1),
      I3 => \^m_valid_i\,
      I4 => \^aa_grant_rnw\,
      I5 => s_axi_wready_0_sn_1,
      O => s_axi_wlast_0_sn_1
    );
m_valid_i_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => m_valid_i_reg(1),
      I1 => m_valid_i_i_2_n_0,
      I2 => \^e\(0),
      O => \aresetn_d_reg[1]\
    );
m_valid_i_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4000FFFF"
    )
        port map (
      I0 => m_ready_d(0),
      I1 => \^aa_grant_rnw\,
      I2 => \^m_valid_i\,
      I3 => s_ready_i_reg,
      I4 => aa_rready,
      O => m_valid_i_i_2_n_0
    );
\s_arvalid_reg[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => s_awvalid_reg,
      I1 => s_axi_arvalid(0),
      I2 => aresetn_d,
      I3 => s_ready_i,
      O => \s_arvalid_reg[0]_i_1_n_0\
    );
\s_arvalid_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \s_arvalid_reg[0]_i_1_n_0\,
      Q => \s_arvalid_reg_reg_n_0_[0]\,
      R => '0'
    );
\s_awvalid_reg[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000D00000"
    )
        port map (
      I0 => s_axi_arvalid(0),
      I1 => s_awvalid_reg,
      I2 => s_axi_awvalid(0),
      I3 => \s_arvalid_reg_reg_n_0_[0]\,
      I4 => aresetn_d,
      I5 => s_ready_i,
      O => \s_awvalid_reg[0]_i_1_n_0\
    );
\s_awvalid_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \s_awvalid_reg[0]_i_1_n_0\,
      Q => s_awvalid_reg,
      R => '0'
    );
\s_axi_arready[0]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^aa_grant_rnw\,
      I1 => s_ready_i,
      O => s_axi_arready(0)
    );
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => s_ready_i,
      I1 => \^aa_grant_rnw\,
      O => s_axi_awready(0)
    );
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => m_ready_d_1(0),
      I1 => \^m_valid_i\,
      I2 => \^aa_grant_rnw\,
      I3 => \^p_0_in1_in\,
      I4 => s_axi_bvalid_0_sn_1,
      O => s_axi_bvalid(0)
    );
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => s_axi_wready_0_sn_1,
      I1 => \^p_0_in1_in\,
      I2 => m_ready_d_1(1),
      I3 => \^m_valid_i\,
      I4 => \^aa_grant_rnw\,
      O => s_axi_wready(0)
    );
s_ready_i_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => m_valid_i_reg(0),
      I1 => \^e\(0),
      I2 => m_valid_i_i_2_n_0,
      O => \aresetn_d_reg[0]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blok_xbar_0_axi_crossbar_v2_1_23_decerr_slave is
  port (
    mi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    mi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
    \m_ready_d_reg[1]\ : out STD_LOGIC;
    \gen_axi.s_axi_wready_i_reg_0\ : out STD_LOGIC;
    \gen_axi.s_axi_bvalid_i_reg_0\ : out STD_LOGIC;
    \gen_axi.s_axi_rlast_i_reg_0\ : out STD_LOGIC;
    m_axi_rvalid_0_sp_1 : out STD_LOGIC;
    m_axi_arready_0_sp_1 : out STD_LOGIC;
    \gen_axi.s_axi_awready_i_reg_0\ : out STD_LOGIC;
    \FSM_onehot_gen_axi.write_cs_reg[2]_0\ : out STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    aclk : in STD_LOGIC;
    aa_rready : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    aresetn_d : in STD_LOGIC;
    \gen_axi.s_axi_arready_i_reg_0\ : in STD_LOGIC;
    \gen_axi.s_axi_rid_i\ : in STD_LOGIC;
    \gen_axi.read_cnt_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \gen_axi.s_axi_awready_i_reg_1\ : in STD_LOGIC;
    \gen_axi.s_axi_wready_i_reg_1\ : in STD_LOGIC;
    s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_ready_d : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_valid_i : in STD_LOGIC;
    aa_grant_rnw : in STD_LOGIC;
    \gen_no_arbiter.m_grant_hot_i_reg[0]_inv\ : in STD_LOGIC;
    \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\ : in STD_LOGIC;
    m_axi_rlast : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \skid_buffer_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_axi.s_axi_awready_i_reg_2\ : in STD_LOGIC;
    \gen_axi.s_axi_rlast_i_reg_1\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of blok_xbar_0_axi_crossbar_v2_1_23_decerr_slave : entity is "axi_crossbar_v2_1_23_decerr_slave";
end blok_xbar_0_axi_crossbar_v2_1_23_decerr_slave;

architecture STRUCTURE of blok_xbar_0_axi_crossbar_v2_1_23_decerr_slave is
  signal \FSM_onehot_gen_axi.write_cs[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_axi.write_cs[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_axi.write_cs[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_axi.write_cs[2]_i_2_n_0\ : STD_LOGIC;
  signal \^fsm_onehot_gen_axi.write_cs_reg[2]_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_axi.write_cs_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_gen_axi.write_cs_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_axi.read_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_axi.read_cnt[7]_i_1_n_0\ : STD_LOGIC;
  signal \gen_axi.read_cnt[7]_i_3_n_0\ : STD_LOGIC;
  signal \gen_axi.read_cnt[7]_i_5_n_0\ : STD_LOGIC;
  signal \gen_axi.read_cnt_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \gen_axi.read_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \gen_axi.read_cs[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_axi.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
  signal \gen_axi.s_axi_arready_i_i_2_n_0\ : STD_LOGIC;
  signal \gen_axi.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
  signal \gen_axi.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC;
  signal \^gen_axi.s_axi_bvalid_i_reg_0\ : STD_LOGIC;
  signal \gen_axi.s_axi_rlast_i_i_1_n_0\ : STD_LOGIC;
  signal \gen_axi.s_axi_rlast_i_i_3_n_0\ : STD_LOGIC;
  signal \gen_axi.s_axi_rlast_i_i_6_n_0\ : STD_LOGIC;
  signal \gen_axi.s_axi_wready_i_i_1_n_0\ : STD_LOGIC;
  signal \gen_axi.s_axi_wready_i_i_3_n_0\ : STD_LOGIC;
  signal \^gen_axi.s_axi_wready_i_reg_0\ : STD_LOGIC;
  signal m_axi_arready_0_sn_1 : STD_LOGIC;
  signal m_axi_rvalid_0_sn_1 : STD_LOGIC;
  signal \^mi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mi_awready : STD_LOGIC_VECTOR ( 3 to 3 );
  signal mi_bvalid : STD_LOGIC_VECTOR ( 3 to 3 );
  signal mi_rmesg : STD_LOGIC_VECTOR ( 108 to 108 );
  signal \^mi_rvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal mi_wready : STD_LOGIC_VECTOR ( 3 to 3 );
  signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_gen_axi.write_cs[1]_i_1\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \FSM_onehot_gen_axi.write_cs[2]_i_1\ : label is "soft_lutpair16";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_gen_axi.write_cs_reg[0]\ : label is "P_WRITE_IDLE:001,P_WRITE_DATA:010,P_WRITE_RESP:100,";
  attribute FSM_ENCODED_STATES of \FSM_onehot_gen_axi.write_cs_reg[1]\ : label is "P_WRITE_IDLE:001,P_WRITE_DATA:010,P_WRITE_RESP:100,";
  attribute FSM_ENCODED_STATES of \FSM_onehot_gen_axi.write_cs_reg[2]\ : label is "P_WRITE_IDLE:001,P_WRITE_DATA:010,P_WRITE_RESP:100,";
  attribute SOFT_HLUTNM of \gen_axi.read_cnt[0]_i_1\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \gen_axi.read_cnt[1]_i_1\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \gen_axi.read_cnt[2]_i_1\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_2\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \gen_axi.read_cnt[7]_i_2\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \gen_axi.read_cnt[7]_i_3\ : label is "soft_lutpair13";
begin
  \FSM_onehot_gen_axi.write_cs_reg[2]_0\ <= \^fsm_onehot_gen_axi.write_cs_reg[2]_0\;
  \gen_axi.s_axi_bvalid_i_reg_0\ <= \^gen_axi.s_axi_bvalid_i_reg_0\;
  \gen_axi.s_axi_wready_i_reg_0\ <= \^gen_axi.s_axi_wready_i_reg_0\;
  m_axi_arready_0_sp_1 <= m_axi_arready_0_sn_1;
  m_axi_rvalid_0_sp_1 <= m_axi_rvalid_0_sn_1;
  mi_arready(0) <= \^mi_arready\(0);
  mi_rvalid(0) <= \^mi_rvalid\(0);
\FSM_onehot_gen_axi.write_cs[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^fsm_onehot_gen_axi.write_cs_reg[2]_0\,
      I1 => \FSM_onehot_gen_axi.write_cs[2]_i_2_n_0\,
      I2 => \FSM_onehot_gen_axi.write_cs_reg_n_0_[0]\,
      O => \FSM_onehot_gen_axi.write_cs[0]_i_1_n_0\
    );
\FSM_onehot_gen_axi.write_cs[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \FSM_onehot_gen_axi.write_cs_reg_n_0_[0]\,
      I1 => \FSM_onehot_gen_axi.write_cs[2]_i_2_n_0\,
      I2 => \FSM_onehot_gen_axi.write_cs_reg_n_0_[1]\,
      O => \FSM_onehot_gen_axi.write_cs[1]_i_1_n_0\
    );
\FSM_onehot_gen_axi.write_cs[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \FSM_onehot_gen_axi.write_cs_reg_n_0_[1]\,
      I1 => \FSM_onehot_gen_axi.write_cs[2]_i_2_n_0\,
      I2 => \^fsm_onehot_gen_axi.write_cs_reg[2]_0\,
      O => \FSM_onehot_gen_axi.write_cs[2]_i_1_n_0\
    );
\FSM_onehot_gen_axi.write_cs[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEEEEEEEEEEEEEE"
    )
        port map (
      I0 => \gen_axi.s_axi_wready_i_i_3_n_0\,
      I1 => \gen_axi.s_axi_awready_i_reg_1\,
      I2 => \gen_axi.s_axi_wready_i_reg_1\,
      I3 => s_axi_wlast(0),
      I4 => \FSM_onehot_gen_axi.write_cs_reg_n_0_[1]\,
      I5 => Q(0),
      O => \FSM_onehot_gen_axi.write_cs[2]_i_2_n_0\
    );
\FSM_onehot_gen_axi.write_cs_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \FSM_onehot_gen_axi.write_cs[0]_i_1_n_0\,
      Q => \FSM_onehot_gen_axi.write_cs_reg_n_0_[0]\,
      S => SR(0)
    );
\FSM_onehot_gen_axi.write_cs_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \FSM_onehot_gen_axi.write_cs[1]_i_1_n_0\,
      Q => \FSM_onehot_gen_axi.write_cs_reg_n_0_[1]\,
      R => SR(0)
    );
\FSM_onehot_gen_axi.write_cs_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \FSM_onehot_gen_axi.write_cs[2]_i_1_n_0\,
      Q => \^fsm_onehot_gen_axi.write_cs_reg[2]_0\,
      R => SR(0)
    );
\gen_axi.read_cnt[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => \gen_axi.read_cnt_reg\(0),
      I1 => \^mi_rvalid\(0),
      I2 => \gen_axi.read_cnt_reg[7]_0\(0),
      O => p_0_in(0)
    );
\gen_axi.read_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9F90"
    )
        port map (
      I0 => \gen_axi.read_cnt_reg__0\(1),
      I1 => \gen_axi.read_cnt_reg\(0),
      I2 => \^mi_rvalid\(0),
      I3 => \gen_axi.read_cnt_reg[7]_0\(1),
      O => p_0_in(1)
    );
\gen_axi.read_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E1FFE100"
    )
        port map (
      I0 => \gen_axi.read_cnt_reg__0\(1),
      I1 => \gen_axi.read_cnt_reg\(0),
      I2 => \gen_axi.read_cnt_reg__0\(2),
      I3 => \^mi_rvalid\(0),
      I4 => \gen_axi.read_cnt_reg[7]_0\(2),
      O => p_0_in(2)
    );
\gen_axi.read_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE01FFFFFE010000"
    )
        port map (
      I0 => \gen_axi.read_cnt_reg__0\(2),
      I1 => \gen_axi.read_cnt_reg\(0),
      I2 => \gen_axi.read_cnt_reg__0\(1),
      I3 => \gen_axi.read_cnt_reg__0\(3),
      I4 => \^mi_rvalid\(0),
      I5 => \gen_axi.read_cnt_reg[7]_0\(3),
      O => p_0_in(3)
    );
\gen_axi.read_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E1FFE100"
    )
        port map (
      I0 => \gen_axi.read_cnt_reg__0\(3),
      I1 => \gen_axi.read_cnt[5]_i_2_n_0\,
      I2 => \gen_axi.read_cnt_reg__0\(4),
      I3 => \^mi_rvalid\(0),
      I4 => \gen_axi.read_cnt_reg[7]_0\(4),
      O => p_0_in(4)
    );
\gen_axi.read_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE01FFFFFE010000"
    )
        port map (
      I0 => \gen_axi.read_cnt[5]_i_2_n_0\,
      I1 => \gen_axi.read_cnt_reg__0\(3),
      I2 => \gen_axi.read_cnt_reg__0\(4),
      I3 => \gen_axi.read_cnt_reg__0\(5),
      I4 => \^mi_rvalid\(0),
      I5 => \gen_axi.read_cnt_reg[7]_0\(5),
      O => p_0_in(5)
    );
\gen_axi.read_cnt[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \gen_axi.read_cnt_reg__0\(2),
      I1 => \gen_axi.read_cnt_reg\(0),
      I2 => \gen_axi.read_cnt_reg__0\(1),
      O => \gen_axi.read_cnt[5]_i_2_n_0\
    );
\gen_axi.read_cnt[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9F90"
    )
        port map (
      I0 => \gen_axi.read_cnt[7]_i_5_n_0\,
      I1 => \gen_axi.read_cnt_reg__0\(6),
      I2 => \^mi_rvalid\(0),
      I3 => \gen_axi.read_cnt_reg[7]_0\(6),
      O => p_0_in(6)
    );
\gen_axi.read_cnt[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8F80808000000000"
    )
        port map (
      I0 => \gen_axi.read_cnt[7]_i_3_n_0\,
      I1 => aa_rready,
      I2 => \^mi_rvalid\(0),
      I3 => \^mi_arready\(0),
      I4 => \gen_axi.s_axi_arready_i_reg_0\,
      I5 => Q(0),
      O => \gen_axi.read_cnt[7]_i_1_n_0\
    );
\gen_axi.read_cnt[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A9FFA900"
    )
        port map (
      I0 => \gen_axi.read_cnt_reg__0\(7),
      I1 => \gen_axi.read_cnt[7]_i_5_n_0\,
      I2 => \gen_axi.read_cnt_reg__0\(6),
      I3 => \^mi_rvalid\(0),
      I4 => \gen_axi.read_cnt_reg[7]_0\(7),
      O => p_0_in(7)
    );
\gen_axi.read_cnt[7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \gen_axi.read_cnt[7]_i_5_n_0\,
      I1 => \gen_axi.read_cnt_reg__0\(6),
      I2 => \gen_axi.read_cnt_reg__0\(7),
      O => \gen_axi.read_cnt[7]_i_3_n_0\
    );
\gen_axi.read_cnt[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \gen_axi.read_cnt_reg__0\(5),
      I1 => \gen_axi.read_cnt_reg__0\(4),
      I2 => \gen_axi.read_cnt_reg__0\(3),
      I3 => \gen_axi.read_cnt_reg__0\(2),
      I4 => \gen_axi.read_cnt_reg\(0),
      I5 => \gen_axi.read_cnt_reg__0\(1),
      O => \gen_axi.read_cnt[7]_i_5_n_0\
    );
\gen_axi.read_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \gen_axi.read_cnt[7]_i_1_n_0\,
      D => p_0_in(0),
      Q => \gen_axi.read_cnt_reg\(0),
      R => SR(0)
    );
\gen_axi.read_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \gen_axi.read_cnt[7]_i_1_n_0\,
      D => p_0_in(1),
      Q => \gen_axi.read_cnt_reg__0\(1),
      R => SR(0)
    );
\gen_axi.read_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \gen_axi.read_cnt[7]_i_1_n_0\,
      D => p_0_in(2),
      Q => \gen_axi.read_cnt_reg__0\(2),
      R => SR(0)
    );
\gen_axi.read_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \gen_axi.read_cnt[7]_i_1_n_0\,
      D => p_0_in(3),
      Q => \gen_axi.read_cnt_reg__0\(3),
      R => SR(0)
    );
\gen_axi.read_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \gen_axi.read_cnt[7]_i_1_n_0\,
      D => p_0_in(4),
      Q => \gen_axi.read_cnt_reg__0\(4),
      R => SR(0)
    );
\gen_axi.read_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \gen_axi.read_cnt[7]_i_1_n_0\,
      D => p_0_in(5),
      Q => \gen_axi.read_cnt_reg__0\(5),
      R => SR(0)
    );
\gen_axi.read_cnt_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \gen_axi.read_cnt[7]_i_1_n_0\,
      D => p_0_in(6),
      Q => \gen_axi.read_cnt_reg__0\(6),
      R => SR(0)
    );
\gen_axi.read_cnt_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \gen_axi.read_cnt[7]_i_1_n_0\,
      D => p_0_in(7),
      Q => \gen_axi.read_cnt_reg__0\(7),
      R => SR(0)
    );
\gen_axi.read_cs[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFD0D0D0F0F0F0F0"
    )
        port map (
      I0 => aa_rready,
      I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
      I2 => \^mi_rvalid\(0),
      I3 => \^mi_arready\(0),
      I4 => \gen_axi.s_axi_arready_i_reg_0\,
      I5 => Q(0),
      O => \gen_axi.read_cs[0]_i_1_n_0\
    );
\gen_axi.read_cs_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \gen_axi.read_cs[0]_i_1_n_0\,
      Q => \^mi_rvalid\(0),
      R => SR(0)
    );
\gen_axi.s_axi_arready_i_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C088C888C888C888"
    )
        port map (
      I0 => \gen_axi.s_axi_arready_i_i_2_n_0\,
      I1 => aresetn_d,
      I2 => \^mi_rvalid\(0),
      I3 => \^mi_arready\(0),
      I4 => \gen_axi.s_axi_arready_i_reg_0\,
      I5 => Q(0),
      O => \gen_axi.s_axi_arready_i_i_1_n_0\
    );
\gen_axi.s_axi_arready_i_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"01000000FFFFFFFF"
    )
        port map (
      I0 => \gen_axi.read_cnt[7]_i_5_n_0\,
      I1 => \gen_axi.read_cnt_reg__0\(6),
      I2 => \gen_axi.read_cnt_reg__0\(7),
      I3 => Q(0),
      I4 => aa_rready,
      I5 => \^mi_rvalid\(0),
      O => \gen_axi.s_axi_arready_i_i_2_n_0\
    );
\gen_axi.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \gen_axi.s_axi_arready_i_i_1_n_0\,
      Q => \^mi_arready\(0),
      R => '0'
    );
\gen_axi.s_axi_awready_i_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFDFFFFFFFF00"
    )
        port map (
      I0 => Q(0),
      I1 => \gen_axi.s_axi_awready_i_reg_2\,
      I2 => \FSM_onehot_gen_axi.write_cs_reg_n_0_[1]\,
      I3 => \FSM_onehot_gen_axi.write_cs_reg_n_0_[0]\,
      I4 => \gen_axi.s_axi_awready_i_reg_1\,
      I5 => mi_awready(3),
      O => \gen_axi.s_axi_awready_i_i_1_n_0\
    );
\gen_axi.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \gen_axi.s_axi_awready_i_i_1_n_0\,
      Q => mi_awready(3),
      R => SR(0)
    );
\gen_axi.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF00800080"
    )
        port map (
      I0 => Q(0),
      I1 => \FSM_onehot_gen_axi.write_cs_reg_n_0_[1]\,
      I2 => s_axi_wlast(0),
      I3 => \gen_axi.s_axi_wready_i_reg_1\,
      I4 => \gen_axi.s_axi_awready_i_reg_1\,
      I5 => mi_bvalid(3),
      O => \gen_axi.s_axi_bvalid_i_i_1_n_0\
    );
\gen_axi.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \gen_axi.s_axi_bvalid_i_i_1_n_0\,
      Q => mi_bvalid(3),
      R => SR(0)
    );
\gen_axi.s_axi_rlast_i_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \gen_axi.read_cnt[7]_i_3_n_0\,
      I1 => \^mi_rvalid\(0),
      I2 => \gen_axi.s_axi_rlast_i_reg_1\,
      I3 => \gen_axi.s_axi_rlast_i_i_3_n_0\,
      I4 => mi_rmesg(108),
      O => \gen_axi.s_axi_rlast_i_i_1_n_0\
    );
\gen_axi.s_axi_rlast_i_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAABAA"
    )
        port map (
      I0 => \gen_axi.s_axi_rid_i\,
      I1 => \gen_axi.s_axi_rlast_i_i_6_n_0\,
      I2 => \gen_axi.read_cnt_reg__0\(1),
      I3 => \^mi_rvalid\(0),
      I4 => \gen_axi.read_cnt_reg__0\(5),
      I5 => \gen_axi.read_cnt_reg__0\(2),
      O => \gen_axi.s_axi_rlast_i_i_3_n_0\
    );
\gen_axi.s_axi_rlast_i_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFFFFFFFFFF"
    )
        port map (
      I0 => \gen_axi.read_cnt_reg__0\(7),
      I1 => \gen_axi.read_cnt_reg__0\(6),
      I2 => \gen_axi.read_cnt_reg__0\(4),
      I3 => \gen_axi.read_cnt_reg__0\(3),
      I4 => aa_rready,
      I5 => Q(0),
      O => \gen_axi.s_axi_rlast_i_i_6_n_0\
    );
\gen_axi.s_axi_rlast_i_reg\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => \gen_axi.s_axi_rlast_i_i_1_n_0\,
      Q => mi_rmesg(108),
      R => SR(0)
    );
\gen_axi.s_axi_wready_i_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF7FFFFF0000"
    )
        port map (
      I0 => Q(0),
      I1 => \FSM_onehot_gen_axi.write_cs_reg_n_0_[1]\,
      I2 => s_axi_wlast(0),
      I3 => \gen_axi.s_axi_wready_i_reg_1\,
      I4 => \gen_axi.s_axi_wready_i_i_3_n_0\,
      I5 => mi_wready(3),
      O => \gen_axi.s_axi_wready_i_i_1_n_0\
    );
\gen_axi.s_axi_wready_i_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000800000"
    )
        port map (
      I0 => \FSM_onehot_gen_axi.write_cs_reg_n_0_[0]\,
      I1 => Q(0),
      I2 => mi_awready(3),
      I3 => m_ready_d(2),
      I4 => m_valid_i,
      I5 => aa_grant_rnw,
      O => \gen_axi.s_axi_wready_i_i_3_n_0\
    );
\gen_axi.s_axi_wready_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \gen_axi.s_axi_wready_i_i_1_n_0\,
      Q => mi_wready(3),
      R => SR(0)
    );
\gen_no_arbiter.m_grant_hot_i[0]_inv_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"07070707FFFF07FF"
    )
        port map (
      I0 => \^gen_axi.s_axi_wready_i_reg_0\,
      I1 => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv\,
      I2 => m_ready_d(1),
      I3 => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\,
      I4 => \^gen_axi.s_axi_bvalid_i_reg_0\,
      I5 => m_ready_d(0),
      O => \m_ready_d_reg[1]\
    );
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00330F55FF330F55"
    )
        port map (
      I0 => m_axi_arready(0),
      I1 => m_axi_arready(2),
      I2 => m_axi_arready(1),
      I3 => \skid_buffer_reg[0]\(0),
      I4 => \skid_buffer_reg[0]\(1),
      I5 => \^mi_arready\(0),
      O => m_axi_arready_0_sn_1
    );
\m_ready_d[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFFCCF0AA00CCF0"
    )
        port map (
      I0 => mi_awready(3),
      I1 => m_axi_awready(2),
      I2 => m_axi_awready(0),
      I3 => \skid_buffer_reg[0]\(1),
      I4 => \skid_buffer_reg[0]\(0),
      I5 => m_axi_awready(1),
      O => \gen_axi.s_axi_awready_i_reg_0\
    );
m_valid_i_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCF0AA00CCF0AA"
    )
        port map (
      I0 => m_axi_rvalid(0),
      I1 => m_axi_rvalid(1),
      I2 => m_axi_rvalid(2),
      I3 => \skid_buffer_reg[0]\(1),
      I4 => \skid_buffer_reg[0]\(0),
      I5 => \^mi_rvalid\(0),
      O => m_axi_rvalid_0_sn_1
    );
\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55000F3355FF0F33"
    )
        port map (
      I0 => mi_bvalid(3),
      I1 => m_axi_bvalid(0),
      I2 => m_axi_bvalid(1),
      I3 => \skid_buffer_reg[0]\(0),
      I4 => \skid_buffer_reg[0]\(1),
      I5 => m_axi_bvalid(2),
      O => \^gen_axi.s_axi_bvalid_i_reg_0\
    );
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFFF0CCAA00F0CC"
    )
        port map (
      I0 => mi_wready(3),
      I1 => m_axi_wready(0),
      I2 => m_axi_wready(1),
      I3 => \skid_buffer_reg[0]\(0),
      I4 => \skid_buffer_reg[0]\(1),
      I5 => m_axi_wready(2),
      O => \^gen_axi.s_axi_wready_i_reg_0\
    );
\skid_buffer[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFFF0CCAA00F0CC"
    )
        port map (
      I0 => mi_rmesg(108),
      I1 => m_axi_rlast(0),
      I2 => m_axi_rlast(2),
      I3 => \skid_buffer_reg[0]\(1),
      I4 => \skid_buffer_reg[0]\(0),
      I5 => m_axi_rlast(1),
      O => \gen_axi.s_axi_rlast_i_reg_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blok_xbar_0_axi_crossbar_v2_1_23_splitter is
  port (
    m_ready_d : out STD_LOGIC_VECTOR ( 2 downto 0 );
    aresetn_d : in STD_LOGIC;
    m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \m_ready_d_reg[2]_0\ : in STD_LOGIC;
    \m_ready_d_reg[2]_1\ : in STD_LOGIC;
    \m_ready_d_reg[2]_2\ : in STD_LOGIC;
    aclk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of blok_xbar_0_axi_crossbar_v2_1_23_splitter : entity is "axi_crossbar_v2_1_23_splitter";
end blok_xbar_0_axi_crossbar_v2_1_23_splitter;

architecture STRUCTURE of blok_xbar_0_axi_crossbar_v2_1_23_splitter is
  signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
  signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
  signal \m_ready_d[2]_i_1_n_0\ : STD_LOGIC;
begin
  m_ready_d(2 downto 0) <= \^m_ready_d\(2 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0AAA0A020222020"
    )
        port map (
      I0 => aresetn_d,
      I1 => m_ready_d0(0),
      I2 => \^m_ready_d\(0),
      I3 => \m_ready_d_reg[2]_0\,
      I4 => \m_ready_d_reg[2]_1\,
      I5 => \m_ready_d_reg[2]_2\,
      O => \m_ready_d[0]_i_1_n_0\
    );
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000002A222A2A"
    )
        port map (
      I0 => aresetn_d,
      I1 => m_ready_d0(0),
      I2 => \^m_ready_d\(0),
      I3 => \m_ready_d_reg[2]_0\,
      I4 => \m_ready_d_reg[2]_1\,
      I5 => \m_ready_d_reg[2]_2\,
      O => \m_ready_d[1]_i_1_n_0\
    );
\m_ready_d[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888888808000808"
    )
        port map (
      I0 => aresetn_d,
      I1 => m_ready_d0(0),
      I2 => \^m_ready_d\(0),
      I3 => \m_ready_d_reg[2]_0\,
      I4 => \m_ready_d_reg[2]_1\,
      I5 => \m_ready_d_reg[2]_2\,
      O => \m_ready_d[2]_i_1_n_0\
    );
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \m_ready_d[0]_i_1_n_0\,
      Q => \^m_ready_d\(0),
      R => '0'
    );
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \m_ready_d[1]_i_1_n_0\,
      Q => \^m_ready_d\(1),
      R => '0'
    );
\m_ready_d_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \m_ready_d[2]_i_1_n_0\,
      Q => \^m_ready_d\(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blok_xbar_0_axi_crossbar_v2_1_23_splitter__parameterized0\ is
  port (
    m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_valid_i : in STD_LOGIC;
    aa_grant_rnw : in STD_LOGIC;
    \m_ready_d_reg[1]_0\ : in STD_LOGIC;
    m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    aresetn_d : in STD_LOGIC;
    aclk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \blok_xbar_0_axi_crossbar_v2_1_23_splitter__parameterized0\ : entity is "axi_crossbar_v2_1_23_splitter";
end \blok_xbar_0_axi_crossbar_v2_1_23_splitter__parameterized0\;

architecture STRUCTURE of \blok_xbar_0_axi_crossbar_v2_1_23_splitter__parameterized0\ is
  signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
  signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
begin
  m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F07000000000000"
    )
        port map (
      I0 => m_valid_i,
      I1 => aa_grant_rnw,
      I2 => \^m_ready_d\(1),
      I3 => \m_ready_d_reg[1]_0\,
      I4 => m_ready_d0(0),
      I5 => aresetn_d,
      O => \m_ready_d[0]_i_1_n_0\
    );
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000F0F800000000"
    )
        port map (
      I0 => m_valid_i,
      I1 => aa_grant_rnw,
      I2 => \^m_ready_d\(1),
      I3 => \m_ready_d_reg[1]_0\,
      I4 => m_ready_d0(0),
      I5 => aresetn_d,
      O => \m_ready_d[1]_i_1_n_0\
    );
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \m_ready_d[0]_i_1_n_0\,
      Q => \^m_ready_d\(0),
      R => '0'
    );
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \m_ready_d[1]_i_1_n_0\,
      Q => \^m_ready_d\(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blok_xbar_0_axi_register_slice_v2_1_22_axic_register_slice is
  port (
    sr_rvalid : out STD_LOGIC;
    aa_rready : out STD_LOGIC;
    m_ready_d0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \m_payload_i_reg[34]_0\ : out STD_LOGIC_VECTOR ( 34 downto 0 );
    s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \aresetn_d_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_valid_i_reg_0 : in STD_LOGIC;
    aclk : in STD_LOGIC;
    s_ready_i_reg_0 : in STD_LOGIC;
    s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_valid_i : in STD_LOGIC;
    aa_grant_rnw : in STD_LOGIC;
    m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
    \skid_buffer_reg[0]_0\ : in STD_LOGIC;
    m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 );
    p_0_in1_in : in STD_LOGIC;
    \m_axi_rready[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of blok_xbar_0_axi_register_slice_v2_1_22_axic_register_slice : entity is "axi_register_slice_v2_1_22_axic_register_slice";
end blok_xbar_0_axi_register_slice_v2_1_22_axic_register_slice;

architecture STRUCTURE of blok_xbar_0_axi_register_slice_v2_1_22_axic_register_slice is
  signal \^aa_rready\ : STD_LOGIC;
  signal \^aresetn_d_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \m_payload_i[12]_i_2_n_0\ : STD_LOGIC;
  signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
  signal \m_payload_i[14]_i_2_n_0\ : STD_LOGIC;
  signal \m_payload_i[15]_i_2_n_0\ : STD_LOGIC;
  signal \m_payload_i[17]_i_2_n_0\ : STD_LOGIC;
  signal \m_payload_i[18]_i_2_n_0\ : STD_LOGIC;
  signal \m_payload_i[1]_i_2_n_0\ : STD_LOGIC;
  signal \m_payload_i[25]_i_2_n_0\ : STD_LOGIC;
  signal \m_payload_i[26]_i_2_n_0\ : STD_LOGIC;
  signal \m_payload_i[28]_i_2_n_0\ : STD_LOGIC;
  signal \m_payload_i[29]_i_2_n_0\ : STD_LOGIC;
  signal \m_payload_i[2]_i_2_n_0\ : STD_LOGIC;
  signal \m_payload_i[30]_i_2_n_0\ : STD_LOGIC;
  signal \m_payload_i[31]_i_2_n_0\ : STD_LOGIC;
  signal \m_payload_i[33]_i_2_n_0\ : STD_LOGIC;
  signal \m_payload_i[34]_i_3_n_0\ : STD_LOGIC;
  signal \m_payload_i[5]_i_2_n_0\ : STD_LOGIC;
  signal \m_payload_i[6]_i_2_n_0\ : STD_LOGIC;
  signal \m_payload_i[7]_i_2_n_0\ : STD_LOGIC;
  signal \^m_payload_i_reg[34]_0\ : STD_LOGIC_VECTOR ( 34 downto 0 );
  signal skid_buffer : STD_LOGIC_VECTOR ( 34 downto 0 );
  signal \skid_buffer[10]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[11]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[16]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[19]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[20]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[21]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[22]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[23]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[24]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[27]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[32]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[3]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[4]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[8]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[9]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
  signal \^sr_rvalid\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \m_axi_rready[0]_INST_0\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \m_axi_rready[1]_INST_0\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \m_axi_rready[2]_INST_0\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \m_payload_i[0]_i_1\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \m_payload_i[34]_i_2\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair21";
begin
  aa_rready <= \^aa_rready\;
  \aresetn_d_reg[1]_0\(1 downto 0) <= \^aresetn_d_reg[1]_0\(1 downto 0);
  \m_payload_i_reg[34]_0\(34 downto 0) <= \^m_payload_i_reg[34]_0\(34 downto 0);
  sr_rvalid <= \^sr_rvalid\;
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => '1',
      Q => \^aresetn_d_reg[1]_0\(0),
      R => SR(0)
    );
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \^aresetn_d_reg[1]_0\(0),
      Q => \^aresetn_d_reg[1]_0\(1),
      R => SR(0)
    );
\m_axi_rready[0]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^aa_rready\,
      I1 => \m_axi_rready[2]\(0),
      O => m_axi_rready(0)
    );
\m_axi_rready[1]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^aa_rready\,
      I1 => \m_axi_rready[2]\(1),
      O => m_axi_rready(1)
    );
\m_axi_rready[2]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^aa_rready\,
      I1 => \m_axi_rready[2]\(2),
      O => m_axi_rready(2)
    );
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \skid_buffer_reg[0]_0\,
      I1 => \^aa_rready\,
      I2 => \skid_buffer_reg_n_0_[0]\,
      O => skid_buffer(0)
    );
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \skid_buffer[10]_i_1_n_0\,
      I1 => \^aa_rready\,
      I2 => \skid_buffer_reg_n_0_[10]\,
      O => skid_buffer(10)
    );
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \skid_buffer[11]_i_1_n_0\,
      I1 => \^aa_rready\,
      I2 => \skid_buffer_reg_n_0_[11]\,
      O => skid_buffer(11)
    );
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[12]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[12]_i_2_n_0\,
      O => skid_buffer(12)
    );
\m_payload_i[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440C00CC440C"
    )
        port map (
      I0 => m_axi_rdata(73),
      I1 => \^aa_rready\,
      I2 => m_axi_rdata(9),
      I3 => Q(1),
      I4 => Q(0),
      I5 => m_axi_rdata(41),
      O => \m_payload_i[12]_i_2_n_0\
    );
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[13]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[13]_i_2_n_0\,
      O => skid_buffer(13)
    );
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440C00CC440C"
    )
        port map (
      I0 => m_axi_rdata(74),
      I1 => \^aa_rready\,
      I2 => m_axi_rdata(10),
      I3 => Q(1),
      I4 => Q(0),
      I5 => m_axi_rdata(42),
      O => \m_payload_i[13]_i_2_n_0\
    );
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[14]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[14]_i_2_n_0\,
      O => skid_buffer(14)
    );
\m_payload_i[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"030503F500000000"
    )
        port map (
      I0 => m_axi_rdata(11),
      I1 => m_axi_rdata(43),
      I2 => Q(1),
      I3 => Q(0),
      I4 => m_axi_rdata(75),
      I5 => \^aa_rready\,
      O => \m_payload_i[14]_i_2_n_0\
    );
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[15]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[15]_i_2_n_0\,
      O => skid_buffer(15)
    );
\m_payload_i[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000C4400CC0C44"
    )
        port map (
      I0 => m_axi_rdata(12),
      I1 => \^aa_rready\,
      I2 => m_axi_rdata(44),
      I3 => Q(0),
      I4 => Q(1),
      I5 => m_axi_rdata(76),
      O => \m_payload_i[15]_i_2_n_0\
    );
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \skid_buffer[16]_i_1_n_0\,
      I1 => \^aa_rready\,
      I2 => \skid_buffer_reg_n_0_[16]\,
      O => skid_buffer(16)
    );
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[17]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[17]_i_2_n_0\,
      O => skid_buffer(17)
    );
\m_payload_i[17]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000C4400CC0C44"
    )
        port map (
      I0 => m_axi_rdata(14),
      I1 => \^aa_rready\,
      I2 => m_axi_rdata(46),
      I3 => Q(0),
      I4 => Q(1),
      I5 => m_axi_rdata(78),
      O => \m_payload_i[17]_i_2_n_0\
    );
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[18]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[18]_i_2_n_0\,
      O => skid_buffer(18)
    );
\m_payload_i[18]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000C4400CC0C44"
    )
        port map (
      I0 => m_axi_rdata(15),
      I1 => \^aa_rready\,
      I2 => m_axi_rdata(47),
      I3 => Q(0),
      I4 => Q(1),
      I5 => m_axi_rdata(79),
      O => \m_payload_i[18]_i_2_n_0\
    );
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \skid_buffer[19]_i_1_n_0\,
      I1 => \^aa_rready\,
      I2 => \skid_buffer_reg_n_0_[19]\,
      O => skid_buffer(19)
    );
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[1]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[1]_i_2_n_0\,
      O => skid_buffer(1)
    );
\m_payload_i[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440C00CC440C"
    )
        port map (
      I0 => m_axi_rresp(4),
      I1 => \^aa_rready\,
      I2 => m_axi_rresp(0),
      I3 => Q(1),
      I4 => Q(0),
      I5 => m_axi_rresp(2),
      O => \m_payload_i[1]_i_2_n_0\
    );
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \skid_buffer[20]_i_1_n_0\,
      I1 => \^aa_rready\,
      I2 => \skid_buffer_reg_n_0_[20]\,
      O => skid_buffer(20)
    );
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \skid_buffer[21]_i_1_n_0\,
      I1 => \^aa_rready\,
      I2 => \skid_buffer_reg_n_0_[21]\,
      O => skid_buffer(21)
    );
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \skid_buffer[22]_i_1_n_0\,
      I1 => \^aa_rready\,
      I2 => \skid_buffer_reg_n_0_[22]\,
      O => skid_buffer(22)
    );
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \skid_buffer[23]_i_1_n_0\,
      I1 => \^aa_rready\,
      I2 => \skid_buffer_reg_n_0_[23]\,
      O => skid_buffer(23)
    );
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \skid_buffer[24]_i_1_n_0\,
      I1 => \^aa_rready\,
      I2 => \skid_buffer_reg_n_0_[24]\,
      O => skid_buffer(24)
    );
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[25]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[25]_i_2_n_0\,
      O => skid_buffer(25)
    );
\m_payload_i[25]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000C4400CC0C44"
    )
        port map (
      I0 => m_axi_rdata(22),
      I1 => \^aa_rready\,
      I2 => m_axi_rdata(54),
      I3 => Q(0),
      I4 => Q(1),
      I5 => m_axi_rdata(86),
      O => \m_payload_i[25]_i_2_n_0\
    );
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[26]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[26]_i_2_n_0\,
      O => skid_buffer(26)
    );
\m_payload_i[26]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0530053F00000000"
    )
        port map (
      I0 => m_axi_rdata(55),
      I1 => m_axi_rdata(87),
      I2 => Q(1),
      I3 => Q(0),
      I4 => m_axi_rdata(23),
      I5 => \^aa_rready\,
      O => \m_payload_i[26]_i_2_n_0\
    );
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \skid_buffer[27]_i_1_n_0\,
      I1 => \^aa_rready\,
      I2 => \skid_buffer_reg_n_0_[27]\,
      O => skid_buffer(27)
    );
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[28]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[28]_i_2_n_0\,
      O => skid_buffer(28)
    );
\m_payload_i[28]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0530053F00000000"
    )
        port map (
      I0 => m_axi_rdata(57),
      I1 => m_axi_rdata(89),
      I2 => Q(1),
      I3 => Q(0),
      I4 => m_axi_rdata(25),
      I5 => \^aa_rready\,
      O => \m_payload_i[28]_i_2_n_0\
    );
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[29]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[29]_i_2_n_0\,
      O => skid_buffer(29)
    );
\m_payload_i[29]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440C00CC440C"
    )
        port map (
      I0 => m_axi_rdata(90),
      I1 => \^aa_rready\,
      I2 => m_axi_rdata(26),
      I3 => Q(1),
      I4 => Q(0),
      I5 => m_axi_rdata(58),
      O => \m_payload_i[29]_i_2_n_0\
    );
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[2]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[2]_i_2_n_0\,
      O => skid_buffer(2)
    );
\m_payload_i[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440C00CC440C"
    )
        port map (
      I0 => m_axi_rresp(5),
      I1 => \^aa_rready\,
      I2 => m_axi_rresp(1),
      I3 => Q(1),
      I4 => Q(0),
      I5 => m_axi_rresp(3),
      O => \m_payload_i[2]_i_2_n_0\
    );
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[30]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[30]_i_2_n_0\,
      O => skid_buffer(30)
    );
\m_payload_i[30]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"030503F500000000"
    )
        port map (
      I0 => m_axi_rdata(27),
      I1 => m_axi_rdata(59),
      I2 => Q(1),
      I3 => Q(0),
      I4 => m_axi_rdata(91),
      I5 => \^aa_rready\,
      O => \m_payload_i[30]_i_2_n_0\
    );
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[31]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[31]_i_2_n_0\,
      O => skid_buffer(31)
    );
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000C4400CC0C44"
    )
        port map (
      I0 => m_axi_rdata(28),
      I1 => \^aa_rready\,
      I2 => m_axi_rdata(60),
      I3 => Q(0),
      I4 => Q(1),
      I5 => m_axi_rdata(92),
      O => \m_payload_i[31]_i_2_n_0\
    );
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \skid_buffer[32]_i_1_n_0\,
      I1 => \^aa_rready\,
      I2 => \skid_buffer_reg_n_0_[32]\,
      O => skid_buffer(32)
    );
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[33]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[33]_i_2_n_0\,
      O => skid_buffer(33)
    );
\m_payload_i[33]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440C00CC440C"
    )
        port map (
      I0 => m_axi_rdata(94),
      I1 => \^aa_rready\,
      I2 => m_axi_rdata(30),
      I3 => Q(1),
      I4 => Q(0),
      I5 => m_axi_rdata(62),
      O => \m_payload_i[33]_i_2_n_0\
    );
\m_payload_i[34]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[34]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[34]_i_3_n_0\,
      O => skid_buffer(34)
    );
\m_payload_i[34]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440C00CC440C"
    )
        port map (
      I0 => m_axi_rdata(95),
      I1 => \^aa_rready\,
      I2 => m_axi_rdata(31),
      I3 => Q(1),
      I4 => Q(0),
      I5 => m_axi_rdata(63),
      O => \m_payload_i[34]_i_3_n_0\
    );
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \skid_buffer[3]_i_1_n_0\,
      I1 => \^aa_rready\,
      I2 => \skid_buffer_reg_n_0_[3]\,
      O => skid_buffer(3)
    );
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \skid_buffer[4]_i_1_n_0\,
      I1 => \^aa_rready\,
      I2 => \skid_buffer_reg_n_0_[4]\,
      O => skid_buffer(4)
    );
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[5]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[5]_i_2_n_0\,
      O => skid_buffer(5)
    );
\m_payload_i[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440C00CC440C"
    )
        port map (
      I0 => m_axi_rdata(66),
      I1 => \^aa_rready\,
      I2 => m_axi_rdata(2),
      I3 => Q(1),
      I4 => Q(0),
      I5 => m_axi_rdata(34),
      O => \m_payload_i[5]_i_2_n_0\
    );
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[6]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[6]_i_2_n_0\,
      O => skid_buffer(6)
    );
\m_payload_i[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440C00CC440C"
    )
        port map (
      I0 => m_axi_rdata(67),
      I1 => \^aa_rready\,
      I2 => m_axi_rdata(3),
      I3 => Q(1),
      I4 => Q(0),
      I5 => m_axi_rdata(35),
      O => \m_payload_i[6]_i_2_n_0\
    );
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \skid_buffer_reg_n_0_[7]\,
      I1 => \^aa_rready\,
      I2 => \m_payload_i[7]_i_2_n_0\,
      O => skid_buffer(7)
    );
\m_payload_i[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440C00CC440C"
    )
        port map (
      I0 => m_axi_rdata(68),
      I1 => \^aa_rready\,
      I2 => m_axi_rdata(4),
      I3 => Q(1),
      I4 => Q(0),
      I5 => m_axi_rdata(36),
      O => \m_payload_i[7]_i_2_n_0\
    );
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \skid_buffer[8]_i_1_n_0\,
      I1 => \^aa_rready\,
      I2 => \skid_buffer_reg_n_0_[8]\,
      O => skid_buffer(8)
    );
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \skid_buffer[9]_i_1_n_0\,
      I1 => \^aa_rready\,
      I2 => \skid_buffer_reg_n_0_[9]\,
      O => skid_buffer(9)
    );
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(0),
      Q => \^m_payload_i_reg[34]_0\(0),
      R => '0'
    );
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(10),
      Q => \^m_payload_i_reg[34]_0\(10),
      R => '0'
    );
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(11),
      Q => \^m_payload_i_reg[34]_0\(11),
      R => '0'
    );
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(12),
      Q => \^m_payload_i_reg[34]_0\(12),
      R => '0'
    );
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(13),
      Q => \^m_payload_i_reg[34]_0\(13),
      R => '0'
    );
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(14),
      Q => \^m_payload_i_reg[34]_0\(14),
      R => '0'
    );
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(15),
      Q => \^m_payload_i_reg[34]_0\(15),
      R => '0'
    );
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(16),
      Q => \^m_payload_i_reg[34]_0\(16),
      R => '0'
    );
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(17),
      Q => \^m_payload_i_reg[34]_0\(17),
      R => '0'
    );
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(18),
      Q => \^m_payload_i_reg[34]_0\(18),
      R => '0'
    );
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(19),
      Q => \^m_payload_i_reg[34]_0\(19),
      R => '0'
    );
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(1),
      Q => \^m_payload_i_reg[34]_0\(1),
      R => '0'
    );
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(20),
      Q => \^m_payload_i_reg[34]_0\(20),
      R => '0'
    );
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(21),
      Q => \^m_payload_i_reg[34]_0\(21),
      R => '0'
    );
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(22),
      Q => \^m_payload_i_reg[34]_0\(22),
      R => '0'
    );
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(23),
      Q => \^m_payload_i_reg[34]_0\(23),
      R => '0'
    );
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(24),
      Q => \^m_payload_i_reg[34]_0\(24),
      R => '0'
    );
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(25),
      Q => \^m_payload_i_reg[34]_0\(25),
      R => '0'
    );
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(26),
      Q => \^m_payload_i_reg[34]_0\(26),
      R => '0'
    );
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(27),
      Q => \^m_payload_i_reg[34]_0\(27),
      R => '0'
    );
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(28),
      Q => \^m_payload_i_reg[34]_0\(28),
      R => '0'
    );
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(29),
      Q => \^m_payload_i_reg[34]_0\(29),
      R => '0'
    );
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(2),
      Q => \^m_payload_i_reg[34]_0\(2),
      R => '0'
    );
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(30),
      Q => \^m_payload_i_reg[34]_0\(30),
      R => '0'
    );
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(31),
      Q => \^m_payload_i_reg[34]_0\(31),
      R => '0'
    );
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(32),
      Q => \^m_payload_i_reg[34]_0\(32),
      R => '0'
    );
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(33),
      Q => \^m_payload_i_reg[34]_0\(33),
      R => '0'
    );
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(34),
      Q => \^m_payload_i_reg[34]_0\(34),
      R => '0'
    );
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(3),
      Q => \^m_payload_i_reg[34]_0\(3),
      R => '0'
    );
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(4),
      Q => \^m_payload_i_reg[34]_0\(4),
      R => '0'
    );
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(5),
      Q => \^m_payload_i_reg[34]_0\(5),
      R => '0'
    );
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(6),
      Q => \^m_payload_i_reg[34]_0\(6),
      R => '0'
    );
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(7),
      Q => \^m_payload_i_reg[34]_0\(7),
      R => '0'
    );
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(8),
      Q => \^m_payload_i_reg[34]_0\(8),
      R => '0'
    );
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(9),
      Q => \^m_payload_i_reg[34]_0\(9),
      R => '0'
    );
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF80000000"
    )
        port map (
      I0 => \^m_payload_i_reg[34]_0\(0),
      I1 => \^sr_rvalid\,
      I2 => s_axi_rready(0),
      I3 => m_valid_i,
      I4 => aa_grant_rnw,
      I5 => m_ready_d(0),
      O => m_ready_d0(0)
    );
m_valid_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => m_valid_i_reg_0,
      Q => \^sr_rvalid\,
      R => '0'
    );
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^sr_rvalid\,
      I1 => p_0_in1_in,
      O => s_axi_rvalid(0)
    );
s_ready_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => s_ready_i_reg_0,
      Q => \^aa_rready\,
      R => '0'
    );
\skid_buffer[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0CAF0CA0"
    )
        port map (
      I0 => m_axi_rdata(39),
      I1 => m_axi_rdata(71),
      I2 => Q(0),
      I3 => Q(1),
      I4 => m_axi_rdata(7),
      O => \skid_buffer[10]_i_1_n_0\
    );
\skid_buffer[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FCA00CA"
    )
        port map (
      I0 => m_axi_rdata(8),
      I1 => m_axi_rdata(72),
      I2 => Q(1),
      I3 => Q(0),
      I4 => m_axi_rdata(40),
      O => \skid_buffer[11]_i_1_n_0\
    );
\skid_buffer[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FCA00CA"
    )
        port map (
      I0 => m_axi_rdata(13),
      I1 => m_axi_rdata(77),
      I2 => Q(1),
      I3 => Q(0),
      I4 => m_axi_rdata(45),
      O => \skid_buffer[16]_i_1_n_0\
    );
\skid_buffer[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0CAF0CA0"
    )
        port map (
      I0 => m_axi_rdata(48),
      I1 => m_axi_rdata(80),
      I2 => Q(0),
      I3 => Q(1),
      I4 => m_axi_rdata(16),
      O => \skid_buffer[19]_i_1_n_0\
    );
\skid_buffer[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FCA00CA"
    )
        port map (
      I0 => m_axi_rdata(17),
      I1 => m_axi_rdata(81),
      I2 => Q(1),
      I3 => Q(0),
      I4 => m_axi_rdata(49),
      O => \skid_buffer[20]_i_1_n_0\
    );
\skid_buffer[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FCA00CA"
    )
        port map (
      I0 => m_axi_rdata(18),
      I1 => m_axi_rdata(82),
      I2 => Q(1),
      I3 => Q(0),
      I4 => m_axi_rdata(50),
      O => \skid_buffer[21]_i_1_n_0\
    );
\skid_buffer[22]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FCA00CA"
    )
        port map (
      I0 => m_axi_rdata(19),
      I1 => m_axi_rdata(83),
      I2 => Q(1),
      I3 => Q(0),
      I4 => m_axi_rdata(51),
      O => \skid_buffer[22]_i_1_n_0\
    );
\skid_buffer[23]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FCA00CA"
    )
        port map (
      I0 => m_axi_rdata(20),
      I1 => m_axi_rdata(84),
      I2 => Q(1),
      I3 => Q(0),
      I4 => m_axi_rdata(52),
      O => \skid_buffer[23]_i_1_n_0\
    );
\skid_buffer[24]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FCA00CA"
    )
        port map (
      I0 => m_axi_rdata(21),
      I1 => m_axi_rdata(53),
      I2 => Q(0),
      I3 => Q(1),
      I4 => m_axi_rdata(85),
      O => \skid_buffer[24]_i_1_n_0\
    );
\skid_buffer[27]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FCA00CA"
    )
        port map (
      I0 => m_axi_rdata(24),
      I1 => m_axi_rdata(88),
      I2 => Q(1),
      I3 => Q(0),
      I4 => m_axi_rdata(56),
      O => \skid_buffer[27]_i_1_n_0\
    );
\skid_buffer[32]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FCA00CA"
    )
        port map (
      I0 => m_axi_rdata(29),
      I1 => m_axi_rdata(93),
      I2 => Q(1),
      I3 => Q(0),
      I4 => m_axi_rdata(61),
      O => \skid_buffer[32]_i_1_n_0\
    );
\skid_buffer[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FCA00CA"
    )
        port map (
      I0 => m_axi_rdata(0),
      I1 => m_axi_rdata(32),
      I2 => Q(0),
      I3 => Q(1),
      I4 => m_axi_rdata(64),
      O => \skid_buffer[3]_i_1_n_0\
    );
\skid_buffer[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FCA00CA"
    )
        port map (
      I0 => m_axi_rdata(1),
      I1 => m_axi_rdata(65),
      I2 => Q(1),
      I3 => Q(0),
      I4 => m_axi_rdata(33),
      O => \skid_buffer[4]_i_1_n_0\
    );
\skid_buffer[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0ACF0AC0"
    )
        port map (
      I0 => m_axi_rdata(69),
      I1 => m_axi_rdata(37),
      I2 => Q(0),
      I3 => Q(1),
      I4 => m_axi_rdata(5),
      O => \skid_buffer[8]_i_1_n_0\
    );
\skid_buffer[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FCA00CA"
    )
        port map (
      I0 => m_axi_rdata(6),
      I1 => m_axi_rdata(70),
      I2 => Q(1),
      I3 => Q(0),
      I4 => m_axi_rdata(38),
      O => \skid_buffer[9]_i_1_n_0\
    );
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^aa_rready\,
      D => \skid_buffer_reg[0]_0\,
      Q => \skid_buffer_reg_n_0_[0]\,
      R => '0'
    );
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^aa_rready\,
      D => \skid_buffer[10]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[10]\,
      R => '0'
    );
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^aa_rready\,
      D => \skid_buffer[11]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[11]\,
      R => '0'
    );
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(12),
      Q => \skid_buffer_reg_n_0_[12]\,
      R => '0'
    );
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(13),
      Q => \skid_buffer_reg_n_0_[13]\,
      R => '0'
    );
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(14),
      Q => \skid_buffer_reg_n_0_[14]\,
      R => '0'
    );
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(15),
      Q => \skid_buffer_reg_n_0_[15]\,
      R => '0'
    );
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^aa_rready\,
      D => \skid_buffer[16]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[16]\,
      R => '0'
    );
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(17),
      Q => \skid_buffer_reg_n_0_[17]\,
      R => '0'
    );
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(18),
      Q => \skid_buffer_reg_n_0_[18]\,
      R => '0'
    );
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^aa_rready\,
      D => \skid_buffer[19]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[19]\,
      R => '0'
    );
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(1),
      Q => \skid_buffer_reg_n_0_[1]\,
      R => '0'
    );
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^aa_rready\,
      D => \skid_buffer[20]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[20]\,
      R => '0'
    );
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^aa_rready\,
      D => \skid_buffer[21]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[21]\,
      R => '0'
    );
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^aa_rready\,
      D => \skid_buffer[22]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[22]\,
      R => '0'
    );
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^aa_rready\,
      D => \skid_buffer[23]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[23]\,
      R => '0'
    );
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^aa_rready\,
      D => \skid_buffer[24]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[24]\,
      R => '0'
    );
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(25),
      Q => \skid_buffer_reg_n_0_[25]\,
      R => '0'
    );
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(26),
      Q => \skid_buffer_reg_n_0_[26]\,
      R => '0'
    );
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^aa_rready\,
      D => \skid_buffer[27]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[27]\,
      R => '0'
    );
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(28),
      Q => \skid_buffer_reg_n_0_[28]\,
      R => '0'
    );
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(29),
      Q => \skid_buffer_reg_n_0_[29]\,
      R => '0'
    );
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(2),
      Q => \skid_buffer_reg_n_0_[2]\,
      R => '0'
    );
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(30),
      Q => \skid_buffer_reg_n_0_[30]\,
      R => '0'
    );
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(31),
      Q => \skid_buffer_reg_n_0_[31]\,
      R => '0'
    );
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^aa_rready\,
      D => \skid_buffer[32]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[32]\,
      R => '0'
    );
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(33),
      Q => \skid_buffer_reg_n_0_[33]\,
      R => '0'
    );
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(34),
      Q => \skid_buffer_reg_n_0_[34]\,
      R => '0'
    );
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^aa_rready\,
      D => \skid_buffer[3]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[3]\,
      R => '0'
    );
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^aa_rready\,
      D => \skid_buffer[4]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[4]\,
      R => '0'
    );
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(5),
      Q => \skid_buffer_reg_n_0_[5]\,
      R => '0'
    );
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(6),
      Q => \skid_buffer_reg_n_0_[6]\,
      R => '0'
    );
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(7),
      Q => \skid_buffer_reg_n_0_[7]\,
      R => '0'
    );
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^aa_rready\,
      D => \skid_buffer[8]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[8]\,
      R => '0'
    );
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^aa_rready\,
      D => \skid_buffer[9]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[9]\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blok_xbar_0_axi_crossbar_v2_1_23_crossbar_sasd is
  port (
    Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
    \m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 34 downto 0 );
    m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 );
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_rlast : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
    m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 );
    m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_bresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
    s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
    s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of blok_xbar_0_axi_crossbar_v2_1_23_crossbar_sasd : entity is "axi_crossbar_v2_1_23_crossbar_sasd";
end blok_xbar_0_axi_crossbar_v2_1_23_crossbar_sasd;

architecture STRUCTURE of blok_xbar_0_axi_crossbar_v2_1_23_crossbar_sasd is
  signal \^q\ : STD_LOGIC_VECTOR ( 68 downto 0 );
  signal aa_grant_rnw : STD_LOGIC;
  signal aa_rready : STD_LOGIC;
  signal addr_arbiter_inst_n_103 : STD_LOGIC;
  signal addr_arbiter_inst_n_104 : STD_LOGIC;
  signal addr_arbiter_inst_n_107 : STD_LOGIC;
  signal addr_arbiter_inst_n_4 : STD_LOGIC;
  signal addr_arbiter_inst_n_5 : STD_LOGIC;
  signal addr_arbiter_inst_n_6 : STD_LOGIC;
  signal addr_arbiter_inst_n_78 : STD_LOGIC;
  signal addr_arbiter_inst_n_8 : STD_LOGIC;
  signal addr_arbiter_inst_n_80 : STD_LOGIC;
  signal addr_arbiter_inst_n_85 : STD_LOGIC;
  signal addr_arbiter_inst_n_87 : STD_LOGIC;
  signal addr_arbiter_inst_n_91 : STD_LOGIC;
  signal addr_arbiter_inst_n_96 : STD_LOGIC;
  signal addr_arbiter_inst_n_97 : STD_LOGIC;
  signal addr_arbiter_inst_n_98 : STD_LOGIC;
  signal aresetn_d : STD_LOGIC;
  signal \gen_axi.s_axi_rid_i\ : STD_LOGIC;
  signal \gen_decerr.decerr_slave_inst_n_2\ : STD_LOGIC;
  signal \gen_decerr.decerr_slave_inst_n_3\ : STD_LOGIC;
  signal \gen_decerr.decerr_slave_inst_n_4\ : STD_LOGIC;
  signal \gen_decerr.decerr_slave_inst_n_5\ : STD_LOGIC;
  signal \gen_decerr.decerr_slave_inst_n_6\ : STD_LOGIC;
  signal \gen_decerr.decerr_slave_inst_n_7\ : STD_LOGIC;
  signal \gen_decerr.decerr_slave_inst_n_8\ : STD_LOGIC;
  signal \gen_decerr.decerr_slave_inst_n_9\ : STD_LOGIC;
  signal m_atarget_enc : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \m_atarget_enc[0]_i_1_n_0\ : STD_LOGIC;
  signal \m_atarget_enc[1]_i_1_n_0\ : STD_LOGIC;
  signal m_atarget_hot : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal m_atarget_hot0 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal m_ready_d0 : STD_LOGIC_VECTOR ( 2 to 2 );
  signal m_ready_d0_0 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal m_ready_d_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal m_valid_i : STD_LOGIC;
  signal mi_arready : STD_LOGIC_VECTOR ( 3 to 3 );
  signal mi_rvalid : STD_LOGIC_VECTOR ( 3 to 3 );
  signal p_0_in1_in : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal reg_slice_r_n_42 : STD_LOGIC;
  signal reg_slice_r_n_43 : STD_LOGIC;
  signal reset : STD_LOGIC;
  signal sr_rvalid : STD_LOGIC;
begin
  Q(68 downto 0) <= \^q\(68 downto 0);
addr_arbiter_inst: entity work.blok_xbar_0_axi_crossbar_v2_1_23_addr_arbiter_sasd
     port map (
      D(3) => addr_arbiter_inst_n_4,
      D(2) => addr_arbiter_inst_n_5,
      D(1) => addr_arbiter_inst_n_6,
      D(0) => m_atarget_hot0(0),
      E(0) => p_1_in,
      Q(68 downto 0) => \^q\(68 downto 0),
      SR(0) => reset,
      aa_grant_rnw => aa_grant_rnw,
      aa_rready => aa_rready,
      aclk => aclk,
      aresetn_d => aresetn_d,
      \aresetn_d_reg[0]\ => addr_arbiter_inst_n_87,
      \aresetn_d_reg[1]\ => addr_arbiter_inst_n_85,
      \gen_axi.s_axi_awready_i_reg\(3 downto 0) => m_atarget_hot(3 downto 0),
      \gen_axi.s_axi_awready_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_9\,
      \gen_axi.s_axi_rid_i\ => \gen_axi.s_axi_rid_i\,
      \gen_no_arbiter.grant_rnw_reg_0\ => addr_arbiter_inst_n_98,
      \gen_no_arbiter.m_amesg_i_reg[27]_0\ => addr_arbiter_inst_n_80,
      \gen_no_arbiter.m_amesg_i_reg[34]_0\ => addr_arbiter_inst_n_8,
      \gen_no_arbiter.m_amesg_i_reg[47]_0\ => addr_arbiter_inst_n_107,
      \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\ => \gen_decerr.decerr_slave_inst_n_2\,
      \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1\ => \gen_decerr.decerr_slave_inst_n_8\,
      \gen_no_arbiter.m_valid_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_7\,
      m_axi_arvalid(2 downto 0) => m_axi_arvalid(2 downto 0),
      m_axi_awvalid(2 downto 0) => m_axi_awvalid(2 downto 0),
      m_axi_bready(2 downto 0) => m_axi_bready(2 downto 0),
      m_axi_wvalid(2 downto 0) => m_axi_wvalid(2 downto 0),
      m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
      m_ready_d0(0) => m_ready_d0(2),
      m_ready_d0_0(0) => m_ready_d0_0(0),
      m_ready_d_1(2 downto 0) => m_ready_d_1(2 downto 0),
      \m_ready_d_reg[0]\ => addr_arbiter_inst_n_103,
      \m_ready_d_reg[1]\ => addr_arbiter_inst_n_78,
      \m_ready_d_reg[2]\ => addr_arbiter_inst_n_91,
      m_valid_i => m_valid_i,
      m_valid_i_reg(1) => reg_slice_r_n_42,
      m_valid_i_reg(0) => reg_slice_r_n_43,
      mi_arready(0) => mi_arready(3),
      mi_rvalid(0) => mi_rvalid(3),
      p_0_in1_in => p_0_in1_in,
      s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
      s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
      s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
      s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
      s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
      s_axi_arlock(0) => s_axi_arlock(0),
      s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
      s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
      s_axi_arready(0) => s_axi_arready(0),
      s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
      s_axi_arvalid(0) => s_axi_arvalid(0),
      s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
      s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
      s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
      s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
      s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
      s_axi_awlock(0) => s_axi_awlock(0),
      s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
      s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
      s_axi_awready(0) => s_axi_awready(0),
      s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
      s_axi_awvalid(0) => s_axi_awvalid(0),
      s_axi_bready(0) => s_axi_bready(0),
      s_axi_bready_0_sp_1 => addr_arbiter_inst_n_104,
      s_axi_bvalid(0) => s_axi_bvalid(0),
      s_axi_bvalid_0_sp_1 => \gen_decerr.decerr_slave_inst_n_4\,
      s_axi_rready(0) => s_axi_rready(0),
      s_axi_wlast(0) => s_axi_wlast(0),
      \s_axi_wlast[0]_0\ => addr_arbiter_inst_n_97,
      s_axi_wlast_0_sp_1 => addr_arbiter_inst_n_96,
      s_axi_wready(0) => s_axi_wready(0),
      s_axi_wready_0_sp_1 => \gen_decerr.decerr_slave_inst_n_3\,
      s_axi_wvalid(0) => s_axi_wvalid(0),
      s_ready_i_reg => \gen_decerr.decerr_slave_inst_n_6\,
      sr_rvalid => sr_rvalid
    );
aresetn_d_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => aresetn,
      Q => aresetn_d,
      R => '0'
    );
\gen_decerr.decerr_slave_inst\: entity work.blok_xbar_0_axi_crossbar_v2_1_23_decerr_slave
     port map (
      \FSM_onehot_gen_axi.write_cs_reg[2]_0\ => \gen_decerr.decerr_slave_inst_n_9\,
      Q(0) => m_atarget_hot(3),
      SR(0) => reset,
      aa_grant_rnw => aa_grant_rnw,
      aa_rready => aa_rready,
      aclk => aclk,
      aresetn_d => aresetn_d,
      \gen_axi.read_cnt_reg[7]_0\(7 downto 0) => \^q\(51 downto 44),
      \gen_axi.s_axi_arready_i_reg_0\ => addr_arbiter_inst_n_78,
      \gen_axi.s_axi_awready_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_8\,
      \gen_axi.s_axi_awready_i_reg_1\ => addr_arbiter_inst_n_103,
      \gen_axi.s_axi_awready_i_reg_2\ => addr_arbiter_inst_n_91,
      \gen_axi.s_axi_bvalid_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_4\,
      \gen_axi.s_axi_rid_i\ => \gen_axi.s_axi_rid_i\,
      \gen_axi.s_axi_rlast_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_5\,
      \gen_axi.s_axi_rlast_i_reg_1\ => addr_arbiter_inst_n_107,
      \gen_axi.s_axi_wready_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_3\,
      \gen_axi.s_axi_wready_i_reg_1\ => addr_arbiter_inst_n_98,
      \gen_no_arbiter.m_grant_hot_i_reg[0]_inv\ => addr_arbiter_inst_n_97,
      \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\ => addr_arbiter_inst_n_104,
      m_axi_arready(2 downto 0) => m_axi_arready(2 downto 0),
      m_axi_arready_0_sp_1 => \gen_decerr.decerr_slave_inst_n_7\,
      m_axi_awready(2 downto 0) => m_axi_awready(2 downto 0),
      m_axi_bvalid(2 downto 0) => m_axi_bvalid(2 downto 0),
      m_axi_rlast(2 downto 0) => m_axi_rlast(2 downto 0),
      m_axi_rvalid(2 downto 0) => m_axi_rvalid(2 downto 0),
      m_axi_rvalid_0_sp_1 => \gen_decerr.decerr_slave_inst_n_6\,
      m_axi_wready(2 downto 0) => m_axi_wready(2 downto 0),
      m_ready_d(2 downto 0) => m_ready_d_1(2 downto 0),
      \m_ready_d_reg[1]\ => \gen_decerr.decerr_slave_inst_n_2\,
      m_valid_i => m_valid_i,
      mi_arready(0) => mi_arready(3),
      mi_rvalid(0) => mi_rvalid(3),
      s_axi_wlast(0) => s_axi_wlast(0),
      \skid_buffer_reg[0]\(1 downto 0) => m_atarget_enc(1 downto 0)
    );
\m_atarget_enc[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEFEFEEE"
    )
        port map (
      I0 => addr_arbiter_inst_n_8,
      I1 => addr_arbiter_inst_n_80,
      I2 => \^q\(38),
      I3 => \^q\(26),
      I4 => \^q\(25),
      I5 => \^q\(37),
      O => \m_atarget_enc[0]_i_1_n_0\
    );
\m_atarget_enc[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => addr_arbiter_inst_n_8,
      I1 => addr_arbiter_inst_n_80,
      I2 => \^q\(38),
      O => \m_atarget_enc[1]_i_1_n_0\
    );
\m_atarget_enc_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \m_atarget_enc[0]_i_1_n_0\,
      Q => m_atarget_enc(0),
      R => reset
    );
\m_atarget_enc_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \m_atarget_enc[1]_i_1_n_0\,
      Q => m_atarget_enc(1),
      R => reset
    );
\m_atarget_hot_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => m_atarget_hot0(0),
      Q => m_atarget_hot(0),
      R => reset
    );
\m_atarget_hot_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => addr_arbiter_inst_n_6,
      Q => m_atarget_hot(1),
      R => reset
    );
\m_atarget_hot_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => addr_arbiter_inst_n_5,
      Q => m_atarget_hot(2),
      R => reset
    );
\m_atarget_hot_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => addr_arbiter_inst_n_4,
      Q => m_atarget_hot(3),
      R => reset
    );
reg_slice_r: entity work.blok_xbar_0_axi_register_slice_v2_1_22_axic_register_slice
     port map (
      E(0) => p_1_in,
      Q(1 downto 0) => m_atarget_enc(1 downto 0),
      SR(0) => reset,
      aa_grant_rnw => aa_grant_rnw,
      aa_rready => aa_rready,
      aclk => aclk,
      \aresetn_d_reg[1]_0\(1) => reg_slice_r_n_42,
      \aresetn_d_reg[1]_0\(0) => reg_slice_r_n_43,
      m_axi_rdata(95 downto 0) => m_axi_rdata(95 downto 0),
      m_axi_rready(2 downto 0) => m_axi_rready(2 downto 0),
      \m_axi_rready[2]\(2 downto 0) => m_atarget_hot(2 downto 0),
      m_axi_rresp(5 downto 0) => m_axi_rresp(5 downto 0),
      \m_payload_i_reg[34]_0\(34 downto 0) => \m_payload_i_reg[34]\(34 downto 0),
      m_ready_d(0) => m_ready_d(0),
      m_ready_d0(0) => m_ready_d0_0(0),
      m_valid_i => m_valid_i,
      m_valid_i_reg_0 => addr_arbiter_inst_n_85,
      p_0_in1_in => p_0_in1_in,
      s_axi_rready(0) => s_axi_rready(0),
      s_axi_rvalid(0) => s_axi_rvalid(0),
      s_ready_i_reg_0 => addr_arbiter_inst_n_87,
      \skid_buffer_reg[0]_0\ => \gen_decerr.decerr_slave_inst_n_5\,
      sr_rvalid => sr_rvalid
    );
\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FCEEFC22"
    )
        port map (
      I0 => m_axi_bresp(0),
      I1 => m_atarget_enc(1),
      I2 => m_axi_bresp(2),
      I3 => m_atarget_enc(0),
      I4 => m_axi_bresp(4),
      O => s_axi_bresp(0)
    );
\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FCEEFC22"
    )
        port map (
      I0 => m_axi_bresp(1),
      I1 => m_atarget_enc(1),
      I2 => m_axi_bresp(3),
      I3 => m_atarget_enc(0),
      I4 => m_axi_bresp(5),
      O => s_axi_bresp(1)
    );
splitter_ar: entity work.\blok_xbar_0_axi_crossbar_v2_1_23_splitter__parameterized0\
     port map (
      aa_grant_rnw => aa_grant_rnw,
      aclk => aclk,
      aresetn_d => aresetn_d,
      m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
      m_ready_d0(0) => m_ready_d0_0(0),
      \m_ready_d_reg[1]_0\ => \gen_decerr.decerr_slave_inst_n_7\,
      m_valid_i => m_valid_i
    );
splitter_aw: entity work.blok_xbar_0_axi_crossbar_v2_1_23_splitter
     port map (
      aclk => aclk,
      aresetn_d => aresetn_d,
      m_ready_d(2 downto 0) => m_ready_d_1(2 downto 0),
      m_ready_d0(0) => m_ready_d0(2),
      \m_ready_d_reg[2]_0\ => \gen_decerr.decerr_slave_inst_n_4\,
      \m_ready_d_reg[2]_1\ => addr_arbiter_inst_n_104,
      \m_ready_d_reg[2]_2\ => addr_arbiter_inst_n_96
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar is
  port (
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
    s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_awid : out STD_LOGIC_VECTOR ( 35 downto 0 );
    m_axi_awaddr : out STD_LOGIC_VECTOR ( 95 downto 0 );
    m_axi_awlen : out STD_LOGIC_VECTOR ( 23 downto 0 );
    m_axi_awsize : out STD_LOGIC_VECTOR ( 8 downto 0 );
    m_axi_awburst : out STD_LOGIC_VECTOR ( 5 downto 0 );
    m_axi_awlock : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awcache : out STD_LOGIC_VECTOR ( 11 downto 0 );
    m_axi_awprot : out STD_LOGIC_VECTOR ( 8 downto 0 );
    m_axi_awregion : out STD_LOGIC_VECTOR ( 11 downto 0 );
    m_axi_awqos : out STD_LOGIC_VECTOR ( 11 downto 0 );
    m_axi_awuser : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_wid : out STD_LOGIC_VECTOR ( 35 downto 0 );
    m_axi_wdata : out STD_LOGIC_VECTOR ( 95 downto 0 );
    m_axi_wstrb : out STD_LOGIC_VECTOR ( 11 downto 0 );
    m_axi_wlast : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_wuser : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_bid : in STD_LOGIC_VECTOR ( 35 downto 0 );
    m_axi_bresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
    m_axi_buser : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arid : out STD_LOGIC_VECTOR ( 35 downto 0 );
    m_axi_araddr : out STD_LOGIC_VECTOR ( 95 downto 0 );
    m_axi_arlen : out STD_LOGIC_VECTOR ( 23 downto 0 );
    m_axi_arsize : out STD_LOGIC_VECTOR ( 8 downto 0 );
    m_axi_arburst : out STD_LOGIC_VECTOR ( 5 downto 0 );
    m_axi_arlock : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arcache : out STD_LOGIC_VECTOR ( 11 downto 0 );
    m_axi_arprot : out STD_LOGIC_VECTOR ( 8 downto 0 );
    m_axi_arregion : out STD_LOGIC_VECTOR ( 11 downto 0 );
    m_axi_arqos : out STD_LOGIC_VECTOR ( 11 downto 0 );
    m_axi_aruser : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_rid : in STD_LOGIC_VECTOR ( 35 downto 0 );
    m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 );
    m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
    m_axi_rlast : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_ruser : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute C_AXI_ADDR_WIDTH : integer;
  attribute C_AXI_ADDR_WIDTH of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 32;
  attribute C_AXI_ARUSER_WIDTH : integer;
  attribute C_AXI_ARUSER_WIDTH of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 1;
  attribute C_AXI_AWUSER_WIDTH : integer;
  attribute C_AXI_AWUSER_WIDTH of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 1;
  attribute C_AXI_BUSER_WIDTH : integer;
  attribute C_AXI_BUSER_WIDTH of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 1;
  attribute C_AXI_DATA_WIDTH : integer;
  attribute C_AXI_DATA_WIDTH of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 32;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 12;
  attribute C_AXI_PROTOCOL : integer;
  attribute C_AXI_PROTOCOL of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 0;
  attribute C_AXI_RUSER_WIDTH : integer;
  attribute C_AXI_RUSER_WIDTH of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 1;
  attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
  attribute C_AXI_SUPPORTS_USER_SIGNALS of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 0;
  attribute C_AXI_WUSER_WIDTH : integer;
  attribute C_AXI_WUSER_WIDTH of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 1;
  attribute C_CONNECTIVITY_MODE : integer;
  attribute C_CONNECTIVITY_MODE of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 0;
  attribute C_DEBUG : integer;
  attribute C_DEBUG of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 1;
  attribute C_FAMILY : string;
  attribute C_FAMILY of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "zynq";
  attribute C_M_AXI_ADDR_WIDTH : string;
  attribute C_M_AXI_ADDR_WIDTH of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "96'b000000000000000000000000000011010000000000000000000000000000111100000000000000000000000000001111";
  attribute C_M_AXI_BASE_ADDR : string;
  attribute C_M_AXI_BASE_ADDR of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "192'b000000000000000000000000000000000100010000000000000000000000000000000000000000000000000000000000010000100000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
  attribute C_M_AXI_READ_CONNECTIVITY : string;
  attribute C_M_AXI_READ_CONNECTIVITY of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
  attribute C_M_AXI_READ_ISSUING : string;
  attribute C_M_AXI_READ_ISSUING of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
  attribute C_M_AXI_SECURE : string;
  attribute C_M_AXI_SECURE of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
  attribute C_M_AXI_WRITE_CONNECTIVITY : string;
  attribute C_M_AXI_WRITE_CONNECTIVITY of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
  attribute C_M_AXI_WRITE_ISSUING : string;
  attribute C_M_AXI_WRITE_ISSUING of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
  attribute C_NUM_ADDR_RANGES : integer;
  attribute C_NUM_ADDR_RANGES of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 1;
  attribute C_NUM_MASTER_SLOTS : integer;
  attribute C_NUM_MASTER_SLOTS of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 3;
  attribute C_NUM_SLAVE_SLOTS : integer;
  attribute C_NUM_SLAVE_SLOTS of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 1;
  attribute C_R_REGISTER : integer;
  attribute C_R_REGISTER of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 1;
  attribute C_S_AXI_ARB_PRIORITY : integer;
  attribute C_S_AXI_ARB_PRIORITY of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 0;
  attribute C_S_AXI_BASE_ID : integer;
  attribute C_S_AXI_BASE_ID of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 0;
  attribute C_S_AXI_READ_ACCEPTANCE : integer;
  attribute C_S_AXI_READ_ACCEPTANCE of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 1;
  attribute C_S_AXI_SINGLE_THREAD : integer;
  attribute C_S_AXI_SINGLE_THREAD of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 1;
  attribute C_S_AXI_THREAD_ID_WIDTH : integer;
  attribute C_S_AXI_THREAD_ID_WIDTH of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 12;
  attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
  attribute C_S_AXI_WRITE_ACCEPTANCE of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 1;
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "yes";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "axi_crossbar_v2_1_23_axi_crossbar";
  attribute P_ADDR_DECODE : integer;
  attribute P_ADDR_DECODE of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 1;
  attribute P_AXI3 : integer;
  attribute P_AXI3 of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 1;
  attribute P_AXI4 : integer;
  attribute P_AXI4 of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 0;
  attribute P_AXILITE : integer;
  attribute P_AXILITE of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 2;
  attribute P_AXILITE_SIZE : string;
  attribute P_AXILITE_SIZE of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "3'b010";
  attribute P_FAMILY : string;
  attribute P_FAMILY of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "zynq";
  attribute P_INCR : string;
  attribute P_INCR of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "2'b01";
  attribute P_LEN : integer;
  attribute P_LEN of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 8;
  attribute P_LOCK : integer;
  attribute P_LOCK of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 1;
  attribute P_M_AXI_ERR_MODE : string;
  attribute P_M_AXI_ERR_MODE of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
  attribute P_M_AXI_SUPPORTS_READ : string;
  attribute P_M_AXI_SUPPORTS_READ of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "3'b111";
  attribute P_M_AXI_SUPPORTS_WRITE : string;
  attribute P_M_AXI_SUPPORTS_WRITE of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "3'b111";
  attribute P_ONES : string;
  attribute P_ONES of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
  attribute P_RANGE_CHECK : integer;
  attribute P_RANGE_CHECK of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is 1;
  attribute P_S_AXI_BASE_ID : string;
  attribute P_S_AXI_BASE_ID of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute P_S_AXI_HIGH_ID : string;
  attribute P_S_AXI_HIGH_ID of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000111111111111";
  attribute P_S_AXI_SUPPORTS_READ : string;
  attribute P_S_AXI_SUPPORTS_READ of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "1'b1";
  attribute P_S_AXI_SUPPORTS_WRITE : string;
  attribute P_S_AXI_SUPPORTS_WRITE of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar : entity is "1'b1";
end blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar;

architecture STRUCTURE of blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar is
  signal \<const0>\ : STD_LOGIC;
  signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \^m_axi_arburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^m_axi_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^m_axi_arlock\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^m_axi_arqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^m_axi_arsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 95 downto 77 );
  signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 23 downto 16 );
  signal \^s_axi_rid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \^s_axi_wlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
  \^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
  \^s_axi_wlast\(0) <= s_axi_wlast(0);
  \^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
  m_axi_araddr(95 downto 77) <= \^m_axi_awaddr\(95 downto 77);
  m_axi_araddr(76 downto 64) <= \^m_axi_araddr\(12 downto 0);
  m_axi_araddr(63 downto 45) <= \^m_axi_awaddr\(95 downto 77);
  m_axi_araddr(44 downto 32) <= \^m_axi_araddr\(12 downto 0);
  m_axi_araddr(31 downto 13) <= \^m_axi_awaddr\(95 downto 77);
  m_axi_araddr(12 downto 0) <= \^m_axi_araddr\(12 downto 0);
  m_axi_arburst(5 downto 4) <= \^m_axi_arburst\(1 downto 0);
  m_axi_arburst(3 downto 2) <= \^m_axi_arburst\(1 downto 0);
  m_axi_arburst(1 downto 0) <= \^m_axi_arburst\(1 downto 0);
  m_axi_arcache(11 downto 8) <= \^m_axi_arcache\(3 downto 0);
  m_axi_arcache(7 downto 4) <= \^m_axi_arcache\(3 downto 0);
  m_axi_arcache(3 downto 0) <= \^m_axi_arcache\(3 downto 0);
  m_axi_arid(35) <= \<const0>\;
  m_axi_arid(34) <= \<const0>\;
  m_axi_arid(33) <= \<const0>\;
  m_axi_arid(32) <= \<const0>\;
  m_axi_arid(31) <= \<const0>\;
  m_axi_arid(30) <= \<const0>\;
  m_axi_arid(29) <= \<const0>\;
  m_axi_arid(28) <= \<const0>\;
  m_axi_arid(27) <= \<const0>\;
  m_axi_arid(26) <= \<const0>\;
  m_axi_arid(25) <= \<const0>\;
  m_axi_arid(24) <= \<const0>\;
  m_axi_arid(23) <= \<const0>\;
  m_axi_arid(22) <= \<const0>\;
  m_axi_arid(21) <= \<const0>\;
  m_axi_arid(20) <= \<const0>\;
  m_axi_arid(19) <= \<const0>\;
  m_axi_arid(18) <= \<const0>\;
  m_axi_arid(17) <= \<const0>\;
  m_axi_arid(16) <= \<const0>\;
  m_axi_arid(15) <= \<const0>\;
  m_axi_arid(14) <= \<const0>\;
  m_axi_arid(13) <= \<const0>\;
  m_axi_arid(12) <= \<const0>\;
  m_axi_arid(11) <= \<const0>\;
  m_axi_arid(10) <= \<const0>\;
  m_axi_arid(9) <= \<const0>\;
  m_axi_arid(8) <= \<const0>\;
  m_axi_arid(7) <= \<const0>\;
  m_axi_arid(6) <= \<const0>\;
  m_axi_arid(5) <= \<const0>\;
  m_axi_arid(4) <= \<const0>\;
  m_axi_arid(3) <= \<const0>\;
  m_axi_arid(2) <= \<const0>\;
  m_axi_arid(1) <= \<const0>\;
  m_axi_arid(0) <= \<const0>\;
  m_axi_arlen(23 downto 16) <= \^m_axi_awlen\(23 downto 16);
  m_axi_arlen(15 downto 8) <= \^m_axi_awlen\(23 downto 16);
  m_axi_arlen(7 downto 0) <= \^m_axi_awlen\(23 downto 16);
  m_axi_arlock(2) <= \^m_axi_arlock\(0);
  m_axi_arlock(1) <= \^m_axi_arlock\(0);
  m_axi_arlock(0) <= \^m_axi_arlock\(0);
  m_axi_arprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
  m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
  m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
  m_axi_arqos(11 downto 8) <= \^m_axi_arqos\(3 downto 0);
  m_axi_arqos(7 downto 4) <= \^m_axi_arqos\(3 downto 0);
  m_axi_arqos(3 downto 0) <= \^m_axi_arqos\(3 downto 0);
  m_axi_arregion(11) <= \<const0>\;
  m_axi_arregion(10) <= \<const0>\;
  m_axi_arregion(9) <= \<const0>\;
  m_axi_arregion(8) <= \<const0>\;
  m_axi_arregion(7) <= \<const0>\;
  m_axi_arregion(6) <= \<const0>\;
  m_axi_arregion(5) <= \<const0>\;
  m_axi_arregion(4) <= \<const0>\;
  m_axi_arregion(3) <= \<const0>\;
  m_axi_arregion(2) <= \<const0>\;
  m_axi_arregion(1) <= \<const0>\;
  m_axi_arregion(0) <= \<const0>\;
  m_axi_arsize(8 downto 6) <= \^m_axi_arsize\(2 downto 0);
  m_axi_arsize(5 downto 3) <= \^m_axi_arsize\(2 downto 0);
  m_axi_arsize(2 downto 0) <= \^m_axi_arsize\(2 downto 0);
  m_axi_aruser(2) <= \<const0>\;
  m_axi_aruser(1) <= \<const0>\;
  m_axi_aruser(0) <= \<const0>\;
  m_axi_awaddr(95 downto 77) <= \^m_axi_awaddr\(95 downto 77);
  m_axi_awaddr(76 downto 64) <= \^m_axi_araddr\(12 downto 0);
  m_axi_awaddr(63 downto 45) <= \^m_axi_awaddr\(95 downto 77);
  m_axi_awaddr(44 downto 32) <= \^m_axi_araddr\(12 downto 0);
  m_axi_awaddr(31 downto 13) <= \^m_axi_awaddr\(95 downto 77);
  m_axi_awaddr(12 downto 0) <= \^m_axi_araddr\(12 downto 0);
  m_axi_awburst(5 downto 4) <= \^m_axi_arburst\(1 downto 0);
  m_axi_awburst(3 downto 2) <= \^m_axi_arburst\(1 downto 0);
  m_axi_awburst(1 downto 0) <= \^m_axi_arburst\(1 downto 0);
  m_axi_awcache(11 downto 8) <= \^m_axi_arcache\(3 downto 0);
  m_axi_awcache(7 downto 4) <= \^m_axi_arcache\(3 downto 0);
  m_axi_awcache(3 downto 0) <= \^m_axi_arcache\(3 downto 0);
  m_axi_awid(35) <= \<const0>\;
  m_axi_awid(34) <= \<const0>\;
  m_axi_awid(33) <= \<const0>\;
  m_axi_awid(32) <= \<const0>\;
  m_axi_awid(31) <= \<const0>\;
  m_axi_awid(30) <= \<const0>\;
  m_axi_awid(29) <= \<const0>\;
  m_axi_awid(28) <= \<const0>\;
  m_axi_awid(27) <= \<const0>\;
  m_axi_awid(26) <= \<const0>\;
  m_axi_awid(25) <= \<const0>\;
  m_axi_awid(24) <= \<const0>\;
  m_axi_awid(23) <= \<const0>\;
  m_axi_awid(22) <= \<const0>\;
  m_axi_awid(21) <= \<const0>\;
  m_axi_awid(20) <= \<const0>\;
  m_axi_awid(19) <= \<const0>\;
  m_axi_awid(18) <= \<const0>\;
  m_axi_awid(17) <= \<const0>\;
  m_axi_awid(16) <= \<const0>\;
  m_axi_awid(15) <= \<const0>\;
  m_axi_awid(14) <= \<const0>\;
  m_axi_awid(13) <= \<const0>\;
  m_axi_awid(12) <= \<const0>\;
  m_axi_awid(11) <= \<const0>\;
  m_axi_awid(10) <= \<const0>\;
  m_axi_awid(9) <= \<const0>\;
  m_axi_awid(8) <= \<const0>\;
  m_axi_awid(7) <= \<const0>\;
  m_axi_awid(6) <= \<const0>\;
  m_axi_awid(5) <= \<const0>\;
  m_axi_awid(4) <= \<const0>\;
  m_axi_awid(3) <= \<const0>\;
  m_axi_awid(2) <= \<const0>\;
  m_axi_awid(1) <= \<const0>\;
  m_axi_awid(0) <= \<const0>\;
  m_axi_awlen(23 downto 16) <= \^m_axi_awlen\(23 downto 16);
  m_axi_awlen(15 downto 8) <= \^m_axi_awlen\(23 downto 16);
  m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(23 downto 16);
  m_axi_awlock(2) <= \^m_axi_arlock\(0);
  m_axi_awlock(1) <= \^m_axi_arlock\(0);
  m_axi_awlock(0) <= \^m_axi_arlock\(0);
  m_axi_awprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
  m_axi_awprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
  m_axi_awprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
  m_axi_awqos(11 downto 8) <= \^m_axi_arqos\(3 downto 0);
  m_axi_awqos(7 downto 4) <= \^m_axi_arqos\(3 downto 0);
  m_axi_awqos(3 downto 0) <= \^m_axi_arqos\(3 downto 0);
  m_axi_awregion(11) <= \<const0>\;
  m_axi_awregion(10) <= \<const0>\;
  m_axi_awregion(9) <= \<const0>\;
  m_axi_awregion(8) <= \<const0>\;
  m_axi_awregion(7) <= \<const0>\;
  m_axi_awregion(6) <= \<const0>\;
  m_axi_awregion(5) <= \<const0>\;
  m_axi_awregion(4) <= \<const0>\;
  m_axi_awregion(3) <= \<const0>\;
  m_axi_awregion(2) <= \<const0>\;
  m_axi_awregion(1) <= \<const0>\;
  m_axi_awregion(0) <= \<const0>\;
  m_axi_awsize(8 downto 6) <= \^m_axi_arsize\(2 downto 0);
  m_axi_awsize(5 downto 3) <= \^m_axi_arsize\(2 downto 0);
  m_axi_awsize(2 downto 0) <= \^m_axi_arsize\(2 downto 0);
  m_axi_awuser(2) <= \<const0>\;
  m_axi_awuser(1) <= \<const0>\;
  m_axi_awuser(0) <= \<const0>\;
  m_axi_wdata(95 downto 64) <= \^s_axi_wdata\(31 downto 0);
  m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
  m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
  m_axi_wid(35) <= \<const0>\;
  m_axi_wid(34) <= \<const0>\;
  m_axi_wid(33) <= \<const0>\;
  m_axi_wid(32) <= \<const0>\;
  m_axi_wid(31) <= \<const0>\;
  m_axi_wid(30) <= \<const0>\;
  m_axi_wid(29) <= \<const0>\;
  m_axi_wid(28) <= \<const0>\;
  m_axi_wid(27) <= \<const0>\;
  m_axi_wid(26) <= \<const0>\;
  m_axi_wid(25) <= \<const0>\;
  m_axi_wid(24) <= \<const0>\;
  m_axi_wid(23) <= \<const0>\;
  m_axi_wid(22) <= \<const0>\;
  m_axi_wid(21) <= \<const0>\;
  m_axi_wid(20) <= \<const0>\;
  m_axi_wid(19) <= \<const0>\;
  m_axi_wid(18) <= \<const0>\;
  m_axi_wid(17) <= \<const0>\;
  m_axi_wid(16) <= \<const0>\;
  m_axi_wid(15) <= \<const0>\;
  m_axi_wid(14) <= \<const0>\;
  m_axi_wid(13) <= \<const0>\;
  m_axi_wid(12) <= \<const0>\;
  m_axi_wid(11) <= \<const0>\;
  m_axi_wid(10) <= \<const0>\;
  m_axi_wid(9) <= \<const0>\;
  m_axi_wid(8) <= \<const0>\;
  m_axi_wid(7) <= \<const0>\;
  m_axi_wid(6) <= \<const0>\;
  m_axi_wid(5) <= \<const0>\;
  m_axi_wid(4) <= \<const0>\;
  m_axi_wid(3) <= \<const0>\;
  m_axi_wid(2) <= \<const0>\;
  m_axi_wid(1) <= \<const0>\;
  m_axi_wid(0) <= \<const0>\;
  m_axi_wlast(2) <= \^s_axi_wlast\(0);
  m_axi_wlast(1) <= \^s_axi_wlast\(0);
  m_axi_wlast(0) <= \^s_axi_wlast\(0);
  m_axi_wstrb(11 downto 8) <= \^s_axi_wstrb\(3 downto 0);
  m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
  m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
  m_axi_wuser(2) <= \<const0>\;
  m_axi_wuser(1) <= \<const0>\;
  m_axi_wuser(0) <= \<const0>\;
  s_axi_bid(11 downto 0) <= \^s_axi_rid\(11 downto 0);
  s_axi_buser(0) <= \<const0>\;
  s_axi_rid(11 downto 0) <= \^s_axi_rid\(11 downto 0);
  s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_sasd.crossbar_sasd_0\: entity work.blok_xbar_0_axi_crossbar_v2_1_23_crossbar_sasd
     port map (
      Q(68 downto 65) => \^m_axi_arqos\(3 downto 0),
      Q(64 downto 61) => \^m_axi_arcache\(3 downto 0),
      Q(60 downto 59) => \^m_axi_arburst\(1 downto 0),
      Q(58 downto 56) => \^m_axi_arprot\(2 downto 0),
      Q(55) => \^m_axi_arlock\(0),
      Q(54 downto 52) => \^m_axi_arsize\(2 downto 0),
      Q(51 downto 44) => \^m_axi_awlen\(23 downto 16),
      Q(43 downto 25) => \^m_axi_awaddr\(95 downto 77),
      Q(24 downto 12) => \^m_axi_araddr\(12 downto 0),
      Q(11 downto 0) => \^s_axi_rid\(11 downto 0),
      aclk => aclk,
      aresetn => aresetn,
      m_axi_arready(2 downto 0) => m_axi_arready(2 downto 0),
      m_axi_arvalid(2 downto 0) => m_axi_arvalid(2 downto 0),
      m_axi_awready(2 downto 0) => m_axi_awready(2 downto 0),
      m_axi_awvalid(2 downto 0) => m_axi_awvalid(2 downto 0),
      m_axi_bready(2 downto 0) => m_axi_bready(2 downto 0),
      m_axi_bresp(5 downto 0) => m_axi_bresp(5 downto 0),
      m_axi_bvalid(2 downto 0) => m_axi_bvalid(2 downto 0),
      m_axi_rdata(95 downto 0) => m_axi_rdata(95 downto 0),
      m_axi_rlast(2 downto 0) => m_axi_rlast(2 downto 0),
      m_axi_rready(2 downto 0) => m_axi_rready(2 downto 0),
      m_axi_rresp(5 downto 0) => m_axi_rresp(5 downto 0),
      m_axi_rvalid(2 downto 0) => m_axi_rvalid(2 downto 0),
      m_axi_wready(2 downto 0) => m_axi_wready(2 downto 0),
      m_axi_wvalid(2 downto 0) => m_axi_wvalid(2 downto 0),
      \m_payload_i_reg[34]\(34 downto 3) => s_axi_rdata(31 downto 0),
      \m_payload_i_reg[34]\(2 downto 1) => s_axi_rresp(1 downto 0),
      \m_payload_i_reg[34]\(0) => s_axi_rlast(0),
      s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
      s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
      s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
      s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
      s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
      s_axi_arlock(0) => s_axi_arlock(0),
      s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
      s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
      s_axi_arready(0) => s_axi_arready(0),
      s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
      s_axi_arvalid(0) => s_axi_arvalid(0),
      s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
      s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
      s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
      s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
      s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
      s_axi_awlock(0) => s_axi_awlock(0),
      s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
      s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
      s_axi_awready(0) => s_axi_awready(0),
      s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
      s_axi_awvalid(0) => s_axi_awvalid(0),
      s_axi_bready(0) => s_axi_bready(0),
      s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
      s_axi_bvalid(0) => s_axi_bvalid(0),
      s_axi_rready(0) => s_axi_rready(0),
      s_axi_rvalid(0) => s_axi_rvalid(0),
      s_axi_wlast(0) => \^s_axi_wlast\(0),
      s_axi_wready(0) => s_axi_wready(0),
      s_axi_wvalid(0) => s_axi_wvalid(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blok_xbar_0 is
  port (
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
    s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_awaddr : out STD_LOGIC_VECTOR ( 95 downto 0 );
    m_axi_awlen : out STD_LOGIC_VECTOR ( 23 downto 0 );
    m_axi_awsize : out STD_LOGIC_VECTOR ( 8 downto 0 );
    m_axi_awburst : out STD_LOGIC_VECTOR ( 5 downto 0 );
    m_axi_awlock : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awcache : out STD_LOGIC_VECTOR ( 11 downto 0 );
    m_axi_awprot : out STD_LOGIC_VECTOR ( 8 downto 0 );
    m_axi_awregion : out STD_LOGIC_VECTOR ( 11 downto 0 );
    m_axi_awqos : out STD_LOGIC_VECTOR ( 11 downto 0 );
    m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_wdata : out STD_LOGIC_VECTOR ( 95 downto 0 );
    m_axi_wstrb : out STD_LOGIC_VECTOR ( 11 downto 0 );
    m_axi_wlast : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_bresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
    m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_araddr : out STD_LOGIC_VECTOR ( 95 downto 0 );
    m_axi_arlen : out STD_LOGIC_VECTOR ( 23 downto 0 );
    m_axi_arsize : out STD_LOGIC_VECTOR ( 8 downto 0 );
    m_axi_arburst : out STD_LOGIC_VECTOR ( 5 downto 0 );
    m_axi_arlock : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arcache : out STD_LOGIC_VECTOR ( 11 downto 0 );
    m_axi_arprot : out STD_LOGIC_VECTOR ( 8 downto 0 );
    m_axi_arregion : out STD_LOGIC_VECTOR ( 11 downto 0 );
    m_axi_arqos : out STD_LOGIC_VECTOR ( 11 downto 0 );
    m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 );
    m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
    m_axi_rlast : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of blok_xbar_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of blok_xbar_0 : entity is "blok_xbar_0,axi_crossbar_v2_1_23_axi_crossbar,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of blok_xbar_0 : entity is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of blok_xbar_0 : entity is "axi_crossbar_v2_1_23_axi_crossbar,Vivado 2020.2";
end blok_xbar_0;

architecture STRUCTURE of blok_xbar_0 is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 35 downto 0 );
  signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 35 downto 0 );
  signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 35 downto 0 );
  signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute C_AXI_ADDR_WIDTH : integer;
  attribute C_AXI_ADDR_WIDTH of inst : label is 32;
  attribute C_AXI_ARUSER_WIDTH : integer;
  attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
  attribute C_AXI_AWUSER_WIDTH : integer;
  attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
  attribute C_AXI_BUSER_WIDTH : integer;
  attribute C_AXI_BUSER_WIDTH of inst : label is 1;
  attribute C_AXI_DATA_WIDTH : integer;
  attribute C_AXI_DATA_WIDTH of inst : label is 32;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of inst : label is 12;
  attribute C_AXI_PROTOCOL : integer;
  attribute C_AXI_PROTOCOL of inst : label is 0;
  attribute C_AXI_RUSER_WIDTH : integer;
  attribute C_AXI_RUSER_WIDTH of inst : label is 1;
  attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
  attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
  attribute C_AXI_WUSER_WIDTH : integer;
  attribute C_AXI_WUSER_WIDTH of inst : label is 1;
  attribute C_CONNECTIVITY_MODE : integer;
  attribute C_CONNECTIVITY_MODE of inst : label is 0;
  attribute C_DEBUG : integer;
  attribute C_DEBUG of inst : label is 1;
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynq";
  attribute C_M_AXI_ADDR_WIDTH : string;
  attribute C_M_AXI_ADDR_WIDTH of inst : label is "96'b000000000000000000000000000011010000000000000000000000000000111100000000000000000000000000001111";
  attribute C_M_AXI_BASE_ADDR : string;
  attribute C_M_AXI_BASE_ADDR of inst : label is "192'b000000000000000000000000000000000100010000000000000000000000000000000000000000000000000000000000010000100000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
  attribute C_M_AXI_READ_CONNECTIVITY : string;
  attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
  attribute C_M_AXI_READ_ISSUING : string;
  attribute C_M_AXI_READ_ISSUING of inst : label is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
  attribute C_M_AXI_SECURE : string;
  attribute C_M_AXI_SECURE of inst : label is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
  attribute C_M_AXI_WRITE_CONNECTIVITY : string;
  attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
  attribute C_M_AXI_WRITE_ISSUING : string;
  attribute C_M_AXI_WRITE_ISSUING of inst : label is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
  attribute C_NUM_ADDR_RANGES : integer;
  attribute C_NUM_ADDR_RANGES of inst : label is 1;
  attribute C_NUM_MASTER_SLOTS : integer;
  attribute C_NUM_MASTER_SLOTS of inst : label is 3;
  attribute C_NUM_SLAVE_SLOTS : integer;
  attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
  attribute C_R_REGISTER : integer;
  attribute C_R_REGISTER of inst : label is 1;
  attribute C_S_AXI_ARB_PRIORITY : integer;
  attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
  attribute C_S_AXI_BASE_ID : integer;
  attribute C_S_AXI_BASE_ID of inst : label is 0;
  attribute C_S_AXI_READ_ACCEPTANCE : integer;
  attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 1;
  attribute C_S_AXI_SINGLE_THREAD : integer;
  attribute C_S_AXI_SINGLE_THREAD of inst : label is 1;
  attribute C_S_AXI_THREAD_ID_WIDTH : integer;
  attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 12;
  attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
  attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 1;
  attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
  attribute P_ADDR_DECODE : integer;
  attribute P_ADDR_DECODE of inst : label is 1;
  attribute P_AXI3 : integer;
  attribute P_AXI3 of inst : label is 1;
  attribute P_AXI4 : integer;
  attribute P_AXI4 of inst : label is 0;
  attribute P_AXILITE : integer;
  attribute P_AXILITE of inst : label is 2;
  attribute P_AXILITE_SIZE : string;
  attribute P_AXILITE_SIZE of inst : label is "3'b010";
  attribute P_FAMILY : string;
  attribute P_FAMILY of inst : label is "zynq";
  attribute P_INCR : string;
  attribute P_INCR of inst : label is "2'b01";
  attribute P_LEN : integer;
  attribute P_LEN of inst : label is 8;
  attribute P_LOCK : integer;
  attribute P_LOCK of inst : label is 1;
  attribute P_M_AXI_ERR_MODE : string;
  attribute P_M_AXI_ERR_MODE of inst : label is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
  attribute P_M_AXI_SUPPORTS_READ : string;
  attribute P_M_AXI_SUPPORTS_READ of inst : label is "3'b111";
  attribute P_M_AXI_SUPPORTS_WRITE : string;
  attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "3'b111";
  attribute P_ONES : string;
  attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
  attribute P_RANGE_CHECK : integer;
  attribute P_RANGE_CHECK of inst : label is 1;
  attribute P_S_AXI_BASE_ID : string;
  attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute P_S_AXI_HIGH_ID : string;
  attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000111111111111";
  attribute P_S_AXI_SUPPORTS_READ : string;
  attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
  attribute P_S_AXI_SUPPORTS_WRITE : string;
  attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLKIF CLK";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLKIF, FREQ_HZ 50000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN blok_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RSTIF RST";
  attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT";
  attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]";
  attribute X_INTERFACE_INFO of m_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI ARBURST [1:0] [5:4]";
  attribute X_INTERFACE_INFO of m_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE [3:0] [11:8]";
  attribute X_INTERFACE_INFO of m_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI ARLEN [7:0] [23:16]";
  attribute X_INTERFACE_INFO of m_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK [0:0] [2:2]";
  attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]";
  attribute X_INTERFACE_INFO of m_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARQOS [3:0] [11:8]";
  attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]";
  attribute X_INTERFACE_INFO of m_axi_arregion : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARREGION [3:0] [11:8]";
  attribute X_INTERFACE_INFO of m_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE [2:0] [8:6]";
  attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]";
  attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]";
  attribute X_INTERFACE_INFO of m_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI AWBURST [1:0] [5:4]";
  attribute X_INTERFACE_INFO of m_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE [3:0] [11:8]";
  attribute X_INTERFACE_INFO of m_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI AWLEN [7:0] [23:16]";
  attribute X_INTERFACE_INFO of m_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK [0:0] [2:2]";
  attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]";
  attribute X_INTERFACE_INFO of m_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWQOS [3:0] [11:8]";
  attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]";
  attribute X_INTERFACE_INFO of m_axi_awregion : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWREGION [3:0] [11:8]";
  attribute X_INTERFACE_INFO of m_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE [2:0] [8:6]";
  attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]";
  attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]";
  attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]";
  attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]";
  attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]";
  attribute X_INTERFACE_INFO of m_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RLAST [0:0] [2:2]";
  attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]";
  attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN blok_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN blok_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN blok_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]";
  attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]";
  attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]";
  attribute X_INTERFACE_INFO of m_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WLAST [0:0] [2:2]";
  attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]";
  attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]";
  attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]";
  attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
  attribute X_INTERFACE_INFO of s_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST";
  attribute X_INTERFACE_INFO of s_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE";
  attribute X_INTERFACE_INFO of s_axi_arid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARID";
  attribute X_INTERFACE_INFO of s_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN";
  attribute X_INTERFACE_INFO of s_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK";
  attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
  attribute X_INTERFACE_INFO of s_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS";
  attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
  attribute X_INTERFACE_INFO of s_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE";
  attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
  attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
  attribute X_INTERFACE_INFO of s_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST";
  attribute X_INTERFACE_INFO of s_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE";
  attribute X_INTERFACE_INFO of s_axi_awid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWID";
  attribute X_INTERFACE_INFO of s_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN";
  attribute X_INTERFACE_INFO of s_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK";
  attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
  attribute X_INTERFACE_INFO of s_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS";
  attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
  attribute X_INTERFACE_INFO of s_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE";
  attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
  attribute X_INTERFACE_INFO of s_axi_bid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BID";
  attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
  attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
  attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
  attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
  attribute X_INTERFACE_INFO of s_axi_rid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RID";
  attribute X_INTERFACE_INFO of s_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RLAST";
  attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
  attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN blok_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
  attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
  attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
  attribute X_INTERFACE_INFO of s_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WLAST";
  attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
  attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
  attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
begin
  m_axi_arregion(11) <= \<const0>\;
  m_axi_arregion(10) <= \<const0>\;
  m_axi_arregion(9) <= \<const0>\;
  m_axi_arregion(8) <= \<const0>\;
  m_axi_arregion(7) <= \<const0>\;
  m_axi_arregion(6) <= \<const0>\;
  m_axi_arregion(5) <= \<const0>\;
  m_axi_arregion(4) <= \<const0>\;
  m_axi_arregion(3) <= \<const0>\;
  m_axi_arregion(2) <= \<const0>\;
  m_axi_arregion(1) <= \<const0>\;
  m_axi_arregion(0) <= \<const0>\;
  m_axi_awregion(11) <= \<const0>\;
  m_axi_awregion(10) <= \<const0>\;
  m_axi_awregion(9) <= \<const0>\;
  m_axi_awregion(8) <= \<const0>\;
  m_axi_awregion(7) <= \<const0>\;
  m_axi_awregion(6) <= \<const0>\;
  m_axi_awregion(5) <= \<const0>\;
  m_axi_awregion(4) <= \<const0>\;
  m_axi_awregion(3) <= \<const0>\;
  m_axi_awregion(2) <= \<const0>\;
  m_axi_awregion(1) <= \<const0>\;
  m_axi_awregion(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
inst: entity work.blok_xbar_0_axi_crossbar_v2_1_23_axi_crossbar
     port map (
      aclk => aclk,
      aresetn => aresetn,
      m_axi_araddr(95 downto 0) => m_axi_araddr(95 downto 0),
      m_axi_arburst(5 downto 0) => m_axi_arburst(5 downto 0),
      m_axi_arcache(11 downto 0) => m_axi_arcache(11 downto 0),
      m_axi_arid(35 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(35 downto 0),
      m_axi_arlen(23 downto 0) => m_axi_arlen(23 downto 0),
      m_axi_arlock(2 downto 0) => m_axi_arlock(2 downto 0),
      m_axi_arprot(8 downto 0) => m_axi_arprot(8 downto 0),
      m_axi_arqos(11 downto 0) => m_axi_arqos(11 downto 0),
      m_axi_arready(2 downto 0) => m_axi_arready(2 downto 0),
      m_axi_arregion(11 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(11 downto 0),
      m_axi_arsize(8 downto 0) => m_axi_arsize(8 downto 0),
      m_axi_aruser(2 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(2 downto 0),
      m_axi_arvalid(2 downto 0) => m_axi_arvalid(2 downto 0),
      m_axi_awaddr(95 downto 0) => m_axi_awaddr(95 downto 0),
      m_axi_awburst(5 downto 0) => m_axi_awburst(5 downto 0),
      m_axi_awcache(11 downto 0) => m_axi_awcache(11 downto 0),
      m_axi_awid(35 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(35 downto 0),
      m_axi_awlen(23 downto 0) => m_axi_awlen(23 downto 0),
      m_axi_awlock(2 downto 0) => m_axi_awlock(2 downto 0),
      m_axi_awprot(8 downto 0) => m_axi_awprot(8 downto 0),
      m_axi_awqos(11 downto 0) => m_axi_awqos(11 downto 0),
      m_axi_awready(2 downto 0) => m_axi_awready(2 downto 0),
      m_axi_awregion(11 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(11 downto 0),
      m_axi_awsize(8 downto 0) => m_axi_awsize(8 downto 0),
      m_axi_awuser(2 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(2 downto 0),
      m_axi_awvalid(2 downto 0) => m_axi_awvalid(2 downto 0),
      m_axi_bid(35 downto 0) => B"000000000000000000000000000000000000",
      m_axi_bready(2 downto 0) => m_axi_bready(2 downto 0),
      m_axi_bresp(5 downto 0) => m_axi_bresp(5 downto 0),
      m_axi_buser(2 downto 0) => B"000",
      m_axi_bvalid(2 downto 0) => m_axi_bvalid(2 downto 0),
      m_axi_rdata(95 downto 0) => m_axi_rdata(95 downto 0),
      m_axi_rid(35 downto 0) => B"000000000000000000000000000000000000",
      m_axi_rlast(2 downto 0) => m_axi_rlast(2 downto 0),
      m_axi_rready(2 downto 0) => m_axi_rready(2 downto 0),
      m_axi_rresp(5 downto 0) => m_axi_rresp(5 downto 0),
      m_axi_ruser(2 downto 0) => B"000",
      m_axi_rvalid(2 downto 0) => m_axi_rvalid(2 downto 0),
      m_axi_wdata(95 downto 0) => m_axi_wdata(95 downto 0),
      m_axi_wid(35 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(35 downto 0),
      m_axi_wlast(2 downto 0) => m_axi_wlast(2 downto 0),
      m_axi_wready(2 downto 0) => m_axi_wready(2 downto 0),
      m_axi_wstrb(11 downto 0) => m_axi_wstrb(11 downto 0),
      m_axi_wuser(2 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(2 downto 0),
      m_axi_wvalid(2 downto 0) => m_axi_wvalid(2 downto 0),
      s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
      s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
      s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
      s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
      s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
      s_axi_arlock(0) => s_axi_arlock(0),
      s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
      s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
      s_axi_arready(0) => s_axi_arready(0),
      s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
      s_axi_aruser(0) => '0',
      s_axi_arvalid(0) => s_axi_arvalid(0),
      s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
      s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
      s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
      s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
      s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
      s_axi_awlock(0) => s_axi_awlock(0),
      s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
      s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
      s_axi_awready(0) => s_axi_awready(0),
      s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
      s_axi_awuser(0) => '0',
      s_axi_awvalid(0) => s_axi_awvalid(0),
      s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
      s_axi_bready(0) => s_axi_bready(0),
      s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
      s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
      s_axi_bvalid(0) => s_axi_bvalid(0),
      s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
      s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
      s_axi_rlast(0) => s_axi_rlast(0),
      s_axi_rready(0) => s_axi_rready(0),
      s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
      s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
      s_axi_rvalid(0) => s_axi_rvalid(0),
      s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
      s_axi_wid(11 downto 0) => B"000000000000",
      s_axi_wlast(0) => s_axi_wlast(0),
      s_axi_wready(0) => s_axi_wready(0),
      s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
      s_axi_wuser(0) => '0',
      s_axi_wvalid(0) => s_axi_wvalid(0)
    );
end STRUCTURE;
