-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
-- Date        : Fri May 14 19:52:47 2021
-- Host        : zz-Latitude-7490 running 64-bit Ubuntu 20.04.2 LTS
-- Command     : write_vhdl -force -mode funcsim
--               /home/zz/phpix/phpix-vivado-peta/hw_linux/clean_hw/clean_hw.gen/sources_1/bd/blok/ip/blok_controller_0_0/blok_controller_0_0_sim_netlist.vhdl
-- Design      : blok_controller_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blok_controller_0_0_LFSR_convert_LUT is
  port (
    Q : out STD_LOGIC_VECTOR ( 12 downto 0 );
    ena : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 12 downto 0 );
    ctl_clk_i : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of blok_controller_0_0_LFSR_convert_LUT : entity is "LFSR_convert_LUT";
end blok_controller_0_0_LFSR_convert_LUT;

architecture STRUCTURE of blok_controller_0_0_LFSR_convert_LUT is
begin
\LFSR_in_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => D(0),
      Q => Q(0),
      R => '0'
    );
\LFSR_in_i_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => D(10),
      Q => Q(10),
      R => '0'
    );
\LFSR_in_i_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => D(11),
      Q => Q(11),
      R => '0'
    );
\LFSR_in_i_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => D(12),
      Q => Q(12),
      R => '0'
    );
\LFSR_in_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => D(1),
      Q => Q(1),
      R => '0'
    );
\LFSR_in_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => D(2),
      Q => Q(2),
      R => '0'
    );
\LFSR_in_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => D(3),
      Q => Q(3),
      R => '0'
    );
\LFSR_in_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => D(4),
      Q => Q(4),
      R => '0'
    );
\LFSR_in_i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => D(5),
      Q => Q(5),
      R => '0'
    );
\LFSR_in_i_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => D(6),
      Q => Q(6),
      R => '0'
    );
\LFSR_in_i_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => D(7),
      Q => Q(7),
      R => '0'
    );
\LFSR_in_i_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => D(8),
      Q => Q(8),
      R => '0'
    );
\LFSR_in_i_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => D(9),
      Q => Q(9),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blok_controller_0_0_LFSR_convert_LUT_0 is
  port (
    D : out STD_LOGIC_VECTOR ( 25 downto 0 );
    \writer_state__0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \datmem_data_o_reg[28]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
    \LFSR_in_i_reg[12]_0\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
    ena : in STD_LOGIC;
    ctl_clk_i : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 12 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of blok_controller_0_0_LFSR_convert_LUT_0 : entity is "LFSR_convert_LUT";
end blok_controller_0_0_LFSR_convert_LUT_0;

architecture STRUCTURE of blok_controller_0_0_LFSR_convert_LUT_0 is
  signal BIN_out : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal BIN_out_i_reg : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \LFSR_in_i_reg_n_0_[0]\ : STD_LOGIC;
  signal \LFSR_in_i_reg_n_0_[10]\ : STD_LOGIC;
  signal \LFSR_in_i_reg_n_0_[11]\ : STD_LOGIC;
  signal \LFSR_in_i_reg_n_0_[12]\ : STD_LOGIC;
  signal \LFSR_in_i_reg_n_0_[1]\ : STD_LOGIC;
  signal \LFSR_in_i_reg_n_0_[2]\ : STD_LOGIC;
  signal \LFSR_in_i_reg_n_0_[3]\ : STD_LOGIC;
  signal \LFSR_in_i_reg_n_0_[4]\ : STD_LOGIC;
  signal \LFSR_in_i_reg_n_0_[5]\ : STD_LOGIC;
  signal \LFSR_in_i_reg_n_0_[6]\ : STD_LOGIC;
  signal \LFSR_in_i_reg_n_0_[7]\ : STD_LOGIC;
  signal \LFSR_in_i_reg_n_0_[8]\ : STD_LOGIC;
  signal \LFSR_in_i_reg_n_0_[9]\ : STD_LOGIC;
  signal NLW_BIN_out_i_reg_0_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_0_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_0_DBITERR_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_0_INJECTDBITERR_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_0_INJECTSBITERR_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_0_SBITERR_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_0_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 4 );
  signal NLW_BIN_out_i_reg_0_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 4 );
  signal NLW_BIN_out_i_reg_0_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_BIN_out_i_reg_0_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_BIN_out_i_reg_0_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_BIN_out_i_reg_0_RDADDRECC_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_BIN_out_i_reg_1_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_1_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_1_DBITERR_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_1_INJECTDBITERR_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_1_INJECTSBITERR_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_1_SBITERR_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_1_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 4 );
  signal NLW_BIN_out_i_reg_1_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 4 );
  signal NLW_BIN_out_i_reg_1_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_BIN_out_i_reg_1_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_BIN_out_i_reg_1_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_BIN_out_i_reg_1_RDADDRECC_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_BIN_out_i_reg_2_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_2_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_2_DBITERR_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_2_INJECTDBITERR_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_2_INJECTSBITERR_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_2_SBITERR_UNCONNECTED : STD_LOGIC;
  signal NLW_BIN_out_i_reg_2_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 4 );
  signal NLW_BIN_out_i_reg_2_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 4 );
  signal NLW_BIN_out_i_reg_2_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_BIN_out_i_reg_2_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_BIN_out_i_reg_2_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_BIN_out_i_reg_2_RDADDRECC_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_BIN_out_i_reg_3_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 1 );
  signal NLW_BIN_out_i_reg_3_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 1 );
  signal NLW_BIN_out_i_reg_3_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_BIN_out_i_reg_3_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
  attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of BIN_out_i_reg_0 : label is "p0_d4";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of BIN_out_i_reg_0 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of BIN_out_i_reg_0 : label is 106496;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of BIN_out_i_reg_0 : label is "lfsr_decoder_l/BIN_out_i";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of BIN_out_i_reg_0 : label is "RAM_SP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of BIN_out_i_reg_0 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of BIN_out_i_reg_0 : label is 8191;
  attribute ram_offset : integer;
  attribute ram_offset of BIN_out_i_reg_0 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of BIN_out_i_reg_0 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of BIN_out_i_reg_0 : label is 3;
  attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of BIN_out_i_reg_1 : label is "p0_d4";
  attribute METHODOLOGY_DRC_VIOS of BIN_out_i_reg_1 : label is "";
  attribute RTL_RAM_BITS of BIN_out_i_reg_1 : label is 106496;
  attribute RTL_RAM_NAME of BIN_out_i_reg_1 : label is "lfsr_decoder_l/BIN_out_i";
  attribute RTL_RAM_TYPE of BIN_out_i_reg_1 : label is "RAM_SP";
  attribute ram_addr_begin of BIN_out_i_reg_1 : label is 0;
  attribute ram_addr_end of BIN_out_i_reg_1 : label is 8191;
  attribute ram_offset of BIN_out_i_reg_1 : label is 0;
  attribute ram_slice_begin of BIN_out_i_reg_1 : label is 4;
  attribute ram_slice_end of BIN_out_i_reg_1 : label is 7;
  attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of BIN_out_i_reg_2 : label is "p0_d4";
  attribute METHODOLOGY_DRC_VIOS of BIN_out_i_reg_2 : label is "";
  attribute RTL_RAM_BITS of BIN_out_i_reg_2 : label is 106496;
  attribute RTL_RAM_NAME of BIN_out_i_reg_2 : label is "lfsr_decoder_l/BIN_out_i";
  attribute RTL_RAM_TYPE of BIN_out_i_reg_2 : label is "RAM_SP";
  attribute ram_addr_begin of BIN_out_i_reg_2 : label is 0;
  attribute ram_addr_end of BIN_out_i_reg_2 : label is 8191;
  attribute ram_offset of BIN_out_i_reg_2 : label is 0;
  attribute ram_slice_begin of BIN_out_i_reg_2 : label is 8;
  attribute ram_slice_end of BIN_out_i_reg_2 : label is 11;
  attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of BIN_out_i_reg_3 : label is "p0_d1";
  attribute METHODOLOGY_DRC_VIOS of BIN_out_i_reg_3 : label is "";
  attribute RTL_RAM_BITS of BIN_out_i_reg_3 : label is 106496;
  attribute RTL_RAM_NAME of BIN_out_i_reg_3 : label is "lfsr_decoder_l/BIN_out_i";
  attribute RTL_RAM_TYPE of BIN_out_i_reg_3 : label is "RAM_SP";
  attribute ram_addr_begin of BIN_out_i_reg_3 : label is 0;
  attribute ram_addr_end of BIN_out_i_reg_3 : label is 8191;
  attribute ram_offset of BIN_out_i_reg_3 : label is 0;
  attribute ram_slice_begin of BIN_out_i_reg_3 : label is 12;
  attribute ram_slice_end of BIN_out_i_reg_3 : label is 12;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \datmem_data_o[0]_i_1\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \datmem_data_o[10]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \datmem_data_o[11]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \datmem_data_o[12]_i_1\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \datmem_data_o[16]_i_1\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \datmem_data_o[17]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \datmem_data_o[18]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \datmem_data_o[19]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \datmem_data_o[1]_i_1\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \datmem_data_o[20]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \datmem_data_o[21]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \datmem_data_o[22]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \datmem_data_o[23]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \datmem_data_o[24]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \datmem_data_o[25]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \datmem_data_o[26]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \datmem_data_o[27]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \datmem_data_o[28]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \datmem_data_o[2]_i_1\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \datmem_data_o[3]_i_1\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \datmem_data_o[4]_i_1\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \datmem_data_o[5]_i_1\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \datmem_data_o[6]_i_1\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \datmem_data_o[7]_i_1\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \datmem_data_o[8]_i_1\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \datmem_data_o[9]_i_1\ : label is "soft_lutpair8";
begin
BIN_out_i_reg_0: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 1,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"A078117059CE162FFA653EECE05DC5C3F70F8D5E94DBFC426ECD3AB1DC90BFEF",
      INIT_01 => X"1B01C8F932E2D8D1267ADDBF8297A300A0FBF726A4EF0FAD5FE1464E4D864D84",
      INIT_02 => X"FBA190CC4F4863076B450F507170DB1EC610DF1225A7A56F159EC9F7E55EC9E5",
      INIT_03 => X"C29C41824DD9801A24F30FB3CE49AE72E327284BCE0ECC2059F32A28DB245161",
      INIT_04 => X"FDD79251FE7032F31396DB98FB865750B2868A1F7D5AE0C8FF26564F6D0A6F96",
      INIT_05 => X"EF1C8B922A910D2DE5FF15A9F71441B8E7FCF5C6C1003631F8F2E8B1AE3C42DF",
      INIT_06 => X"7FC473F8A38945DCCDBFE17FEDADA391769AC034636BE3F92E8C63B51692C7F2",
      INIT_07 => X"4DD33AAD1592B943555EEE4A49B1E2AB13257F141140DC04BD6F954A7BCF08F3",
      INIT_08 => X"6CB329B729FB0220883E061BBFB17DB960D0B3F7568715D0470E81DBB7E03A17",
      INIT_09 => X"106EFEF8AAA3E612DF5FF831F4B3F0E4C2641AF73EDC9A99A06C195766E8F6F1",
      INIT_0A => X"3FC8304DD0C6CD57BDA201A174277442B04990536F599CF27B1F84FDF593FE10",
      INIT_0B => X"DFBF42CD899C8A9373EBFAC2D18E734E5F96C07F1216AB8AB048D22595326C59",
      INIT_0C => X"28F7BA4B3DC1A4C5B754F76C5F34408AA32F296DF7E4ACD6E2273A43FD487FC3",
      INIT_0D => X"C8B07D656864E0F95B74D9DA05262E8D5DCEECF02F12C8F0DF6E3BFEBB144AD2",
      INIT_0E => X"E2F47366D8DF82C5F21255D17E2D91157C8E47F08AD6F5DB886C7DB0E1896FB4",
      INIT_0F => X"E52EFEA4641B0B6EF2D6AA03DC2A55C4C6B686FFCF5F05CB054A3C72FF13ABDC",
      INIT_10 => X"7117ED1FCA460C8F6F78908A2C62E9165E841FF39D2EE3CBCA8DF7154FB9218B",
      INIT_11 => X"73D9C94A39AECA883CA5FCCA19353A19969145F212712CCECE0BC62C8FE8CAAE",
      INIT_12 => X"DB3F785520BD0A8646F2EDDDA6B5A8A4B91479D923A162857576FB9BFF730828",
      INIT_13 => X"25127AFE0EF5019CBFBFB644F2762E37EBF6640A0796492C0255C3400C11FE5C",
      INIT_14 => X"CC185BADA0186A497F0F63AEA0D106388FC1210D9F5C01EB0163AA4DFAF42917",
      INIT_15 => X"430CD497431256E9E01BD672D8E26685C9EFBC311327B920865831808F545630",
      INIT_16 => X"600AAA75D5138FF320352D7EBAC096B0C4115993E63B3C6DA964433B78D864A9",
      INIT_17 => X"EE04C0F05A3ADDEE9AACAFD69ABAAB428A40FCCA03BED43BEE2498F884415AF8",
      INIT_18 => X"B64F310339AF7BEF0B89FC54BBDDEC74FA353A824DBA59410CEE5C9889F0DF4F",
      INIT_19 => X"359DFF83C1B750C549EBDC28B855D868CF84695F028D7FD6620F495758129CB3",
      INIT_1A => X"6DECD1F3F2D6F11A3906203CD69C0C19E80E76F74ACB0FFCCCCD2C5554B2E13F",
      INIT_1B => X"DA94C8118BE6766E7E9F7D5FF41D0FA960CF8259E4A9EBB71B653F733DFF9DED",
      INIT_1C => X"84DD99F25B830F1595BFE47A0664E1C9979270D580E6C711FC2299A679F7C55A",
      INIT_1D => X"FE3B005E8C487572E59AE5FE9736DF620E3A2F3E6160E72981F03BE7AF232267",
      INIT_1E => X"D27FCF7398770D01D5066302116ED9C812655CB34FDA8A34070D274CB4CFEEDF",
      INIT_1F => X"FD6E37F507FFBF58705129C415C471F5F937ED7AB5B9124DE0D131B26968D851",
      INIT_20 => X"76BFF92502E0D0048A2E235FFF847D3CEDCB597ED0C8C26655A04C3AE3B2A97C",
      INIT_21 => X"B87232980F2E42AFAD6B9587714D697FF770D8F9DAE1D91BB35D77636F3A02E7",
      INIT_22 => X"9A77CA6275F62013A2A38802233DFD7F4D8F319C4DB743CD99F01F99BD6BEBCF",
      INIT_23 => X"08F4BE0A9D3A25FBD4BAFB0F6DBB4969944D5B06AFFD4DFBF2AA341604CB022A",
      INIT_24 => X"0C3AD245484A3EFAD3B40B3227F3491678C63837F0FC9A6C5F4F680421C9B379",
      INIT_25 => X"2E8CA480E8C926F683113CEEF19B2967A5079003FF5E6E2E6B67DCF6FBA91B25",
      INIT_26 => X"2F4CDFB7D77531FBA1484AA7C59AB30DB15396362DB4D501D1DD72B2308FC6ED",
      INIT_27 => X"C3D6F223587BF06FD15F40C63182BAFD9C608C408CE7E515B013D827034F0458",
      INIT_28 => X"E970BD427382F1EE7A50860D21227F9C91E28754DBBB954E5FEB60D5C3BA32C8",
      INIT_29 => X"AD3DB219766C9BEE0BB182A9970BB51A08C061D087F44BDFEB21BE0251D73409",
      INIT_2A => X"9DBA4F6F4C9D6472722453486CCAA3518957E679E462C931C95F560576B734A1",
      INIT_2B => X"B5B4F17DDEC5CA3865A412D38627FFDA6F61E24CBEC7F8838EF96FA397174916",
      INIT_2C => X"AD8502F216CABA648FA7145CC45D577EBB3A9755357494BC68F9BEE937158BCA",
      INIT_2D => X"8771113B8B6B38560ED6426469C0EF44D3410416E32E989F1CFBADA1AAC75CB1",
      INIT_2E => X"898B7511C0BD6D9B31744C5FFEB5540CAFFF83354AA99069F9F51572F68BC0C9",
      INIT_2F => X"DF5F71A5DD316F21169B341B9E2EFF6FFA3B0B2DEB5F7E87EADBCC0B5BACA553",
      INIT_30 => X"08BB4A6D41B79B395DE1C0B160A25B2315D7F9F263DAA7999AA7FD11EE095C08",
      INIT_31 => X"CD725D0745261C434BAFB90187C1F70415C497A309D4665FCBCCE6EFFDD48E50",
      INIT_32 => X"DAF891577CA36901133396E38703EE767E3B160B57A56F8567972937A9D6C04E",
      INIT_33 => X"4C6EAFE5FA06974BD22CC48F6F1ED46253ACF8CAEED93C9ECD956C69E899769C",
      INIT_34 => X"F39F1EF28F7D0D8B5CB3DFCF1C0E03D4DCD3DCEF3ED469696754CE3BFD204304",
      INIT_35 => X"7FE3F5D2E62D03490231E678F32428B940AA157E341240D7EB7EAADD1BD621A9",
      INIT_36 => X"721ED00C9F3E68A2F656B4A6F8C1C68128CF7B694E03824B40E10FFDA6E0F6E5",
      INIT_37 => X"EAB3A95AD99F232593C2F37485757DF18AFAAD0088E76DF305552AE3170DB8AF",
      INIT_38 => X"AF8CAB348119E76A9317F773D986242001D7383EAAABBD7B8EA1F28DDE616BB2",
      INIT_39 => X"9C5CE1E3A1AD01386AC7954815FE2768A66ACC05FC528BBD1B7E7251F82ADBA6",
      INIT_3A => X"15F943BB390F46FB762B7E11F78E31AA912D00194DC2F780B706364F32317E86",
      INIT_3B => X"0AFD4BCB1A126DFD99DD5792836A833DFE61A2BDFD6AFFF0A8814F73EB087D33",
      INIT_3C => X"203A7C6B6FD5CD485E01EEBA92BE4D5817831DEA3C815ED0CC51D7F2F7FDE504",
      INIT_3D => X"E1358C0CD5FD8D46A29E8D8F14E01F25E0651D7277411F36292670FAEAA6D997",
      INIT_3E => X"F3A84880FBE88DBCC56FC6AC23395DE2FB10E025442AC03671AF7195E8996128",
      INIT_3F => X"0FE471F14783016D198E030ECC0F67968F136F2D35A6D35C2861DF58842F036D",
      INIT_40 => X"0FBE2DCC16CA789F9EF19DF94D33373796064B01E52DD4BBEF748CE35B2AC8AD",
      INIT_41 => X"B8373C701FFAB396D113BFB14E11C145F98B335F53F466C0B0C0199508BED4BD",
      INIT_42 => X"D07818F1DE09E03ADEEBBF22EEDA923CEC84F62E08C8E744A77064DBE1435F58",
      INIT_43 => X"3C2908A344D33AD9016003CFA5836BFF6B6E973CBAD6D99868B255DE175A08BF",
      INIT_44 => X"05EE99D0C4E2EAEDB50E2C8895045DFE5A1A1FF172F0AA6A5CAE470C3F7CAD20",
      INIT_45 => X"CA3B78786DEBC76348B60097A3C182542B23CBB4A9F96163A384548E607EE8F0",
      INIT_46 => X"BA6555DE46CCF1174BDF10BEC52EA03C1FA32B9BA4E542379115ED9CD123E36B",
      INIT_47 => X"D1E950F5FC9FC14BBA7EB4FBF326E09CDE65CC7BE04C6180673E7CEC756AD75A",
      INIT_48 => X"28898D97B4B98498504110BDDA5BE79D06CF95BFE7F9B185D3E2CD2A9C64E80A",
      INIT_49 => X"419DD40BEE5315D6A539658B142FB0DBAE74FC9551CC54738388201445AAF277",
      INIT_4A => X"2B362158FA5171548FB0268F570FF35FB7ACF798EE2DF057E00CEB0A029C9386",
      INIT_4B => X"D3FF99CD9BF599A19FB92D3AD3773097F99442E2F4CD9F5F30825ABC832A7738",
      INIT_4C => X"4CE206F48AB77477F38E1CE51E8671B25E028EAEA8B3ACB39491C980BDB78FEE",
      INIT_4D => X"9370A55DDECF3CE8FE1838A6A4E2CFCCCB02150985FB5BB87D569AEBBCB4310E",
      INIT_4E => X"DAFDB741494D65E1D9ED0F680FA6E2163C81A2F44E39530861F4F560B1858649",
      INIT_4F => X"CD646EE7F083430486C9481CF00187701EF276C045210D8714B2E9936C6B3FDE",
      INIT_50 => X"A628F13995876356E6CECDC0A46552FD6AF1FDCF7114E762DB46CBB54932DA96",
      INIT_51 => X"FEAF821ECAEF5A35834F9E3EF920FBF186B56E10997F12E637283A3B8F08A5DB",
      INIT_52 => X"1797DB1E702DE8159F8FF45155CEE901F2C3332ECAF21E306B22EE85435F1BA6",
      INIT_53 => X"BCE146E5C43B27AF85737DD0A0C1F3F413CAC62F9339B8AFA4821ACFCC6A27BD",
      INIT_54 => X"92A0658DFA798FA0FB5C7F3CD1AF4C2FD6A367FD647F11688D74CA834D5CBA2B",
      INIT_55 => X"AAE6CBB2590C71FC55D3ABE77E5980308A35385661435B9474D6D5B2B44F6A29",
      INIT_56 => X"76027524FC355BD3C3F0D1880F999B4A97FF0BA57904B446A284268A5EAD207B",
      INIT_57 => X"C469C251082081E5E2F1D467DCBF49947760BA582634EA4F9E723985FE06E7BB",
      INIT_58 => X"C1C645B2AE8060634362835FAB5FC3DF7A9C06A8C0F0F1A24681296896C0D8B7",
      INIT_59 => X"BDE4956A1B3EFD312B79D8BDC4B8785B9706B280225262D5DA5A64E4668685FD",
      INIT_5A => X"E2415C2810572378F94D31F6AD9CA5082FD1FCCAB2EEBD23B2BED38863DACF23",
      INIT_5B => X"92898E24212344C099CF76C244926C7E1DFBED71553570507EA8D21AF0FC5F54",
      INIT_5C => X"BB020C0796474D6759B4B1ACAD1079A5FBA308692662853F067D9ACAD01CD0A1",
      INIT_5D => X"9CAA91CC8C61292CD01CC9EF70E2A7C2482A8F5A5AD06D090CF8C16F655F10D5",
      INIT_5E => X"04BB4CC51DCE3FE4F4C160F585F99586F9BAE4C7D0D91DC762C9B0DFB0616C43",
      INIT_5F => X"E300620C8D2DBF65E2EC452B70F73E2C277FA7CB4E5B28C1AFF439F50E047807",
      INIT_60 => X"A2260EA8C0AA30B3F7244E5BAB08FACAFA1B0B688F8E32228F3FD1CAD67D41B9",
      INIT_61 => X"21F93C2CF5FB975E5582ACC85A4C04FAC60ECFD2CDA1DC82D7F1FBD3965CD344",
      INIT_62 => X"B2665DB53AF89B7411BA9E55974756DFFD8CBDDDAF178F4F400E6E95493F2691",
      INIT_63 => X"CD4EF8B3A6AEE1D8C5B6D357526D65C4A54C3BE03C0AB19209189D3280D8C1D5",
      INIT_64 => X"38CFD40C925701AC96E84B46771039F61778AA78430AC4D8FB8ADEA7CDB185DF",
      INIT_65 => X"CE8B8F898A12C628E83DEB84274A71621214E4647A174FF4A9E8D1E4DFDFF887",
      INIT_66 => X"8694CB2DE0299DBBBF0F7E4A648DAA2F3DFE7A66F70D076A4F799A9A88B7AA7D",
      INIT_67 => X"B55DE73F7B30EF760F6B31F70AD8552CCEA3335DCDF5F9D0279F324F5EE5A773",
      INIT_68 => X"DE1D9E942EDD8FA054DF8E15679AF74A570846255DCF341C90CE0361A5A48195",
      INIT_69 => X"B0543A6F42CFF023295F287E319EB96C66ADFC74EE304D80122D91DFA1D42EA5",
      INIT_6A => X"95A18B0B42A6D8FF947502A335413E981F4C98EFABFB0EBE526C3E07C392CB9A",
      INIT_6B => X"38107F041036BE836F97539ED184D56A5143B4A22F07F8A96FA483351359DCFA",
      INIT_6C => X"C349ADC0A87C377A651F11149933554C0541DFF2212FAF2E9B57FF0150875F76",
      INIT_6D => X"18D3023F8E5131BDCAC044FFD719FBE310B7F6278C05CB47F0B91DC21D2729E2",
      INIT_6E => X"B90BB08BFB8EF16179F99FC8B70E4FF4A1B656C6830BCF84A278514E5C99FBF0",
      INIT_6F => X"2F1BCCF41B4AF6DB6E6ADA70E384D3763AB4CDE330F448458936F8C618FEF0B2",
      INIT_70 => X"1E21EE84479B43FEBFBCB9C7CFEC84C391F9B92AF1349FEBE0F5772172CBC63A",
      INIT_71 => X"B3FA99DCBAC4455B932D2FA8F0827CBCA54A2E860A84834CE7AC90733F583218",
      INIT_72 => X"B77770B1D2D7136500D5603F9DCDCCE72BCF84F98D33602F06963FBCE7C9BA7C",
      INIT_73 => X"A4D262D6F52EFC41B924BEEC18234D9678B1D18AAF6357912E65FFF536887A96",
      INIT_74 => X"A4253BE1141628A559E6D237018C9C19C0881C794C7058F34F314B208BF59978",
      INIT_75 => X"206F02A75848C7C543A91FF9597204CE897F39CE86F92328038D9FFA452FB8B8",
      INIT_76 => X"0CF2742ABB3EC0ED0AE17FB3FA0B011DB39B962650008243F3CE119184EF4746",
      INIT_77 => X"10BF03EC55C6D7C62ABD2E3372EB0EEAAFA7E7E56F8BAF3E9A4B7FB7964348EE",
      INIT_78 => X"298B934A2CE7F1BB49D5932B6BF2E717D0D36A2DEB86FB32088903EAF4601A59",
      INIT_79 => X"31154DB083DB72C57009E260D4E4579566F01624F4FFCCB6AE38C2FF55EB689B",
      INIT_7A => X"FE16776428E8813D8E8D58272CF94E7734A0357485160BB8F7B8BF72E0AFA487",
      INIT_7B => X"FF2B45659CD21AD9E664FAED9AE6527DB139ADFC90E29A0C2A55FF122D003E65",
      INIT_7C => X"04CF2A14F81F33645F533FB5D71F4A7A8A29B60A842AA166F29CA5A178293F98",
      INIT_7D => X"FA44B198539C951C08CBF19B94E1CFD4D563770CDC76B8D63F4345A767E1FE36",
      INIT_7E => X"93072B4B7A0A30E3426BB575E24660D53E937E23E2F46F99985939051B4078E7",
      INIT_7F => X"0102F1538022062459819343112773E526AA99F21A4415F4D2D213F87884AF76",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
      READ_WIDTH_A => 4,
      READ_WIDTH_B => 4,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 4,
      WRITE_WIDTH_B => 0
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14) => \LFSR_in_i_reg_n_0_[12]\,
      ADDRARDADDR(13) => \LFSR_in_i_reg_n_0_[11]\,
      ADDRARDADDR(12) => \LFSR_in_i_reg_n_0_[10]\,
      ADDRARDADDR(11) => \LFSR_in_i_reg_n_0_[9]\,
      ADDRARDADDR(10) => \LFSR_in_i_reg_n_0_[8]\,
      ADDRARDADDR(9) => \LFSR_in_i_reg_n_0_[7]\,
      ADDRARDADDR(8) => \LFSR_in_i_reg_n_0_[6]\,
      ADDRARDADDR(7) => \LFSR_in_i_reg_n_0_[5]\,
      ADDRARDADDR(6) => \LFSR_in_i_reg_n_0_[4]\,
      ADDRARDADDR(5) => \LFSR_in_i_reg_n_0_[3]\,
      ADDRARDADDR(4) => \LFSR_in_i_reg_n_0_[2]\,
      ADDRARDADDR(3) => \LFSR_in_i_reg_n_0_[1]\,
      ADDRARDADDR(2) => \LFSR_in_i_reg_n_0_[0]\,
      ADDRARDADDR(1 downto 0) => B"00",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 2) => Q(12 downto 0),
      ADDRBWRADDR(1 downto 0) => B"00",
      CASCADEINA => '1',
      CASCADEINB => '0',
      CASCADEOUTA => NLW_BIN_out_i_reg_0_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => NLW_BIN_out_i_reg_0_CASCADEOUTB_UNCONNECTED,
      CLKARDCLK => ctl_clk_i,
      CLKBWRCLK => ctl_clk_i,
      DBITERR => NLW_BIN_out_i_reg_0_DBITERR_UNCONNECTED,
      DIADI(31 downto 0) => B"00000000000000000000000000001111",
      DIBDI(31 downto 0) => B"11111111111111111111111111111111",
      DIPADIP(3 downto 0) => B"0000",
      DIPBDIP(3 downto 0) => B"1111",
      DOADO(31 downto 4) => NLW_BIN_out_i_reg_0_DOADO_UNCONNECTED(31 downto 4),
      DOADO(3 downto 0) => BIN_out_i_reg(3 downto 0),
      DOBDO(31 downto 4) => NLW_BIN_out_i_reg_0_DOBDO_UNCONNECTED(31 downto 4),
      DOBDO(3 downto 0) => BIN_out(3 downto 0),
      DOPADOP(3 downto 0) => NLW_BIN_out_i_reg_0_DOPADOP_UNCONNECTED(3 downto 0),
      DOPBDOP(3 downto 0) => NLW_BIN_out_i_reg_0_DOPBDOP_UNCONNECTED(3 downto 0),
      ECCPARITY(7 downto 0) => NLW_BIN_out_i_reg_0_ECCPARITY_UNCONNECTED(7 downto 0),
      ENARDEN => ena,
      ENBWREN => ena,
      INJECTDBITERR => NLW_BIN_out_i_reg_0_INJECTDBITERR_UNCONNECTED,
      INJECTSBITERR => NLW_BIN_out_i_reg_0_INJECTSBITERR_UNCONNECTED,
      RDADDRECC(8 downto 0) => NLW_BIN_out_i_reg_0_RDADDRECC_UNCONNECTED(8 downto 0),
      REGCEAREGCE => ena,
      REGCEB => ena,
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => NLW_BIN_out_i_reg_0_SBITERR_UNCONNECTED,
      WEA(3 downto 0) => B"0000",
      WEBWE(7 downto 0) => B"00000000"
    );
BIN_out_i_reg_1: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 1,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"1A833DF1CA75DD49981A4E9035373AC793D0A5D98AE047A73059A0770907966F",
      INIT_01 => X"917A0823437DBF016CCAC7650D6D34DAEA78F1FA44FEB940B35523C7B3DA0C87",
      INIT_02 => X"FEFAD868FF012FDA94849F3FFB6AF410EBB485B522E33C779B335D8AD0AC18B7",
      INIT_03 => X"69A1D7BA70D8B35384F367DDAB9F0011769C3CDACCF786E6007DB62D3374BD8A",
      INIT_04 => X"1E8B4B34F8A6DBA5C2127ED3637C8778492BD3A345ED796A1D40EADCD1386B97",
      INIT_05 => X"5F7EAFFA0DB85638CF5F00E1B22FDDAAC9D44854A9D0B37F9FCB56AA6F24F170",
      INIT_06 => X"1716F94C23ACEDEABCFCDF47D826AE16E080B82D6B6612FDD3E367047B4D28FA",
      INIT_07 => X"A6B9AAF1BDC72B0AD790CD284B6335F338547F234698FD8D7A0B99EF208011F1",
      INIT_08 => X"14F9922BCDF37A049455DE7DA769261AF21E4410FE5A3D9DBDD163A826ECF9D7",
      INIT_09 => X"C2BE78AB542BE3549FE88A867DEB5B555CC21162371EDDE3F7F3979C6877F778",
      INIT_0A => X"9C793ED4858825B43A295DE0FBE3671FBADF7D7B5556FAFAB62FB2D48F51F7C1",
      INIT_0B => X"650F779E2A8F4FEA50BD7B48051683B8DC3F665F30101E01DC22B26F4D1DFA8A",
      INIT_0C => X"1EF00870BBE8D2FD060B06A651F2C07D5D134E036627708497FBA44DC2D80F2A",
      INIT_0D => X"11E841C64F99B52CA223BADCBEBDAE0A1B9CEFFDFD4FD4288D78A236FA1E6186",
      INIT_0E => X"23681594C7CF3233847609284F4D18CD273A402C69795E3F321068B191516F81",
      INIT_0F => X"3A165B195A2AAF41FBBDCC57420B403AFD87D9F0FCDD52C8544B46934325AF63",
      INIT_10 => X"F02F17EF4E412F0FF2EA57A73AD796D9B4D1DD186C30A78B206CE4C8F39CDA76",
      INIT_11 => X"1443FC96932B23B8C2D0F2387FA708429E4B5058DBE17FDBA4856E972F6119AC",
      INIT_12 => X"5EC3CF29111C7624377B19E7DADCEC35FB79F239947596C668827B7CFF798B86",
      INIT_13 => X"C623B5EF898EBEBB564F24B7EC345E4993F8E29F9CAA86628CD8ECB469B65D59",
      INIT_14 => X"B9AADAFD76DE7BBA5666536DF8A205ACB361270EB121EF4C90FE5C13F773C515",
      INIT_15 => X"98D3719337ECD647825581882053BE4B31AF269250D0E20AFEB3EA3F6F7F18F8",
      INIT_16 => X"DADE30F1696E5AF1320612011DE1071DD0C52B27B52E65F645D71FD2F1A783A4",
      INIT_17 => X"666801F6747499EE2DA58FFC40FAE2A4540DB6DC8AB24C8F035716628039BB89",
      INIT_18 => X"5CD310464BE90039776B247B78088C469C79FDB6AF4547DED52AD8850CF223A9",
      INIT_19 => X"13EFFD080C8B710CBDB7EA8DDA29F4D80F6602BE1169A26C542BF92BC20E76D4",
      INIT_1A => X"10BB9FC9E1F5FBDCF5ED4BFADA483C8A89EA7888A0214B66F3AE1DE662178662",
      INIT_1B => X"141FEB8A4410C1634DF79D9FB3573AC8AF2F2C3EB6A0D2C2BAE6B7D9A5EF0EAF",
      INIT_1C => X"2B7E37AF4E093FCC649F719363EB3EF43F2211056D8BB51F921E5C1467FE8E19",
      INIT_1D => X"2332718514589347CF7DCCF43A2E3730974E786205922C8448FB4BDB1882CBD7",
      INIT_1E => X"F8DF8F78DF96061AF1DADEE95029C08E5F4E40BB4865903E5C4A285BA2FF6E3B",
      INIT_1F => X"32AB116C65B4109655AC23A2A5F94413FBB3BEDBC2C55E754A2A00BF4A073BA0",
      INIT_20 => X"ABD4FD919DEE7278F60C8360AAE738AB6270C66C7FF45CD88F74193CCDEA5706",
      INIT_21 => X"BFC0926F51970E8F14AEF421826FE04F6FB35E1AD5C7CA2783AA1D7729E64D29",
      INIT_22 => X"098EB41B350026187D8B2EE1D75F1D5BBA24E8E5C61EF977F2F056611159CAEC",
      INIT_23 => X"1114B4038FDC491669C3624B32731B58EC922DB09F327308F7EF0AF71028F4D2",
      INIT_24 => X"3FEBF7498FA2835939C4B7C599462C9636B80872A80B571CFF1FA779180BC8C6",
      INIT_25 => X"854E5CA4CC2F7289E1E1610C47E6727433C7583BF1093EF7ADEA6D1C0E1CE335",
      INIT_26 => X"F9037F78FE0269FFB95CDA8AA816E672F8BC7D986E9CBBE43699BB86965DA519",
      INIT_27 => X"BC46B2933B559F7FF869A99EEB5EABFB2587D4E0E214AB27EF9CF3B425BEE4E9",
      INIT_28 => X"0B846631E297F00E0B3272D1BECFF41CB9401F8E65DC8123AF87F8A36C7581C5",
      INIT_29 => X"BB39FAEA2DEAEF1DF7F6BDAEF76B3B9A85C7E64735F3A60D2F883A9230A5FA1C",
      INIT_2A => X"D3915A4FC2E60992D5C0DDB0BE7200BABF2EEBF37E3A233F06EF07BFB168AF68",
      INIT_2B => X"D9083DF397D119F353E7BE5C4DD6F4C7C85225E5E8E16818020095D39B4E24BB",
      INIT_2C => X"0D603CF512AB02079BA562BED6653FF69435BDD7412FED622FD14AC7B823BAC4",
      INIT_2D => X"CD7A9DFE53D02F913689561EE52B5F21E3929006E192100171FD8E511007816D",
      INIT_2E => X"554430ADEC167D9CB88AEBF254DCC8AF40E3D5D7D1166722F8905399CBCB7959",
      INIT_2F => X"D696961800018FF647B4D714F9D93EDE928D8AC5D8EF1F3C14509FCAFE223AC4",
      INIT_30 => X"A2C37F90FEDAB162A4FD4B5F4D78D7E6DB5028ABD28F83510BC3FA202C43A4A9",
      INIT_31 => X"59C4D44A130145664BB9EDA60D0C37A0747861BF32467FBF7E850D8F86C2426F",
      INIT_32 => X"09F26C6B0A27B5F3161E6298AB356EC55D4E26CDF69C25BBC3280FE97F66D749",
      INIT_33 => X"1033EDFBF6E0008E03C78CBA7F1D05CEB1DAB27EEAAC8BD5D0A42296F04CD783",
      INIT_34 => X"879FE1AE7F869D81A8072E1245C8716CF135A0EC10D5E76E68241172866A6D30",
      INIT_35 => X"1E0DB3BC99F9D295F912F056F0BFD6CCFF5CE1DA49BBF3A6D1A8408030C182AC",
      INIT_36 => X"A3F7270228CF39E9B56CA60CD12CCE20BEADE563B285DB99A650FFFE02E6A1F9",
      INIT_37 => X"1C4D1DFAE7BD8AA3494F1D0FCF1C6E3845DFF3839DD890F7C2355F7039BAC182",
      INIT_38 => X"3FF428231A18005965DD83BBB95F19FBAD271BEC5CC91B416770F9E885EB1993",
      INIT_39 => X"24B971EC3F77B4F24DEA05933DF3C7C56D439105711E963F663BE7B832E4F240",
      INIT_3A => X"9B7548E9789F6A2D0E509B2E2FC78348468805B94DBEDCB11C9E882FCABADF77",
      INIT_3B => X"35313524741984551343508E9A3B4D7FCEF57CDFC1C8F64437A42DE839853C03",
      INIT_3C => X"52F844EC4500B0BF49956F519C033AEC5FC64EA6228552BFA326FAF46CE134C8",
      INIT_3D => X"FA87D20488FD7D89D8F49A640C6C15AFFE11D8A2DEE3EF9D51092090C3018CEF",
      INIT_3E => X"F4B3B73FBBE8D4B7CD25C75B51E4745E4FA32AA80D07BAFA44A40F7A3DB6AF03",
      INIT_3F => X"4D23A7B2191077CC6955C654111F986D5054A0C1203AA12DA852FF9F4F45263A",
      INIT_40 => X"960247B06CC6063CE7FF4FA4B52CBD08183FC7D49149333C9CAD8E4A35A70096",
      INIT_41 => X"6ADB7DB58F5DA901793DCE8E07B237B8FFD6F02C9883F6F1EB8B2E379358DA1B",
      INIT_42 => X"57AF0B43C50EB2DACD45ACB79C5A62F71843FADAC17D678742DA4E7614EDD269",
      INIT_43 => X"ABAFBC20D9C2463F357249F7709E280F11F42AEEBFD4D2A1E8B2661FDE60742F",
      INIT_44 => X"CB7A52E59E887E555C1631DEFF9967F71F92CF6095C7A621F141F539BC6A2EFD",
      INIT_45 => X"6079284E5B74018BD3653110D2B641F8973D882B324EFE61BD7755FFB2BD85FC",
      INIT_46 => X"1E4C49B2A2BDABA019EFF4D287A3F1681F07BEDF000A5FC7514062789FA4CD02",
      INIT_47 => X"31515294FBC44043F8DFFD4C444942A62619CC338702441C23426753316B9568",
      INIT_48 => X"43C63B382028F782EB08B1FB45E7F19C0F7FE1FF2A67A76941D8C07B0C483CA6",
      INIT_49 => X"635F9EEB6F47C4E9382FCA62C8C396D9E3F90C647B97ACC5B929456682BCF9B6",
      INIT_4A => X"83137C67151803EB1F620029E3AEFF879AAD5EBA663D725C317E11FC0EC37355",
      INIT_4B => X"6805449ED5FC0A244C6CA2CF376209B99E019EA11621D07C05B75E5657F21734",
      INIT_4C => X"3FD8CB0CD7ADA948F62E192C4B9B2E64C306B9097B4B88C6C9D6F57E5A85C139",
      INIT_4D => X"4FBA4013D7DF37A8EFCE6022A6795FEF0BF915BC5DAAA8CA9A8801B63ED62762",
      INIT_4E => X"32054837FDC4AE707E8251C48ABB82B7BE7FE9FC4F133BE4F205CB5F2EC47EE9",
      INIT_4F => X"2B1C54064C325943B3EB25E59A0FA7B08FF8F66A1AE9090EFE0B850ECA8B2FEB",
      INIT_50 => X"BC9649081AF286E46B51DCC28A172E32ADF98E76F086AE3A67C67F5D8713CE50",
      INIT_51 => X"01BF8D416C633715E92A9370FE0F02ED08B13021782DD515B2EEC1F7FF5615CE",
      INIT_52 => X"845AC278EE604E773B52F03FAE6101E32EF48A853CAC94293B07A051F1A610CC",
      INIT_53 => X"B4B93597F6A9E5AF28DEE1A2E9FB1BDEF077F06FB5D8A1E6FB7969BD39B895A1",
      INIT_54 => X"B3FE2EE1EFBAF5397CE43FA028383AF00863E9F0037CBCF1B4186D82A8FA678C",
      INIT_55 => X"D03F9D1F5EB54DFCC52EEE61009D942BD954CE09DCDBB70BB2EF73230E0AB6A6",
      INIT_56 => X"C79F5D292851E252E980E9107F851086062F1A009A6BD63F93BD42E62D4CB2BC",
      INIT_57 => X"D991008F4BD1FD3D987CDE13159BF23C543AE179B8EF5DC94EDDD162F959CC75",
      INIT_58 => X"944A3156B9D6DC70481F26FFE5DF622E23F0EA124DAFC876B08B2F31B3A0C349",
      INIT_59 => X"03DB600E37CAFD5E1A2EACB504260C7392CBA7536E28B5E5DE6D6C5B38F9F669",
      INIT_5A => X"ED3C992592060F6CEC1A9B261800012C7F1EF6D187E2581C150C057E841269D0",
      INIT_5B => X"CDDA7DA39FDFFCE85F32D80725F09A1237628F995C6C1CE0ED5325B950FE2519",
      INIT_5C => X"491CF742DA53D375D3151E6F6B782420F483A8095D3B9F9AD7BCC9B170985B93",
      INIT_5D => X"51544945330EABDFE5CF186374D895C3B5898FADE0BEF7386849DEC0CE8FAAF7",
      INIT_5E => X"A7248DD984A4CB5FD182E3FD19F031CF184C500F95F1C3ACF6E6252E36A4C148",
      INIT_5F => X"D372907C95641F8D04010A1D82FFF56A437EB847D57B144EF298D79A44FAD6F3",
      INIT_60 => X"6D7B85A073C80B3BFDF298FFE82385D1804B6C03EF4AB2B012CC94339A843A09",
      INIT_61 => X"AAA2DC43273F79201F2EBDDAEB61D6625A04CFBDC4AB956F14FDB7684D471ED6",
      INIT_62 => X"67245708D621DB4F938234F6B75FBB8FB75E9875503DF86F19C69CA2F4F2B62F",
      INIT_63 => X"3559FC44FDF4444A21C3804124653696144BABAA1EFD8AF610BD005C54679AC0",
      INIT_64 => X"659D64CE32C6CC9DEF0679ACB2468BFB4C3322F8E0BF4EF9F7EF26A64DC70439",
      INIT_65 => X"6049DF0246AC360B909A12D70B555F138176110E1602E9F89A5B6375361EFC75",
      INIT_66 => X"4B41DD3AEC62A75E0E1A5AAC980B3D253DB0DAA4F2124926CFB0748CCDF758C3",
      INIT_67 => X"21504353BE2E9FAB8FF61EF0F080C82E3043FCA7784C7B8BB7EF413DF0C52C7E",
      INIT_68 => X"1FD1C3759A30EE2D81008D552E17F65EC698A264B1C1A7E2D9E606EA76FD73E0",
      INIT_69 => X"4957695F8E118BBE070F5816B99D98514A28D0E7B20FE113E4A5CC48B701160C",
      INIT_6A => X"0FDFE5DC5EE10D3A94E9CB7B2F33EA663DE1FA58C4F088A083903CC148D28A7C",
      INIT_6B => X"910FB0DD8CE35B2C49198FD9ED1299C57FD981229F90F5066FA0AB6F3D26DC1C",
      INIT_6C => X"3B0E7ADEAEC546C32B72E855EDCB89694A1695B08F6F5F2E30A2CE860BF13F39",
      INIT_6D => X"DAD3FFC7F28750A272F9CCBFD359FE59DC9516FCCAB6801CFE61728C5C5E4290",
      INIT_6E => X"14953EBF4F83385359FD0D7889E0EF979C72A33535EFB7404389DBFA7C91F8A3",
      INIT_6F => X"310C54FD41AD1F5A3E875B4E287A4A6374D944BF122D901F8C0F413C664E5418",
      INIT_70 => X"AAD4237212BDE6C65FCBCA961FB6441D677A7C03FF9FE18D8450E4BB1C939830",
      INIT_71 => X"35F4FF442C84263914AA1E8F0B05569C6250D2D4983FB5B8B59753F61B9AFFB2",
      INIT_72 => X"64D04A30991D0551871010EF956731F7696B3CB9E07AB48F432FEA4FFE2A4C03",
      INIT_73 => X"2545B29A7F1FE8C234FA7478BE43FC2744D3E6A5005A90323BDAF032CB78CF5C",
      INIT_74 => X"4565818B0051B99542DEB0E1EAC4B0101DC793E2808521F5C8A6BCAEDEFE7F7E",
      INIT_75 => X"90BC8E52418DE19C7D8298F06AA632D10DEC5E039EB723E63EF5CF7A893B4D87",
      INIT_76 => X"DDECF85A7FCBD5F5D91FCA81F6785549307DAC4C27E5EC86319B86523AC70F33",
      INIT_77 => X"305F4A15385427467D4B129180436451183B48355F078DE997A33DB448DF79FA",
      INIT_78 => X"54F4C4694AEFA56C20248F585726BAF2A4322D66FBA6F64D7AC3FF1D304BC380",
      INIT_79 => X"552AFF824A48E3C743650A02BA02B8FC40909D5160FF57179BC90A3F3FAFEAC3",
      INIT_7A => X"FCE21D1CD280A621DCE3E736E5FA9BD7551B01952E01A400C732041586CDEEFE",
      INIT_7B => X"FFA58476DB2103418B85F7D973D48F9ADC8AFB459FA168590DCC64C61B62A7F3",
      INIT_7C => X"5AF1A83725A1A28C0FD10F77B9AFFFA34449AF5C04F876A232D6B66DA3FD0A30",
      INIT_7D => X"F546B131B57934FACAB5E189DC46B173C2DC2061C3765AB75A15E14072455DEE",
      INIT_7E => X"5611594AA519C6132C0136A7A51025DEA187512CF1F79FF349FC4862266D3DA0",
      INIT_7F => X"00E02E30A37EC3201A93170E7C73C2C0619A5953C167504E171C17F39C826CD0",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
      READ_WIDTH_A => 4,
      READ_WIDTH_B => 4,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 4,
      WRITE_WIDTH_B => 0
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14) => \LFSR_in_i_reg_n_0_[12]\,
      ADDRARDADDR(13) => \LFSR_in_i_reg_n_0_[11]\,
      ADDRARDADDR(12) => \LFSR_in_i_reg_n_0_[10]\,
      ADDRARDADDR(11) => \LFSR_in_i_reg_n_0_[9]\,
      ADDRARDADDR(10) => \LFSR_in_i_reg_n_0_[8]\,
      ADDRARDADDR(9) => \LFSR_in_i_reg_n_0_[7]\,
      ADDRARDADDR(8) => \LFSR_in_i_reg_n_0_[6]\,
      ADDRARDADDR(7) => \LFSR_in_i_reg_n_0_[5]\,
      ADDRARDADDR(6) => \LFSR_in_i_reg_n_0_[4]\,
      ADDRARDADDR(5) => \LFSR_in_i_reg_n_0_[3]\,
      ADDRARDADDR(4) => \LFSR_in_i_reg_n_0_[2]\,
      ADDRARDADDR(3) => \LFSR_in_i_reg_n_0_[1]\,
      ADDRARDADDR(2) => \LFSR_in_i_reg_n_0_[0]\,
      ADDRARDADDR(1 downto 0) => B"00",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 2) => Q(12 downto 0),
      ADDRBWRADDR(1 downto 0) => B"00",
      CASCADEINA => '1',
      CASCADEINB => '0',
      CASCADEOUTA => NLW_BIN_out_i_reg_1_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => NLW_BIN_out_i_reg_1_CASCADEOUTB_UNCONNECTED,
      CLKARDCLK => ctl_clk_i,
      CLKBWRCLK => ctl_clk_i,
      DBITERR => NLW_BIN_out_i_reg_1_DBITERR_UNCONNECTED,
      DIADI(31 downto 0) => B"00000000000000000000000000001111",
      DIBDI(31 downto 0) => B"11111111111111111111111111111111",
      DIPADIP(3 downto 0) => B"0000",
      DIPBDIP(3 downto 0) => B"1111",
      DOADO(31 downto 4) => NLW_BIN_out_i_reg_1_DOADO_UNCONNECTED(31 downto 4),
      DOADO(3 downto 0) => BIN_out_i_reg(7 downto 4),
      DOBDO(31 downto 4) => NLW_BIN_out_i_reg_1_DOBDO_UNCONNECTED(31 downto 4),
      DOBDO(3 downto 0) => BIN_out(7 downto 4),
      DOPADOP(3 downto 0) => NLW_BIN_out_i_reg_1_DOPADOP_UNCONNECTED(3 downto 0),
      DOPBDOP(3 downto 0) => NLW_BIN_out_i_reg_1_DOPBDOP_UNCONNECTED(3 downto 0),
      ECCPARITY(7 downto 0) => NLW_BIN_out_i_reg_1_ECCPARITY_UNCONNECTED(7 downto 0),
      ENARDEN => ena,
      ENBWREN => ena,
      INJECTDBITERR => NLW_BIN_out_i_reg_1_INJECTDBITERR_UNCONNECTED,
      INJECTSBITERR => NLW_BIN_out_i_reg_1_INJECTSBITERR_UNCONNECTED,
      RDADDRECC(8 downto 0) => NLW_BIN_out_i_reg_1_RDADDRECC_UNCONNECTED(8 downto 0),
      REGCEAREGCE => ena,
      REGCEB => ena,
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => NLW_BIN_out_i_reg_1_SBITERR_UNCONNECTED,
      WEA(3 downto 0) => B"0000",
      WEBWE(7 downto 0) => B"00000000"
    );
BIN_out_i_reg_2: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 1,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0F3B1520E51D000520823C988E92AD22FB505D0502C8E2D2B0D528220582522F",
      INIT_01 => X"D06FC3BBB135B250CED591BD70D0505532C0F812A33C2988D84E69026A2DC222",
      INIT_02 => X"F3C2DCD00FB811E20AE353AC828988E85D78A4DED6E980A2C6FAE22D8CB29202",
      INIT_03 => X"6D4066CF7C53ABFBDBF14375FB9215706C8E3DF569714B0D67F05D9095E055A5",
      INIT_04 => X"757DA768FA449D0ECDE64E2938309AE28CE65FAADED2227DC89CFB2279A2B092",
      INIT_05 => X"AFA38C92FD7C3DD0806F3BF8B1913E92108ACE9325C49A8C181208B99888CEE8",
      INIT_06 => X"262CB80E53ADCF1536C90791A47BC09DE6175F40251DA9E0E9251EC005C53AF5",
      INIT_07 => X"D68DC4A016766C3FA7ACC5C34ABB1FEBEDEB0F41443317B59F1B0982014527F0",
      INIT_08 => X"58FCEE26D5FF0AEAED8E4D726242274DAC48094C9F9B62A2C7F9DAD2BB102902",
      INIT_09 => X"6745876DFA57D6386F2A6424190DC01E9C3DCE46446EE2B963B82320794AFEA2",
      INIT_0A => X"4180784A1CCE2983D2857CD4399A582C4138E17250680B19E9B80828AC6EFED8",
      INIT_0B => X"CA4FCAE308BC2962AF0D57DC33FDBD30D8C0168FC30B5FF8BBF129E1535E1942",
      INIT_0C => X"1EF6E107354F9450B295D1AD1AA94FB03E3952E5C17E8CE0C0B58CA563DACF15",
      INIT_0D => X"B26652DC1B6880FE65B36A5DBCCF112573762CF960C739318AD487FB9CF0B99D",
      INIT_0E => X"0E5D3EEB80AF54B1B49463E30167CB75A93F912BF0690872F0B1C465D2A76FD0",
      INIT_0F => X"FDD6385D7CC4BA70F1E6B786B6ACB34FDA37EAFC4C455C43B46A1BCB710F1E7B",
      INIT_10 => X"A3CE4B8F01994ECF9DF998BE602EA729CF77F09ADEAEDA20B5B5180220920D22",
      INIT_11 => X"5784F4C7EBE7276DDF52F3F905ABEEA1E6D38FE448D2712D63214B2A2D744AD0",
      INIT_12 => X"98CA3AD2C9E24A6E4D4B64E3E525BF9D6E3FB9822E3D22027D914DA0FFE9A022",
      INIT_13 => X"607941568C7761DEF9A05E73DC6F3A8F6DFC2AAB69472E49119501D8C80D1FE2",
      INIT_14 => X"49133A8EE81A71255508618205B12195E69BBD9B0F8B2B8FA1C261E9FFEFD48D",
      INIT_15 => X"46108D047B8A49AD1EC6CAE428978D3BD82F81567ACDD944379193AE5F8F27C3",
      INIT_16 => X"D089C90C1D6180F9CF3004BE5BF4F482B9B9F514229BE21A503850E61A92482E",
      INIT_17 => X"CFAA4BF9C1A6E5380785BFCC2A98642AA2FB02D3507CD2CA3235F5DDBBDE3C02",
      INIT_18 => X"3BE1369C5628ED58C51277E086C2E40DCC00B05182C0A45F6435D5AEC9F61352",
      INIT_19 => X"12E7F961EA1A0871365749F999445705BF259450DA13A1D11EA1A49D43FBB808",
      INIT_1A => X"7139746626CDF1996301C9743E9F331787AEDF428471F5BE96CAF904B79398D9",
      INIT_1B => X"B92D63665622DFCD14BE668F860DFEEC6354B5326EA75FDAB7C8C7FA1B1F2C5B",
      INIT_1C => X"AF9730FD93172FBCF20868960D8E762FFD0AB713CD44695ADE2EA17866F5D30F",
      INIT_1D => X"03ED5EDF34E7E2B98503AAFA5E4ABB11B0459145623DEB3E071A6A77C6B57753",
      INIT_1E => X"D9A33F78E7A304CC43C1495757C74037B74366A61DB8C9B1781301FD15EF70BE",
      INIT_1F => X"FAD9D1663B805AD07CC4C247BBA87509FF1EEE64B8758B61BE69A8C5BB314BF7",
      INIT_20 => X"4C5FF7978F70F9EACDBEEA8E7DEAF2B06B35DBD5C13840223210899250CDD282",
      INIT_21 => X"8A73ACBEE43B184F20A1C979141E2CCFA97D6F9989C81B8E7640E23EEAD792A9",
      INIT_22 => X"4EB60DF3C80FFE5484C88D923761B26D46532201346BB24AF2FE8744449AFD10",
      INIT_23 => X"D5C7E8A43F446C075EAB9E673267B6AD6D6FB5C27FC3DFF9F0459AAB3E7EBAD1",
      INIT_24 => X"967E03FFCB7958D2A22EB35DF2D21092477D29B1342D1A40EF9F9EE97AE05222",
      INIT_25 => X"A9685C8AB3CA5DE29C190E4294BA862E04AD647BF6D41EF33EA58215BBBF29FD",
      INIT_26 => X"D62DEFDC427A8AFB96D914F7E21EA43971A1794550311DB81C88202D010F5E62",
      INIT_27 => X"96004789E4519516383C177736813DFEDF793AA155DEA7537D7C86EFA34AE85F",
      INIT_28 => X"DE36593B6B7DF93B40CF883B423BF84F8AE12C12A6817EE94F8FCE7F6DC4385D",
      INIT_29 => X"94E93133D35A78AEDE4891EA77511205A5B5909806F138B290C5ABF14231E975",
      INIT_2A => X"CD3872CF7891A5B6C77ACC9D9DA9D48493D7D971A9039A4ED56F484F82A74C63",
      INIT_2B => X"C466D160384D8044778B283AC479FAAD712E8C069C4A1E04A2F85917B82D63AB",
      INIT_2C => X"AB492BF9FF1581D45202991B1EA271EAB55083982520DE0661CA3992A418B20E",
      INIT_2D => X"7D9018292CC9E0CC815DC66108806F399C1FC3D040B4AB3E15FBEFD40F5448E2",
      INIT_2E => X"7A427F7B8032BD132550874C3D12ACAAC35243657FE59DFDFB6BAD6EA38CD0C2",
      INIT_2F => X"CCBF4A7A645B6F99DC211A166EB503A8300788354B4FDCCC82EA099846C4426A",
      INIT_30 => X"C6C10102BC0C5A138323C90CA94952FB6A413455D158A8E9CB95F26C103A5E25",
      INIT_31 => X"3BBBE511356C90C65861238BE9D4588CC25B15217275E00F8D6CCE2FE04206D2",
      INIT_32 => X"B5F4225C90445208D9AD1937A111DB1411EAAE1FAA4F92D0473EF1BABE870A8D",
      INIT_33 => X"1A25EB7BF4906910E2AB1BA70F8679133F6E5F7C4193F598989741485D740453",
      INIT_34 => X"817FA5E5DFF34B268E427F1FFD59B4E2906ACFADF5960441B47C983A9E8BD298",
      INIT_35 => X"791A3C96714A6F6C2C63C3DEFD1E9090643A001ACB9874463AE09BF733341E75",
      INIT_36 => X"6830515BB5573D256CE0A67556F2D1A8B073C883C874F0AD16BC1FF223CB59B5",
      INIT_37 => X"B7982DD6693E606851682823D2FEC9D01245BCE56C6889F18E6400D5FCECECCB",
      INIT_38 => X"FFDB0BAFB6781B3CCADB4D4E66965EACDAE923EEA8117C8C6D66F05CDC3D02FB",
      INIT_39 => X"ACFE93783507F2DE9437137626FEB5C4F7220F906E87956009D18DED7F632DF5",
      INIT_3A => X"B20E4556951F405C682F37D6E4BC3CE803772DA861AA7279CA64BC5F7A745A31",
      INIT_3B => X"0733EAD154E3D2F23747EF74E721BB958854003BA3A0F2AC5BE74DAEB1BC1315",
      INIT_3C => X"B87D423D6E64AA6210D2B98FC99EB81E748F163C0C15F4D91452E2FD760DBAE0",
      INIT_3D => X"D395A04530FA7781E874A836034FC5C8443ECB1244905F785D73CD724C063C73",
      INIT_3E => X"FDFE1CE6E2E96149B18A7A5381BD661EB6ED6E96AB85C550B0B133164AB3F878",
      INIT_3F => X"FCA0DC9BDB1E6F6734B78A0957AFDA0876C3C442C5234B7DB6B3AF8D79570996",
      INIT_40 => X"D6CBB3B5CD9B7D553CF1A328D46062C20312E100283989A2F5500CEDBD220852",
      INIT_41 => X"646C75AFDF47F917683F67406F599E5AFCDD0B1E0E5A888E57ADDE8ACFE28B90",
      INIT_42 => X"AA89F73D863FB93918C92C98110B98CE77A6F490CE42339E8E5ADD27C9F27AB9",
      INIT_43 => X"D8CA1763AACC4B1EEE04431B9108042F22B05AC13C09A7C9E15421AEE21C0C3F",
      INIT_44 => X"6486F5D3626210C193C446EB6B2274FA5FE2DF0EE8476424A404996ACFDDB120",
      INIT_45 => X"C4CE0B26A05D3FB3DC18C05FBF2E551448741C28D87D395243E75601EB02A6FD",
      INIT_46 => X"B65D168F6B65BC12772F6C338D8F9FB91FE03495B9DA1A4B335EC78ECB8A6DC1",
      INIT_47 => X"FD357CB7FEB8BAB4D3EF4454B61C7017053E8A5BB96E06C7A392F607FBC6DA6D",
      INIT_48 => X"7447B77DF2395BE163F4821D31BAD4A03EBF19EFD98E0E79F70AEEA0558202D2",
      INIT_49 => X"0916C71E90E3CFAFDCAB97E915188DF28AA292AEDB4355FDEF92ED22D1D0F902",
      INIT_4A => X"60D4BA9DE6A487DB8F16AD94713EFF7393AE8A15581251156BDBFBBF1219FF4D",
      INIT_4B => X"FAB9165875FCA84A2B230C2A255DBEC2099CD109F04EB44299542B2A0806A28E",
      INIT_4C => X"2791AA8167999475F540A311E14D3B88B16C68D85270624DC001204F455E9632",
      INIT_4D => X"9D3662FD4E6F6DEC3452E7FA787ABFCB19466D193194EF377EF2415E6A947389",
      INIT_4E => X"3DEF472953AAEAB105152DBE7AA76573F70D37FC2886DE6FDA73D49AEE18653F",
      INIT_4F => X"A916B0A0C427B859FEE485B1E985B1B793F8734C319777077366D891831D5F0E",
      INIT_50 => X"87ABE3142AC7112CA7698C1874E3ED9A45F987FECBE87EFB63DDC34231895CD8",
      INIT_51 => X"DCE934605A9636BA66BC7CDFF49A37BD4B0FC0F58C8936B6452036B4FF8449F1",
      INIT_52 => X"A658BC5E91049B820A67FD1F3A81BB2F970FC75DA2B5FD19472B3214E99E7E52",
      INIT_53 => X"9048E5913317383FD73A5DA5778EA4E5D2ED478F9D1FE1A37A74531B18220056",
      INIT_54 => X"9E33D57AD49E7510AB990F3B9CAF43E7D35367F34C8343F48E21A87E48C76C35",
      INIT_55 => X"C6D634847823C7FA72809410AF51B26AC37C79ABC7C99AD89DD7A094D6448A46",
      INIT_56 => X"79122CEC85C6086391CD4BA31FED054EA42FF18D50911A7EB58922D06C39A1B0",
      INIT_57 => X"CB476569D2116B0A308344DC8E094C46747783B1258431AAC5467E9FF6A6A8DC",
      INIT_58 => X"BB515C06813B948C2B51250FDCEF02626112CCA3339C992BA1451889B52C0AE5",
      INIT_59 => X"A5BB40902BB7F693FEFC13588718D443542C04289D9711B41AEFAF207E1AE7AD",
      INIT_5A => X"9AC61AFCC33EDE004A0AB846A0B734E51F55F3B6E2FFD9420AFD56414C8AEB28",
      INIT_5B => X"78D69E0818832E9025C5C891E405CCCB801B57D5C06562180383840D6CF23B95",
      INIT_5C => X"CE38572E47366E5472F0E75091DDF3D5FBBF68BCABDE66ECA93E81CCD60CCD2B",
      INIT_5D => X"73A1432277F471B5840B302CB7DE1C352E565F0C8F764CC837D81A29A4CFA4A1",
      INIT_5E => X"35050A7184863F584EB240F8D3C2C6C38D2DE4A2029F9E8E4F6CC549422D6DA0",
      INIT_5F => X"C0CBBEF747A97FA8634253BD63FD9796DEC629191AA31D6E6DE6B5500136A388",
      INIT_60 => X"667AD4F163646595FD0105885AD8CE89DCBBC9753FA2D66C01E0238AF50EB205",
      INIT_61 => X"DC16AC41E04190022B5C30ACE52AE103A8F382B31C29109C7AF9C43985D2CF7B",
      INIT_62 => X"CC02A53BD1C5B2514712D7354E50E0AF68FD661C9C4E627F5ED0E462A096CDB2",
      INIT_63 => X"F37BFBBBDE45B1710385B60CA9F0FCD6B51866B17263889B1E39BD1435C8C86C",
      INIT_64 => X"01C19ECADA9E118F8A9AD45FE9E2DDF074B7F35E6F813BDA2B1ED807F0EA580D",
      INIT_65 => X"FB157FA4220225BC09D0F4B4952200A86DB9EA8D81A973F79A8151516DFB01F4",
      INIT_66 => X"936F466E35EF77BC146139E37F45697829A86997F4A1E438B56D5764C0244593",
      INIT_67 => X"A1BAC2B5FE8BE7BB9F74396076D981503E425AEB012B7A67F03F28D6D7D9E163",
      INIT_68 => X"C940A66A6CCF4A7DBF05C9665064F4917B34A71C79C843DA597EB8EB3D3219C8",
      INIT_69 => X"0851378F7AD57E452D7FDF13A43B820668CE14B2A7DFA1BF7F7D25D97B249EE2",
      INIT_6A => X"6644837A2040F12A3C9B79A8D70464A6E35A4E50B9FBCF373373C334E18E87C5",
      INIT_6B => X"B75921BA034CE9C64731541A56EF668C92CC56831CB3FD5E4F1D01AE5920C910",
      INIT_6C => X"5B00B763EC3878434C48D714AFF0EA7DB1C61B4CB15FCF2212C33C9B15895BA5",
      INIT_6D => X"86E883E0558145CB0B750527334DB2B5A6AC3EE0AA860745F5362F92AD61CAB8",
      INIT_6E => X"313274154B0C7EC5E6FCF6C878A94F41E87E76E420701D35BF8CBE6C9E1C5CDB",
      INIT_6F => X"0BE779F8323D3D76E699A3DED650163855A146F8E2083263DD422FEEFC592DD0",
      INIT_70 => X"D1A4E490253AE2E0AE8B12197FC38DC767DF6669F0085DC8DBC73AD60E28F0B0",
      INIT_71 => X"F7FBD4B708B0AFFDB16B768913B13CC6C0A3DCB541D345EA6F6194675DE6A9CB",
      INIT_72 => X"F17A202B0DFB920A6BE88A7F98556F0F0C9CD91889D5EEDF7BF5683D21D0FE50",
      INIT_73 => X"ABCBF8EB97367D85345E0276F32DDDE696463E7B163E74672A69FAE3B656C249",
      INIT_74 => X"05387D7427D1A3806C1BADAB772D729EC4A66C47B0C656F973A17C4D57AE331C",
      INIT_75 => X"B52B04EC43515E689C581BF5410A52C1648724F2397AD06AE545BFC337C3E88C",
      INIT_76 => X"8E8E584C070234BBAA3EA804F329A6CB50B6E37444D1AFE7BC14B5C21C39185A",
      INIT_77 => X"0E7F3337E9ADD5135A4FE036D42EF52D3371407CEFFC7A44E77E2713B8B6915D",
      INIT_78 => X"7B4780FD1B6931C603C5135AF147D69B14405A20EB29F3D77F6908D8B7A6E800",
      INIT_79 => X"BB8B76D54E263DD666EB6E47A9A366291A0BDB2AB89F85FFCC9895EFB58D10E0",
      INIT_7A => X"4B4C31E8C8B51A2147429A0A55F3738C58D47130CBDB7D2E46C7066931CD7E3C",
      INIT_7B => X"DF379D53AF064E5D310CFCA47E73861DEE8C724BAE84396B063441F7C452C98A",
      INIT_7C => X"BB65E6D66BE79369AABA8F5FC85F5D00B70DB916353A176B40A0B937F9887680",
      INIT_7D => X"F7D3F6ED1CC4E36DEC2BE49B6417429ABC1885A172AA533C8410BBDE67691DEC",
      INIT_7E => X"736DC43DCB4B472AC8512A3C40BE79DCB566B739AAFF8FD07D965A7B00979860",
      INIT_7F => X"00C0AC00DACC90B0DDBA1CEC69F06B703D4DBB7A81AC0E9C5679AFF0D6AB0780",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
      READ_WIDTH_A => 4,
      READ_WIDTH_B => 4,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 4,
      WRITE_WIDTH_B => 0
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14) => \LFSR_in_i_reg_n_0_[12]\,
      ADDRARDADDR(13) => \LFSR_in_i_reg_n_0_[11]\,
      ADDRARDADDR(12) => \LFSR_in_i_reg_n_0_[10]\,
      ADDRARDADDR(11) => \LFSR_in_i_reg_n_0_[9]\,
      ADDRARDADDR(10) => \LFSR_in_i_reg_n_0_[8]\,
      ADDRARDADDR(9) => \LFSR_in_i_reg_n_0_[7]\,
      ADDRARDADDR(8) => \LFSR_in_i_reg_n_0_[6]\,
      ADDRARDADDR(7) => \LFSR_in_i_reg_n_0_[5]\,
      ADDRARDADDR(6) => \LFSR_in_i_reg_n_0_[4]\,
      ADDRARDADDR(5) => \LFSR_in_i_reg_n_0_[3]\,
      ADDRARDADDR(4) => \LFSR_in_i_reg_n_0_[2]\,
      ADDRARDADDR(3) => \LFSR_in_i_reg_n_0_[1]\,
      ADDRARDADDR(2) => \LFSR_in_i_reg_n_0_[0]\,
      ADDRARDADDR(1 downto 0) => B"00",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 2) => Q(12 downto 0),
      ADDRBWRADDR(1 downto 0) => B"00",
      CASCADEINA => '1',
      CASCADEINB => '0',
      CASCADEOUTA => NLW_BIN_out_i_reg_2_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => NLW_BIN_out_i_reg_2_CASCADEOUTB_UNCONNECTED,
      CLKARDCLK => ctl_clk_i,
      CLKBWRCLK => ctl_clk_i,
      DBITERR => NLW_BIN_out_i_reg_2_DBITERR_UNCONNECTED,
      DIADI(31 downto 0) => B"00000000000000000000000000001111",
      DIBDI(31 downto 0) => B"11111111111111111111111111111111",
      DIPADIP(3 downto 0) => B"0000",
      DIPBDIP(3 downto 0) => B"1111",
      DOADO(31 downto 4) => NLW_BIN_out_i_reg_2_DOADO_UNCONNECTED(31 downto 4),
      DOADO(3 downto 0) => BIN_out_i_reg(11 downto 8),
      DOBDO(31 downto 4) => NLW_BIN_out_i_reg_2_DOBDO_UNCONNECTED(31 downto 4),
      DOBDO(3 downto 0) => BIN_out(11 downto 8),
      DOPADOP(3 downto 0) => NLW_BIN_out_i_reg_2_DOPADOP_UNCONNECTED(3 downto 0),
      DOPBDOP(3 downto 0) => NLW_BIN_out_i_reg_2_DOPBDOP_UNCONNECTED(3 downto 0),
      ECCPARITY(7 downto 0) => NLW_BIN_out_i_reg_2_ECCPARITY_UNCONNECTED(7 downto 0),
      ENARDEN => ena,
      ENBWREN => ena,
      INJECTDBITERR => NLW_BIN_out_i_reg_2_INJECTDBITERR_UNCONNECTED,
      INJECTSBITERR => NLW_BIN_out_i_reg_2_INJECTSBITERR_UNCONNECTED,
      RDADDRECC(8 downto 0) => NLW_BIN_out_i_reg_2_RDADDRECC_UNCONNECTED(8 downto 0),
      REGCEAREGCE => ena,
      REGCEB => ena,
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => NLW_BIN_out_i_reg_2_SBITERR_UNCONNECTED,
      WEA(3 downto 0) => B"0000",
      WEBWE(7 downto 0) => B"00000000"
    );
BIN_out_i_reg_3: unisim.vcomponents.RAMB18E1
    generic map(
      DOA_REG => 1,
      DOB_REG => 1,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0054105404405044445110411011150504440040054145510000111500550515",
      INIT_01 => X"4404515045401510445050401144141050545505014050054504010101154451",
      INIT_02 => X"5500115011110011000110045544445110514014040104414441411114101101",
      INIT_03 => X"1050045455415540141114400555010414505544554414004105141401100144",
      INIT_04 => X"0104114154404150401004454014544150501441104141050114010041454041",
      INIT_05 => X"5111400005055544010145050040014504044445050040545551541050545145",
      INIT_06 => X"4550514411551010511514100150444414050455015045100041010444051454",
      INIT_07 => X"4104550444545554511110011111540405144105455454444011111544410450",
      INIT_08 => X"5501551014415015051151054014014410051451001410004004514451014015",
      INIT_09 => X"0015005004145004544041014114450150101500115151444011045145505005",
      INIT_0A => X"0150104141504155015500015000544154455515444015014501444054154044",
      INIT_0B => X"4505051551101100104400555444404010041005515511551110501000044044",
      INIT_0C => X"0451104410505545101454015155051010115114010510515150014415505451",
      INIT_0D => X"4045450155155050050554440500151054150554155004111004551051405141",
      INIT_0E => X"0144155041151054504445415441404041110515150414445150411401415510",
      INIT_0F => X"5104014055441040415044415545454145141554151001141405151554501150",
      INIT_10 => X"0544445145541501400001540144404050444014150150141141400550440115",
      INIT_11 => X"1555000551550144411014055504015500550501554144111040051404011010",
      INIT_12 => X"5544010001554000414551011505501010000545045411415411550411000451",
      INIT_13 => X"4440415544441504445005105540445415505044144104451005015414514441",
      INIT_14 => X"5550505515110115501454040111440110514041105410001550411554041450",
      INIT_15 => X"0401510001045445104551441045115504051511000444015500440415101441",
      INIT_16 => X"0540041441004055514511514505511505450504510441440044045454405054",
      INIT_17 => X"1415401500150551554501440501040401001450000451155154501450045040",
      INIT_18 => X"0500050554051441010511451511540555145401100541401454440155505504",
      INIT_19 => X"0040551515005051050155104445514514100550454010045404445411441401",
      INIT_1A => X"5451055411455551055544101150041415011150444414105515401044145115",
      INIT_1B => X"4100505550440104444515444511550010440154454040411145000115551410",
      INIT_1C => X"5115051410551545155401410450504154154401400515411014410454440400",
      INIT_1D => X"0005405004454400411515441411454145004141404550055551411441115010",
      INIT_1E => X"5155155114445450044505101005154005401154054404554440550004055400",
      INIT_1F => X"4415114000145111544441400410511040054401405050144545515551554015",
      INIT_20 => X"5144541054440510455104415100015405051445540400111504145400010511",
      INIT_21 => X"0415545410141501145555104111000550040000000155540441101454401000",
      INIT_22 => X"4040115500510405115510455450454501045444401541544414044101004544",
      INIT_23 => X"4151555540000051114155554001541454450500411004551115045004015115",
      INIT_24 => X"0504044040111411445055500505144151544145155104104145044000505105",
      INIT_25 => X"1115545040054000404155555444000014411415150140414155005111004500",
      INIT_26 => X"0111554411401054451454054054505105404451444155144554114554105445",
      INIT_27 => X"5010504014015111145454144155445410541544401141001515504054141154",
      INIT_28 => X"1501450540115105051054500411100015545510400505444541104104414501",
      INIT_29 => X"5445551154105455144514150105145455000540454011400015150450510014",
      INIT_2A => X"1040015505450505111001505051101454451001415100500444050014415114",
      INIT_2B => X"1141011455051011001401414541414414114045450451411511414505155445",
      INIT_2C => X"0055504511540151441410404004504110114141115155415441411044015450",
      INIT_2D => X"1045401001501550401410015101554445145155150454045154004455040455",
      INIT_2E => X"0104010015504511101101415514154455144551541104414501015144104000",
      INIT_2F => X"0550045540100454010104441155550555554044011441501054100500500140",
      INIT_30 => X"1155011015504001410000551401540045505510541440051115510011150010",
      INIT_31 => X"4455400404554051551040150114104144050411050554550155414551140055",
      INIT_32 => X"0154414044555500141110444504005011144010545411144545141045140441",
      INIT_33 => X"4044104015514555051540401144510500550405515145441454545155055055",
      INIT_34 => X"4155444541451144501010500550450451110551144405405454011011410111",
      INIT_35 => X"5114514504111110450110515511154140151111541445444141150400104154",
      INIT_36 => X"4104145404415150145550405400500505415415044000414511555141140144",
      INIT_37 => X"1405040411005551550014144441041010105415451154505415450111150400",
      INIT_38 => X"5541154450410104511011550545410505001440400510505450514101400100",
      INIT_39 => X"4504145511440541051144551554514505445550100551040140550155105114",
      INIT_3A => X"4145100050045014410051554411004545554505400414514014151455000400",
      INIT_3B => X"1111005450115410005150545150011041151444154450411451140450544105",
      INIT_3C => X"1045501115055451105441501051545451504110545511111040014444511010",
      INIT_3D => X"5504454405445414154050414540441111404044105505011511004504545000",
      INIT_3E => X"5010104450411005500045115501044041455145441445445414455540100544",
      INIT_3F => X"0040144405145010001105505504050444404141401551001151041044150410",
      INIT_A => X"00000",
      INIT_B => X"00000",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
      READ_WIDTH_A => 2,
      READ_WIDTH_B => 2,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"00000",
      SRVAL_B => X"00000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 2,
      WRITE_WIDTH_B => 0
    )
        port map (
      ADDRARDADDR(13) => \LFSR_in_i_reg_n_0_[12]\,
      ADDRARDADDR(12) => \LFSR_in_i_reg_n_0_[11]\,
      ADDRARDADDR(11) => \LFSR_in_i_reg_n_0_[10]\,
      ADDRARDADDR(10) => \LFSR_in_i_reg_n_0_[9]\,
      ADDRARDADDR(9) => \LFSR_in_i_reg_n_0_[8]\,
      ADDRARDADDR(8) => \LFSR_in_i_reg_n_0_[7]\,
      ADDRARDADDR(7) => \LFSR_in_i_reg_n_0_[6]\,
      ADDRARDADDR(6) => \LFSR_in_i_reg_n_0_[5]\,
      ADDRARDADDR(5) => \LFSR_in_i_reg_n_0_[4]\,
      ADDRARDADDR(4) => \LFSR_in_i_reg_n_0_[3]\,
      ADDRARDADDR(3) => \LFSR_in_i_reg_n_0_[2]\,
      ADDRARDADDR(2) => \LFSR_in_i_reg_n_0_[1]\,
      ADDRARDADDR(1) => \LFSR_in_i_reg_n_0_[0]\,
      ADDRARDADDR(0) => '0',
      ADDRBWRADDR(13 downto 1) => Q(12 downto 0),
      ADDRBWRADDR(0) => '0',
      CLKARDCLK => ctl_clk_i,
      CLKBWRCLK => ctl_clk_i,
      DIADI(15 downto 0) => B"0000000000000001",
      DIBDI(15 downto 0) => B"1111111111111111",
      DIPADIP(1 downto 0) => B"00",
      DIPBDIP(1 downto 0) => B"11",
      DOADO(15 downto 1) => NLW_BIN_out_i_reg_3_DOADO_UNCONNECTED(15 downto 1),
      DOADO(0) => BIN_out_i_reg(12),
      DOBDO(15 downto 1) => NLW_BIN_out_i_reg_3_DOBDO_UNCONNECTED(15 downto 1),
      DOBDO(0) => BIN_out(12),
      DOPADOP(1 downto 0) => NLW_BIN_out_i_reg_3_DOPADOP_UNCONNECTED(1 downto 0),
      DOPBDOP(1 downto 0) => NLW_BIN_out_i_reg_3_DOPBDOP_UNCONNECTED(1 downto 0),
      ENARDEN => ena,
      ENBWREN => ena,
      REGCEAREGCE => ena,
      REGCEB => ena,
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      WEA(1 downto 0) => B"00",
      WEBWE(3 downto 0) => B"0000"
    );
\LFSR_in_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => \LFSR_in_i_reg[12]_0\(0),
      Q => \LFSR_in_i_reg_n_0_[0]\,
      R => '0'
    );
\LFSR_in_i_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => \LFSR_in_i_reg[12]_0\(10),
      Q => \LFSR_in_i_reg_n_0_[10]\,
      R => '0'
    );
\LFSR_in_i_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => \LFSR_in_i_reg[12]_0\(11),
      Q => \LFSR_in_i_reg_n_0_[11]\,
      R => '0'
    );
\LFSR_in_i_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => \LFSR_in_i_reg[12]_0\(12),
      Q => \LFSR_in_i_reg_n_0_[12]\,
      R => '0'
    );
\LFSR_in_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => \LFSR_in_i_reg[12]_0\(1),
      Q => \LFSR_in_i_reg_n_0_[1]\,
      R => '0'
    );
\LFSR_in_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => \LFSR_in_i_reg[12]_0\(2),
      Q => \LFSR_in_i_reg_n_0_[2]\,
      R => '0'
    );
\LFSR_in_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => \LFSR_in_i_reg[12]_0\(3),
      Q => \LFSR_in_i_reg_n_0_[3]\,
      R => '0'
    );
\LFSR_in_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => \LFSR_in_i_reg[12]_0\(4),
      Q => \LFSR_in_i_reg_n_0_[4]\,
      R => '0'
    );
\LFSR_in_i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => \LFSR_in_i_reg[12]_0\(5),
      Q => \LFSR_in_i_reg_n_0_[5]\,
      R => '0'
    );
\LFSR_in_i_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => \LFSR_in_i_reg[12]_0\(6),
      Q => \LFSR_in_i_reg_n_0_[6]\,
      R => '0'
    );
\LFSR_in_i_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => \LFSR_in_i_reg[12]_0\(7),
      Q => \LFSR_in_i_reg_n_0_[7]\,
      R => '0'
    );
\LFSR_in_i_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => \LFSR_in_i_reg[12]_0\(8),
      Q => \LFSR_in_i_reg_n_0_[8]\,
      R => '0'
    );
\LFSR_in_i_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => ena,
      D => \LFSR_in_i_reg[12]_0\(9),
      Q => \LFSR_in_i_reg_n_0_[9]\,
      R => '0'
    );
\datmem_data_o[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out_i_reg(0),
      I1 => \writer_state__0\(0),
      I2 => \LFSR_in_i_reg[12]_0\(0),
      O => D(0)
    );
\datmem_data_o[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out_i_reg(10),
      I1 => \writer_state__0\(0),
      I2 => \LFSR_in_i_reg[12]_0\(10),
      O => D(10)
    );
\datmem_data_o[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out_i_reg(11),
      I1 => \writer_state__0\(0),
      I2 => \LFSR_in_i_reg[12]_0\(11),
      O => D(11)
    );
\datmem_data_o[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out_i_reg(12),
      I1 => \writer_state__0\(0),
      I2 => \LFSR_in_i_reg[12]_0\(12),
      O => D(12)
    );
\datmem_data_o[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out(0),
      I1 => \writer_state__0\(0),
      I2 => \datmem_data_o_reg[28]\(0),
      O => D(13)
    );
\datmem_data_o[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out(1),
      I1 => \writer_state__0\(0),
      I2 => \datmem_data_o_reg[28]\(1),
      O => D(14)
    );
\datmem_data_o[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out(2),
      I1 => \writer_state__0\(0),
      I2 => \datmem_data_o_reg[28]\(2),
      O => D(15)
    );
\datmem_data_o[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out(3),
      I1 => \writer_state__0\(0),
      I2 => \datmem_data_o_reg[28]\(3),
      O => D(16)
    );
\datmem_data_o[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out_i_reg(1),
      I1 => \writer_state__0\(0),
      I2 => \LFSR_in_i_reg[12]_0\(1),
      O => D(1)
    );
\datmem_data_o[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out(4),
      I1 => \writer_state__0\(0),
      I2 => \datmem_data_o_reg[28]\(4),
      O => D(17)
    );
\datmem_data_o[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out(5),
      I1 => \writer_state__0\(0),
      I2 => \datmem_data_o_reg[28]\(5),
      O => D(18)
    );
\datmem_data_o[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out(6),
      I1 => \writer_state__0\(0),
      I2 => \datmem_data_o_reg[28]\(6),
      O => D(19)
    );
\datmem_data_o[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out(7),
      I1 => \writer_state__0\(0),
      I2 => \datmem_data_o_reg[28]\(7),
      O => D(20)
    );
\datmem_data_o[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out(8),
      I1 => \writer_state__0\(0),
      I2 => \datmem_data_o_reg[28]\(8),
      O => D(21)
    );
\datmem_data_o[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out(9),
      I1 => \writer_state__0\(0),
      I2 => \datmem_data_o_reg[28]\(9),
      O => D(22)
    );
\datmem_data_o[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out(10),
      I1 => \writer_state__0\(0),
      I2 => \datmem_data_o_reg[28]\(10),
      O => D(23)
    );
\datmem_data_o[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out(11),
      I1 => \writer_state__0\(0),
      I2 => \datmem_data_o_reg[28]\(11),
      O => D(24)
    );
\datmem_data_o[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out(12),
      I1 => \writer_state__0\(0),
      I2 => \datmem_data_o_reg[28]\(12),
      O => D(25)
    );
\datmem_data_o[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out_i_reg(2),
      I1 => \writer_state__0\(0),
      I2 => \LFSR_in_i_reg[12]_0\(2),
      O => D(2)
    );
\datmem_data_o[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out_i_reg(3),
      I1 => \writer_state__0\(0),
      I2 => \LFSR_in_i_reg[12]_0\(3),
      O => D(3)
    );
\datmem_data_o[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out_i_reg(4),
      I1 => \writer_state__0\(0),
      I2 => \LFSR_in_i_reg[12]_0\(4),
      O => D(4)
    );
\datmem_data_o[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out_i_reg(5),
      I1 => \writer_state__0\(0),
      I2 => \LFSR_in_i_reg[12]_0\(5),
      O => D(5)
    );
\datmem_data_o[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out_i_reg(6),
      I1 => \writer_state__0\(0),
      I2 => \LFSR_in_i_reg[12]_0\(6),
      O => D(6)
    );
\datmem_data_o[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out_i_reg(7),
      I1 => \writer_state__0\(0),
      I2 => \LFSR_in_i_reg[12]_0\(7),
      O => D(7)
    );
\datmem_data_o[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out_i_reg(8),
      I1 => \writer_state__0\(0),
      I2 => \LFSR_in_i_reg[12]_0\(8),
      O => D(8)
    );
\datmem_data_o[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => BIN_out_i_reg(9),
      I1 => \writer_state__0\(0),
      I2 => \LFSR_in_i_reg[12]_0\(9),
      O => D(9)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blok_controller_0_0_controller is
  port (
    cfgmem_ena_o : out STD_LOGIC;
    cfgmem_addr_o : out STD_LOGIC_VECTOR ( 30 downto 0 );
    datmem_data_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
    datmem_wea_o : out STD_LOGIC_VECTOR ( 0 to 0 );
    datmem_addr_o : out STD_LOGIC_VECTOR ( 30 downto 0 );
    sck_o : out STD_LOGIC;
    cs_o : out STD_LOGIC;
    mosi_o : out STD_LOGIC;
    ctl_clk_i : in STD_LOGIC;
    ctl_data_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
    miso_i : in STD_LOGIC;
    cfgmem_data_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
    ctl_ena_i : in STD_LOGIC;
    ctl_rst_i : in STD_LOGIC;
    ctl_addr_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
    ctl_wea_i : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of blok_controller_0_0_controller : entity is "controller";
end blok_controller_0_0_controller;

architecture STRUCTURE of blok_controller_0_0_controller is
  signal \FSM_sequential_writer_state[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_writer_state[1]_i_1_n_0\ : STD_LOGIC;
  signal LFSR_in : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal LFSR_in_i : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \cfgmem_addr_o[31]_i_1_n_0\ : STD_LOGIC;
  signal cfgmem_ena_o_i_1_n_0 : STD_LOGIC;
  signal cfgmem_ena_o_i_2_n_0 : STD_LOGIC;
  signal \clk_counter0_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \clk_counter0_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \clk_counter0_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \clk_counter0_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \clk_counter0_carry__0_n_0\ : STD_LOGIC;
  signal \clk_counter0_carry__0_n_1\ : STD_LOGIC;
  signal \clk_counter0_carry__0_n_2\ : STD_LOGIC;
  signal \clk_counter0_carry__0_n_3\ : STD_LOGIC;
  signal \clk_counter0_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \clk_counter0_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \clk_counter0_carry__1_i_3_n_0\ : STD_LOGIC;
  signal \clk_counter0_carry__1_n_1\ : STD_LOGIC;
  signal \clk_counter0_carry__1_n_2\ : STD_LOGIC;
  signal \clk_counter0_carry__1_n_3\ : STD_LOGIC;
  signal clk_counter0_carry_i_1_n_0 : STD_LOGIC;
  signal clk_counter0_carry_i_2_n_0 : STD_LOGIC;
  signal clk_counter0_carry_i_3_n_0 : STD_LOGIC;
  signal clk_counter0_carry_i_4_n_0 : STD_LOGIC;
  signal clk_counter0_carry_n_0 : STD_LOGIC;
  signal clk_counter0_carry_n_1 : STD_LOGIC;
  signal clk_counter0_carry_n_2 : STD_LOGIC;
  signal clk_counter0_carry_n_3 : STD_LOGIC;
  signal \clk_counter[0]_i_1_n_0\ : STD_LOGIC;
  signal \clk_counter[0]_i_3_n_0\ : STD_LOGIC;
  signal clk_counter_reg : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \clk_counter_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \clk_counter_reg[0]_i_2_n_1\ : STD_LOGIC;
  signal \clk_counter_reg[0]_i_2_n_2\ : STD_LOGIC;
  signal \clk_counter_reg[0]_i_2_n_3\ : STD_LOGIC;
  signal \clk_counter_reg[0]_i_2_n_4\ : STD_LOGIC;
  signal \clk_counter_reg[0]_i_2_n_5\ : STD_LOGIC;
  signal \clk_counter_reg[0]_i_2_n_6\ : STD_LOGIC;
  signal \clk_counter_reg[0]_i_2_n_7\ : STD_LOGIC;
  signal \clk_counter_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \clk_counter_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \clk_counter_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \clk_counter_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \clk_counter_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \clk_counter_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \clk_counter_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \clk_counter_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \clk_counter_reg[16]_i_1_n_0\ : STD_LOGIC;
  signal \clk_counter_reg[16]_i_1_n_1\ : STD_LOGIC;
  signal \clk_counter_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \clk_counter_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \clk_counter_reg[16]_i_1_n_4\ : STD_LOGIC;
  signal \clk_counter_reg[16]_i_1_n_5\ : STD_LOGIC;
  signal \clk_counter_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \clk_counter_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \clk_counter_reg[20]_i_1_n_0\ : STD_LOGIC;
  signal \clk_counter_reg[20]_i_1_n_1\ : STD_LOGIC;
  signal \clk_counter_reg[20]_i_1_n_2\ : STD_LOGIC;
  signal \clk_counter_reg[20]_i_1_n_3\ : STD_LOGIC;
  signal \clk_counter_reg[20]_i_1_n_4\ : STD_LOGIC;
  signal \clk_counter_reg[20]_i_1_n_5\ : STD_LOGIC;
  signal \clk_counter_reg[20]_i_1_n_6\ : STD_LOGIC;
  signal \clk_counter_reg[20]_i_1_n_7\ : STD_LOGIC;
  signal \clk_counter_reg[24]_i_1_n_0\ : STD_LOGIC;
  signal \clk_counter_reg[24]_i_1_n_1\ : STD_LOGIC;
  signal \clk_counter_reg[24]_i_1_n_2\ : STD_LOGIC;
  signal \clk_counter_reg[24]_i_1_n_3\ : STD_LOGIC;
  signal \clk_counter_reg[24]_i_1_n_4\ : STD_LOGIC;
  signal \clk_counter_reg[24]_i_1_n_5\ : STD_LOGIC;
  signal \clk_counter_reg[24]_i_1_n_6\ : STD_LOGIC;
  signal \clk_counter_reg[24]_i_1_n_7\ : STD_LOGIC;
  signal \clk_counter_reg[28]_i_1_n_1\ : STD_LOGIC;
  signal \clk_counter_reg[28]_i_1_n_2\ : STD_LOGIC;
  signal \clk_counter_reg[28]_i_1_n_3\ : STD_LOGIC;
  signal \clk_counter_reg[28]_i_1_n_4\ : STD_LOGIC;
  signal \clk_counter_reg[28]_i_1_n_5\ : STD_LOGIC;
  signal \clk_counter_reg[28]_i_1_n_6\ : STD_LOGIC;
  signal \clk_counter_reg[28]_i_1_n_7\ : STD_LOGIC;
  signal \clk_counter_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \clk_counter_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \clk_counter_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \clk_counter_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \clk_counter_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \clk_counter_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \clk_counter_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \clk_counter_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \clk_counter_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \clk_counter_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \clk_counter_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \clk_counter_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \clk_counter_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \clk_counter_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \clk_counter_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \clk_counter_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal clk_en : STD_LOGIC;
  signal clk_update_counter_i_1_n_0 : STD_LOGIC;
  signal clk_update_counter_reg_n_0 : STD_LOGIC;
  signal \^cs_o\ : STD_LOGIC;
  signal cs_o_i_1_n_0 : STD_LOGIC;
  signal ctl_reg_bits_to_write : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \ctl_reg_bits_to_write[15]_i_1_n_0\ : STD_LOGIC;
  signal \ctl_reg_bits_to_write[23]_i_1_n_0\ : STD_LOGIC;
  signal \ctl_reg_bits_to_write[31]_i_1_n_0\ : STD_LOGIC;
  signal \ctl_reg_bits_to_write[7]_i_1_n_0\ : STD_LOGIC;
  signal \ctl_reg_control[0]_i_1_n_0\ : STD_LOGIC;
  signal \ctl_reg_control[0]_i_2_n_0\ : STD_LOGIC;
  signal ctl_reg_control_event : STD_LOGIC;
  signal ctl_reg_control_event_i_1_n_0 : STD_LOGIC;
  signal \ctl_reg_control_reg_n_0_[0]\ : STD_LOGIC;
  signal ctl_reg_downcounter : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \ctl_reg_downcounter[15]_i_1_n_0\ : STD_LOGIC;
  signal \ctl_reg_downcounter[23]_i_1_n_0\ : STD_LOGIC;
  signal \ctl_reg_downcounter[31]_i_1_n_0\ : STD_LOGIC;
  signal \ctl_reg_downcounter[31]_i_2_n_0\ : STD_LOGIC;
  signal \ctl_reg_downcounter[31]_i_3_n_0\ : STD_LOGIC;
  signal \ctl_reg_downcounter[31]_i_4_n_0\ : STD_LOGIC;
  signal \ctl_reg_downcounter[31]_i_5_n_0\ : STD_LOGIC;
  signal \ctl_reg_downcounter[31]_i_6_n_0\ : STD_LOGIC;
  signal \ctl_reg_downcounter[31]_i_7_n_0\ : STD_LOGIC;
  signal \ctl_reg_downcounter[31]_i_8_n_0\ : STD_LOGIC;
  signal \ctl_reg_downcounter[31]_i_9_n_0\ : STD_LOGIC;
  signal \ctl_reg_downcounter[7]_i_1_n_0\ : STD_LOGIC;
  signal \ctl_reg_options[0]_i_1_n_0\ : STD_LOGIC;
  signal \ctl_reg_options[1]_i_1_n_0\ : STD_LOGIC;
  signal \ctl_reg_options[1]_i_2_n_0\ : STD_LOGIC;
  signal \ctl_reg_options_reg_n_0_[0]\ : STD_LOGIC;
  signal data0 : STD_LOGIC;
  signal \datmem_addr_o[31]_i_1_n_0\ : STD_LOGIC;
  signal datmem_data_o0_in : STD_LOGIC_VECTOR ( 28 downto 0 );
  signal \datmem_data_o[31]_i_1_n_0\ : STD_LOGIC;
  signal \datmem_data_o[31]_i_2_n_0\ : STD_LOGIC;
  signal datmem_ena_o_i_1_n_0 : STD_LOGIC;
  signal decode_enable_i_1_n_0 : STD_LOGIC;
  signal ena : STD_LOGIC;
  signal fsm_State : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \fsm_State_reg_n_0_[0]\ : STD_LOGIC;
  signal \fsm_State_reg_n_0_[1]\ : STD_LOGIC;
  signal \fsm_State_reg_n_0_[2]\ : STD_LOGIC;
  signal fsm_bits_sent : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \fsm_bits_sent[0]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_bits_sent[31]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[16]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[16]_i_1_n_1\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[20]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[20]_i_1_n_1\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[20]_i_1_n_2\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[20]_i_1_n_3\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[24]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[24]_i_1_n_1\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[24]_i_1_n_2\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[24]_i_1_n_3\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[28]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[28]_i_1_n_1\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[28]_i_1_n_2\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[28]_i_1_n_3\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[31]_i_3_n_2\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[31]_i_3_n_3\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \fsm_bits_sent_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \fsm_skip_counter[0]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_skip_counter[31]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_skip_counter[31]_i_3_n_0\ : STD_LOGIC;
  signal \fsm_skip_counter[31]_i_4_n_0\ : STD_LOGIC;
  signal \fsm_skip_counter[31]_i_5_n_0\ : STD_LOGIC;
  signal \fsm_skip_counter[31]_i_6_n_0\ : STD_LOGIC;
  signal \fsm_skip_counter[31]_i_7_n_0\ : STD_LOGIC;
  signal \fsm_skip_counter[31]_i_8_n_0\ : STD_LOGIC;
  signal \fsm_skip_counter[31]_i_9_n_0\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[16]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[16]_i_1_n_1\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[16]_i_1_n_4\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[16]_i_1_n_5\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[20]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[20]_i_1_n_1\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[20]_i_1_n_2\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[20]_i_1_n_3\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[20]_i_1_n_4\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[20]_i_1_n_5\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[20]_i_1_n_6\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[20]_i_1_n_7\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[24]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[24]_i_1_n_1\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[24]_i_1_n_2\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[24]_i_1_n_3\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[24]_i_1_n_4\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[24]_i_1_n_5\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[24]_i_1_n_6\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[24]_i_1_n_7\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[28]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[28]_i_1_n_1\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[28]_i_1_n_2\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[28]_i_1_n_3\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[28]_i_1_n_4\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[28]_i_1_n_5\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[28]_i_1_n_6\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[28]_i_1_n_7\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[31]_i_2_n_2\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[31]_i_2_n_3\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[31]_i_2_n_5\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[31]_i_2_n_6\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[31]_i_2_n_7\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \fsm_skip_counter_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[0]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[10]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[11]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[12]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[13]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[14]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[15]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[16]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[17]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[18]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[19]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[1]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[20]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[21]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[22]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[23]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[24]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[25]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[26]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[27]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[28]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[29]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[2]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[30]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[31]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[3]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[4]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[5]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[6]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[7]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[8]\ : STD_LOGIC;
  signal \fsm_skip_counter_reg_n_0_[9]\ : STD_LOGIC;
  signal \fsm_start_ack__0\ : STD_LOGIC;
  signal fsm_start_ack_i_1_n_0 : STD_LOGIC;
  signal \i__carry_i_1__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_1_n_0\ : STD_LOGIC;
  signal in9 : STD_LOGIC_VECTOR ( 31 downto 1 );
  signal \ipc_data1_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \ipc_data1_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \ipc_data1_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \ipc_data1_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \ipc_data1_carry__0_n_0\ : STD_LOGIC;
  signal \ipc_data1_carry__0_n_1\ : STD_LOGIC;
  signal \ipc_data1_carry__0_n_2\ : STD_LOGIC;
  signal \ipc_data1_carry__0_n_3\ : STD_LOGIC;
  signal \ipc_data1_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \ipc_data1_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \ipc_data1_carry__1_i_3_n_0\ : STD_LOGIC;
  signal \ipc_data1_carry__1_n_1\ : STD_LOGIC;
  signal \ipc_data1_carry__1_n_2\ : STD_LOGIC;
  signal \ipc_data1_carry__1_n_3\ : STD_LOGIC;
  signal ipc_data1_carry_i_1_n_0 : STD_LOGIC;
  signal ipc_data1_carry_i_2_n_0 : STD_LOGIC;
  signal ipc_data1_carry_i_3_n_0 : STD_LOGIC;
  signal ipc_data1_carry_i_4_n_0 : STD_LOGIC;
  signal ipc_data1_carry_n_0 : STD_LOGIC;
  signal ipc_data1_carry_n_1 : STD_LOGIC;
  signal ipc_data1_carry_n_2 : STD_LOGIC;
  signal ipc_data1_carry_n_3 : STD_LOGIC;
  signal \ipc_data[30]_i_1_n_0\ : STD_LOGIC;
  signal \ipc_data[31]_i_1_n_0\ : STD_LOGIC;
  signal \ipc_data[31]_i_2_n_0\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[0]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[10]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[11]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[12]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[13]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[14]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[15]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[1]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[29]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[2]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[30]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[31]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[3]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[4]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[5]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[6]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[7]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[8]\ : STD_LOGIC;
  signal \ipc_data_reg_n_0_[9]\ : STD_LOGIC;
  signal ipc_reset : STD_LOGIC;
  signal ipc_reset_i_1_n_0 : STD_LOGIC;
  signal ipc_write : STD_LOGIC;
  signal ipc_write_i_1_n_0 : STD_LOGIC;
  signal minusOp : STD_LOGIC_VECTOR ( 31 downto 1 );
  signal \minusOp_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \minusOp_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \minusOp_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \minusOp_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \minusOp_carry__0_n_0\ : STD_LOGIC;
  signal \minusOp_carry__0_n_1\ : STD_LOGIC;
  signal \minusOp_carry__0_n_2\ : STD_LOGIC;
  signal \minusOp_carry__0_n_3\ : STD_LOGIC;
  signal \minusOp_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \minusOp_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \minusOp_carry__1_i_3_n_0\ : STD_LOGIC;
  signal \minusOp_carry__1_i_4_n_0\ : STD_LOGIC;
  signal \minusOp_carry__1_n_0\ : STD_LOGIC;
  signal \minusOp_carry__1_n_1\ : STD_LOGIC;
  signal \minusOp_carry__1_n_2\ : STD_LOGIC;
  signal \minusOp_carry__1_n_3\ : STD_LOGIC;
  signal \minusOp_carry__2_i_1_n_0\ : STD_LOGIC;
  signal \minusOp_carry__2_i_2_n_0\ : STD_LOGIC;
  signal \minusOp_carry__2_i_3_n_0\ : STD_LOGIC;
  signal \minusOp_carry__2_i_4_n_0\ : STD_LOGIC;
  signal \minusOp_carry__2_n_0\ : STD_LOGIC;
  signal \minusOp_carry__2_n_1\ : STD_LOGIC;
  signal \minusOp_carry__2_n_2\ : STD_LOGIC;
  signal \minusOp_carry__2_n_3\ : STD_LOGIC;
  signal \minusOp_carry__3_i_1_n_0\ : STD_LOGIC;
  signal \minusOp_carry__3_i_2_n_0\ : STD_LOGIC;
  signal \minusOp_carry__3_i_3_n_0\ : STD_LOGIC;
  signal \minusOp_carry__3_i_4_n_0\ : STD_LOGIC;
  signal \minusOp_carry__3_n_0\ : STD_LOGIC;
  signal \minusOp_carry__3_n_1\ : STD_LOGIC;
  signal \minusOp_carry__3_n_2\ : STD_LOGIC;
  signal \minusOp_carry__3_n_3\ : STD_LOGIC;
  signal \minusOp_carry__4_i_1_n_0\ : STD_LOGIC;
  signal \minusOp_carry__4_i_2_n_0\ : STD_LOGIC;
  signal \minusOp_carry__4_i_3_n_0\ : STD_LOGIC;
  signal \minusOp_carry__4_i_4_n_0\ : STD_LOGIC;
  signal \minusOp_carry__4_n_0\ : STD_LOGIC;
  signal \minusOp_carry__4_n_1\ : STD_LOGIC;
  signal \minusOp_carry__4_n_2\ : STD_LOGIC;
  signal \minusOp_carry__4_n_3\ : STD_LOGIC;
  signal \minusOp_carry__5_i_1_n_0\ : STD_LOGIC;
  signal \minusOp_carry__5_i_2_n_0\ : STD_LOGIC;
  signal \minusOp_carry__5_i_3_n_0\ : STD_LOGIC;
  signal \minusOp_carry__5_i_4_n_0\ : STD_LOGIC;
  signal \minusOp_carry__5_n_0\ : STD_LOGIC;
  signal \minusOp_carry__5_n_1\ : STD_LOGIC;
  signal \minusOp_carry__5_n_2\ : STD_LOGIC;
  signal \minusOp_carry__5_n_3\ : STD_LOGIC;
  signal \minusOp_carry__6_i_1_n_0\ : STD_LOGIC;
  signal \minusOp_carry__6_i_2_n_0\ : STD_LOGIC;
  signal \minusOp_carry__6_i_3_n_0\ : STD_LOGIC;
  signal \minusOp_carry__6_n_2\ : STD_LOGIC;
  signal \minusOp_carry__6_n_3\ : STD_LOGIC;
  signal minusOp_carry_i_1_n_0 : STD_LOGIC;
  signal minusOp_carry_i_2_n_0 : STD_LOGIC;
  signal minusOp_carry_i_3_n_0 : STD_LOGIC;
  signal minusOp_carry_i_4_n_0 : STD_LOGIC;
  signal minusOp_carry_n_0 : STD_LOGIC;
  signal minusOp_carry_n_1 : STD_LOGIC;
  signal minusOp_carry_n_2 : STD_LOGIC;
  signal minusOp_carry_n_3 : STD_LOGIC;
  signal misobitptr : STD_LOGIC;
  signal \misobitptr[0]_i_1_n_0\ : STD_LOGIC;
  signal \misobitptr[1]_i_1_n_0\ : STD_LOGIC;
  signal \misobitptr[2]_i_1_n_0\ : STD_LOGIC;
  signal \misobitptr[3]_i_1_n_0\ : STD_LOGIC;
  signal \misobitptr[4]_i_1_n_0\ : STD_LOGIC;
  signal \misobitptr[4]_i_2_n_0\ : STD_LOGIC;
  signal \misobitptr[4]_i_3_n_0\ : STD_LOGIC;
  signal \misobitptr[4]_i_4_n_0\ : STD_LOGIC;
  signal \misobitptr[4]_i_5_n_0\ : STD_LOGIC;
  signal \misobitptr_reg_n_0_[0]\ : STD_LOGIC;
  signal \misobitptr_reg_n_0_[1]\ : STD_LOGIC;
  signal \misobitptr_reg_n_0_[2]\ : STD_LOGIC;
  signal \misobitptr_reg_n_0_[3]\ : STD_LOGIC;
  signal \misobitptr_reg_n_0_[4]\ : STD_LOGIC;
  signal \misodata[0]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[0]_i_2_n_0\ : STD_LOGIC;
  signal \misodata[10]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[11]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[12]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[13]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[14]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[15]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[15]_i_2_n_0\ : STD_LOGIC;
  signal \misodata[16]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[17]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[18]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[19]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[1]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[20]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[21]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[22]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[23]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[23]_i_2_n_0\ : STD_LOGIC;
  signal \misodata[23]_i_3_n_0\ : STD_LOGIC;
  signal \misodata[24]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[24]_i_2_n_0\ : STD_LOGIC;
  signal \misodata[25]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[25]_i_2_n_0\ : STD_LOGIC;
  signal \misodata[26]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[26]_i_2_n_0\ : STD_LOGIC;
  signal \misodata[27]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[27]_i_2_n_0\ : STD_LOGIC;
  signal \misodata[28]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[28]_i_2_n_0\ : STD_LOGIC;
  signal \misodata[29]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[29]_i_2_n_0\ : STD_LOGIC;
  signal \misodata[2]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[30]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[30]_i_2_n_0\ : STD_LOGIC;
  signal \misodata[30]_i_3_n_0\ : STD_LOGIC;
  signal \misodata[30]_i_4_n_0\ : STD_LOGIC;
  signal \misodata[30]_i_5_n_0\ : STD_LOGIC;
  signal \misodata[31]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[31]_i_2_n_0\ : STD_LOGIC;
  signal \misodata[3]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[4]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[5]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[6]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[7]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[7]_i_2_n_0\ : STD_LOGIC;
  signal \misodata[8]_i_1_n_0\ : STD_LOGIC;
  signal \misodata[9]_i_1_n_0\ : STD_LOGIC;
  signal \misodata_reg_n_0_[0]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[10]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[11]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[12]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[13]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[14]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[15]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[16]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[17]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[18]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[19]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[1]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[20]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[21]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[22]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[23]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[24]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[25]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[26]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[27]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[28]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[29]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[2]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[30]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[3]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[4]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[5]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[6]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[7]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[8]\ : STD_LOGIC;
  signal \misodata_reg_n_0_[9]\ : STD_LOGIC;
  signal \^mosi_o\ : STD_LOGIC;
  signal mosi_o_i_10_n_0 : STD_LOGIC;
  signal mosi_o_i_11_n_0 : STD_LOGIC;
  signal mosi_o_i_12_n_0 : STD_LOGIC;
  signal mosi_o_i_13_n_0 : STD_LOGIC;
  signal mosi_o_i_14_n_0 : STD_LOGIC;
  signal mosi_o_i_15_n_0 : STD_LOGIC;
  signal mosi_o_i_1_n_0 : STD_LOGIC;
  signal mosi_o_i_8_n_0 : STD_LOGIC;
  signal mosi_o_i_9_n_0 : STD_LOGIC;
  signal mosi_o_reg_i_2_n_0 : STD_LOGIC;
  signal mosi_o_reg_i_3_n_0 : STD_LOGIC;
  signal mosi_o_reg_i_4_n_0 : STD_LOGIC;
  signal mosi_o_reg_i_5_n_0 : STD_LOGIC;
  signal mosi_o_reg_i_6_n_0 : STD_LOGIC;
  signal mosi_o_reg_i_7_n_0 : STD_LOGIC;
  signal mosiaddress : STD_LOGIC;
  signal \mosiaddress[31]_i_1_n_0\ : STD_LOGIC;
  signal \mosiaddress[31]_i_3_n_0\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[10]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[11]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[12]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[13]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[14]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[15]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[16]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[17]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[18]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[19]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[1]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[20]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[21]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[22]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[23]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[24]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[25]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[26]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[27]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[28]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[29]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[2]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[30]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[31]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[3]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[4]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[5]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[6]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[7]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[8]\ : STD_LOGIC;
  signal \mosiaddress_reg_n_0_[9]\ : STD_LOGIC;
  signal \mosibitptr[0]_i_1_n_0\ : STD_LOGIC;
  signal \mosibitptr[1]_i_1_n_0\ : STD_LOGIC;
  signal \mosibitptr[2]_i_1_n_0\ : STD_LOGIC;
  signal \mosibitptr[3]_i_1_n_0\ : STD_LOGIC;
  signal \mosibitptr[4]_i_1_n_0\ : STD_LOGIC;
  signal \mosibitptr[4]_i_2_n_0\ : STD_LOGIC;
  signal \mosibitptr[4]_i_3_n_0\ : STD_LOGIC;
  signal mosidata : STD_LOGIC;
  signal \mosidata[31]_i_1_n_0\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[0]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[10]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[11]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[12]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[13]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[14]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[15]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[16]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[17]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[18]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[19]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[1]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[20]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[21]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[22]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[23]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[24]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[25]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[26]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[27]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[28]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[29]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[2]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[30]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[31]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[3]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[4]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[5]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[6]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[7]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[8]\ : STD_LOGIC;
  signal \mosidata_reg_n_0_[9]\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal plusOp : STD_LOGIC_VECTOR ( 31 downto 1 );
  signal \plusOp_inferred__1/i__carry__0_n_0\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__0_n_1\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__0_n_2\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__0_n_3\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__0_n_4\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__0_n_5\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__0_n_6\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__0_n_7\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__1_n_0\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__1_n_1\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__1_n_2\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__1_n_3\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__1_n_4\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__1_n_5\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__1_n_6\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__1_n_7\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__2_n_0\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__2_n_1\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__2_n_2\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__2_n_3\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__2_n_4\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__2_n_5\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__2_n_6\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__2_n_7\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__3_n_0\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__3_n_1\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__3_n_2\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__3_n_3\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__3_n_4\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__3_n_5\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__3_n_6\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__3_n_7\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__4_n_0\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__4_n_1\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__4_n_2\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__4_n_3\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__4_n_4\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__4_n_5\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__4_n_6\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__4_n_7\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__5_n_0\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__5_n_1\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__5_n_2\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__5_n_3\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__5_n_4\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__5_n_5\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__5_n_6\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__5_n_7\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__6_n_2\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__6_n_3\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__6_n_5\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__6_n_6\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry__6_n_7\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry_n_0\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry_n_1\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry_n_2\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry_n_3\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry_n_4\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry_n_5\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry_n_6\ : STD_LOGIC;
  signal \plusOp_inferred__1/i__carry_n_7\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__0_n_0\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__0_n_1\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__0_n_2\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__0_n_3\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__1_n_0\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__1_n_1\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__1_n_2\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__1_n_3\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__2_n_0\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__2_n_1\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__2_n_2\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__2_n_3\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__3_n_0\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__3_n_1\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__3_n_2\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__3_n_3\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__4_n_0\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__4_n_1\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__4_n_2\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__4_n_3\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__5_n_0\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__5_n_1\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__5_n_2\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__5_n_3\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__6_n_2\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry__6_n_3\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry_n_0\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry_n_1\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry_n_2\ : STD_LOGIC;
  signal \plusOp_inferred__4/i__carry_n_3\ : STD_LOGIC;
  signal \^sck_o\ : STD_LOGIC;
  signal sck_o_i_1_n_0 : STD_LOGIC;
  signal sel0 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \sync_reg_control[0]_i_1_n_0\ : STD_LOGIC;
  signal \sync_reg_control_reg_n_0_[0]\ : STD_LOGIC;
  signal \writer_address[31]_i_1_n_0\ : STD_LOGIC;
  signal \writer_address[31]_i_2_n_0\ : STD_LOGIC;
  signal \writer_address__0\ : STD_LOGIC_VECTOR ( 31 downto 1 );
  signal \writer_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_clk_counter0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_clk_counter0_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_clk_counter0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_clk_counter0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_clk_counter_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_fsm_bits_sent_reg[31]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_fsm_bits_sent_reg[31]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_fsm_skip_counter_reg[31]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_fsm_skip_counter_reg[31]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal NLW_ipc_data1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_ipc_data1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_ipc_data1_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_ipc_data1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_minusOp_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_minusOp_carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_plusOp_inferred__1/i__carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_plusOp_inferred__1/i__carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_plusOp_inferred__4/i__carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_plusOp_inferred__4/i__carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_writer_state_reg[0]\ : label is "writer_state_2:11,writer_state_idle:00,writer_state_1:10,writer_state_decode:01";
  attribute FSM_ENCODED_STATES of \FSM_sequential_writer_state_reg[1]\ : label is "writer_state_2:11,writer_state_idle:00,writer_state_1:10,writer_state_decode:01";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of cfgmem_ena_o_i_1 : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of cfgmem_ena_o_i_2 : label is "soft_lutpair13";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \clk_counter_reg[0]_i_2\ : label is 11;
  attribute ADDER_THRESHOLD of \clk_counter_reg[12]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \clk_counter_reg[16]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \clk_counter_reg[20]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \clk_counter_reg[24]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \clk_counter_reg[28]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \clk_counter_reg[4]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \clk_counter_reg[8]_i_1\ : label is 11;
  attribute SOFT_HLUTNM of \ctl_reg_options[0]_i_1\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \fsm_State[0]_i_1\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \fsm_State[1]_i_1\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \fsm_State[2]_i_1\ : label is "soft_lutpair20";
  attribute ADDER_THRESHOLD of \fsm_bits_sent_reg[12]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \fsm_bits_sent_reg[16]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \fsm_bits_sent_reg[20]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \fsm_bits_sent_reg[24]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \fsm_bits_sent_reg[28]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \fsm_bits_sent_reg[31]_i_3\ : label is 35;
  attribute ADDER_THRESHOLD of \fsm_bits_sent_reg[4]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \fsm_bits_sent_reg[8]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \fsm_skip_counter_reg[12]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \fsm_skip_counter_reg[16]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \fsm_skip_counter_reg[20]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \fsm_skip_counter_reg[24]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \fsm_skip_counter_reg[28]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \fsm_skip_counter_reg[31]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \fsm_skip_counter_reg[4]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \fsm_skip_counter_reg[8]_i_1\ : label is 35;
  attribute SOFT_HLUTNM of \ipc_data[31]_i_1\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of ipc_reset_i_1 : label is "soft_lutpair16";
  attribute ADDER_THRESHOLD of minusOp_carry : label is 35;
  attribute ADDER_THRESHOLD of \minusOp_carry__0\ : label is 35;
  attribute ADDER_THRESHOLD of \minusOp_carry__1\ : label is 35;
  attribute ADDER_THRESHOLD of \minusOp_carry__2\ : label is 35;
  attribute ADDER_THRESHOLD of \minusOp_carry__3\ : label is 35;
  attribute ADDER_THRESHOLD of \minusOp_carry__4\ : label is 35;
  attribute ADDER_THRESHOLD of \minusOp_carry__5\ : label is 35;
  attribute ADDER_THRESHOLD of \minusOp_carry__6\ : label is 35;
  attribute SOFT_HLUTNM of \misobitptr[2]_i_1\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \misobitptr[3]_i_1\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \misobitptr[4]_i_2\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \misobitptr[4]_i_5\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \misodata[0]_i_2\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \misodata[15]_i_2\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \misodata[23]_i_2\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \misodata[23]_i_3\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \misodata[24]_i_2\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \misodata[25]_i_2\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \misodata[26]_i_2\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \misodata[27]_i_2\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \misodata[29]_i_2\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \misodata[30]_i_4\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \misodata[30]_i_5\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \misodata[31]_i_2\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \misodata[7]_i_2\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \mosibitptr[2]_i_1\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \mosibitptr[3]_i_1\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \mosibitptr[4]_i_3\ : label is "soft_lutpair13";
  attribute ADDER_THRESHOLD of \plusOp_inferred__1/i__carry\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_inferred__1/i__carry__0\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_inferred__1/i__carry__1\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_inferred__1/i__carry__2\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_inferred__1/i__carry__3\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_inferred__1/i__carry__4\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_inferred__1/i__carry__5\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_inferred__1/i__carry__6\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_inferred__4/i__carry\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_inferred__4/i__carry__0\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_inferred__4/i__carry__1\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_inferred__4/i__carry__2\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_inferred__4/i__carry__3\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_inferred__4/i__carry__4\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_inferred__4/i__carry__5\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_inferred__4/i__carry__6\ : label is 35;
begin
  cs_o <= \^cs_o\;
  mosi_o <= \^mosi_o\;
  sck_o <= \^sck_o\;
\FSM_sequential_writer_state[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200300032CC30CC"
    )
        port map (
      I0 => p_0_in,
      I1 => \writer_state__0\(0),
      I2 => \writer_state__0\(1),
      I3 => clk_en,
      I4 => ipc_write,
      I5 => ipc_reset,
      O => \FSM_sequential_writer_state[0]_i_1_n_0\
    );
\FSM_sequential_writer_state[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3D003C003DF03CF0"
    )
        port map (
      I0 => p_0_in,
      I1 => \writer_state__0\(0),
      I2 => \writer_state__0\(1),
      I3 => clk_en,
      I4 => ipc_write,
      I5 => ipc_reset,
      O => \FSM_sequential_writer_state[1]_i_1_n_0\
    );
\FSM_sequential_writer_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \FSM_sequential_writer_state[0]_i_1_n_0\,
      Q => \writer_state__0\(0),
      R => '0'
    );
\FSM_sequential_writer_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \FSM_sequential_writer_state[1]_i_1_n_0\,
      Q => \writer_state__0\(1),
      R => '0'
    );
\cfgmem_addr_o[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10F01000"
    )
        port map (
      I0 => sel0(0),
      I1 => cfgmem_ena_o_i_2_n_0,
      I2 => \mosibitptr[4]_i_2_n_0\,
      I3 => \fsm_State_reg_n_0_[1]\,
      I4 => \sync_reg_control_reg_n_0_[0]\,
      O => \cfgmem_addr_o[31]_i_1_n_0\
    );
\cfgmem_addr_o_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[10]\,
      Q => cfgmem_addr_o(9),
      R => '0'
    );
\cfgmem_addr_o_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[11]\,
      Q => cfgmem_addr_o(10),
      R => '0'
    );
\cfgmem_addr_o_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[12]\,
      Q => cfgmem_addr_o(11),
      R => '0'
    );
\cfgmem_addr_o_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[13]\,
      Q => cfgmem_addr_o(12),
      R => '0'
    );
\cfgmem_addr_o_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[14]\,
      Q => cfgmem_addr_o(13),
      R => '0'
    );
\cfgmem_addr_o_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[15]\,
      Q => cfgmem_addr_o(14),
      R => '0'
    );
\cfgmem_addr_o_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[16]\,
      Q => cfgmem_addr_o(15),
      R => '0'
    );
\cfgmem_addr_o_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[17]\,
      Q => cfgmem_addr_o(16),
      R => '0'
    );
\cfgmem_addr_o_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[18]\,
      Q => cfgmem_addr_o(17),
      R => '0'
    );
\cfgmem_addr_o_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[19]\,
      Q => cfgmem_addr_o(18),
      R => '0'
    );
\cfgmem_addr_o_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[1]\,
      Q => cfgmem_addr_o(0),
      R => '0'
    );
\cfgmem_addr_o_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[20]\,
      Q => cfgmem_addr_o(19),
      R => '0'
    );
\cfgmem_addr_o_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[21]\,
      Q => cfgmem_addr_o(20),
      R => '0'
    );
\cfgmem_addr_o_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[22]\,
      Q => cfgmem_addr_o(21),
      R => '0'
    );
\cfgmem_addr_o_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[23]\,
      Q => cfgmem_addr_o(22),
      R => '0'
    );
\cfgmem_addr_o_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[24]\,
      Q => cfgmem_addr_o(23),
      R => '0'
    );
\cfgmem_addr_o_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[25]\,
      Q => cfgmem_addr_o(24),
      R => '0'
    );
\cfgmem_addr_o_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[26]\,
      Q => cfgmem_addr_o(25),
      R => '0'
    );
\cfgmem_addr_o_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[27]\,
      Q => cfgmem_addr_o(26),
      R => '0'
    );
\cfgmem_addr_o_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[28]\,
      Q => cfgmem_addr_o(27),
      R => '0'
    );
\cfgmem_addr_o_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[29]\,
      Q => cfgmem_addr_o(28),
      R => '0'
    );
\cfgmem_addr_o_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[2]\,
      Q => cfgmem_addr_o(1),
      R => '0'
    );
\cfgmem_addr_o_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[30]\,
      Q => cfgmem_addr_o(29),
      R => '0'
    );
\cfgmem_addr_o_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[31]\,
      Q => cfgmem_addr_o(30),
      R => '0'
    );
\cfgmem_addr_o_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[3]\,
      Q => cfgmem_addr_o(2),
      R => '0'
    );
\cfgmem_addr_o_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[4]\,
      Q => cfgmem_addr_o(3),
      R => '0'
    );
\cfgmem_addr_o_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[5]\,
      Q => cfgmem_addr_o(4),
      R => '0'
    );
\cfgmem_addr_o_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[6]\,
      Q => cfgmem_addr_o(5),
      R => '0'
    );
\cfgmem_addr_o_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[7]\,
      Q => cfgmem_addr_o(6),
      R => '0'
    );
\cfgmem_addr_o_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[8]\,
      Q => cfgmem_addr_o(7),
      R => '0'
    );
\cfgmem_addr_o_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \cfgmem_addr_o[31]_i_1_n_0\,
      D => \mosiaddress_reg_n_0_[9]\,
      Q => cfgmem_addr_o(8),
      R => '0'
    );
cfgmem_ena_o_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00101110"
    )
        port map (
      I0 => \fsm_State_reg_n_0_[2]\,
      I1 => \fsm_State_reg_n_0_[0]\,
      I2 => \sync_reg_control_reg_n_0_[0]\,
      I3 => \fsm_State_reg_n_0_[1]\,
      I4 => cfgmem_ena_o_i_2_n_0,
      O => cfgmem_ena_o_i_1_n_0
    );
cfgmem_ena_o_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => sel0(1),
      I1 => sel0(4),
      I2 => sel0(2),
      I3 => sel0(3),
      O => cfgmem_ena_o_i_2_n_0
    );
cfgmem_ena_o_reg: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => cfgmem_ena_o_i_1_n_0,
      Q => cfgmem_ena_o,
      R => '0'
    );
clk_counter0_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => clk_counter0_carry_n_0,
      CO(2) => clk_counter0_carry_n_1,
      CO(1) => clk_counter0_carry_n_2,
      CO(0) => clk_counter0_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_clk_counter0_carry_O_UNCONNECTED(3 downto 0),
      S(3) => clk_counter0_carry_i_1_n_0,
      S(2) => clk_counter0_carry_i_2_n_0,
      S(1) => clk_counter0_carry_i_3_n_0,
      S(0) => clk_counter0_carry_i_4_n_0
    );
\clk_counter0_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => clk_counter0_carry_n_0,
      CO(3) => \clk_counter0_carry__0_n_0\,
      CO(2) => \clk_counter0_carry__0_n_1\,
      CO(1) => \clk_counter0_carry__0_n_2\,
      CO(0) => \clk_counter0_carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_clk_counter0_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3) => \clk_counter0_carry__0_i_1_n_0\,
      S(2) => \clk_counter0_carry__0_i_2_n_0\,
      S(1) => \clk_counter0_carry__0_i_3_n_0\,
      S(0) => \clk_counter0_carry__0_i_4_n_0\
    );
\clk_counter0_carry__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => clk_counter_reg(21),
      I1 => ctl_reg_downcounter(21),
      I2 => ctl_reg_downcounter(23),
      I3 => clk_counter_reg(23),
      I4 => ctl_reg_downcounter(22),
      I5 => clk_counter_reg(22),
      O => \clk_counter0_carry__0_i_1_n_0\
    );
\clk_counter0_carry__0_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => clk_counter_reg(18),
      I1 => ctl_reg_downcounter(18),
      I2 => ctl_reg_downcounter(20),
      I3 => clk_counter_reg(20),
      I4 => ctl_reg_downcounter(19),
      I5 => clk_counter_reg(19),
      O => \clk_counter0_carry__0_i_2_n_0\
    );
\clk_counter0_carry__0_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => clk_counter_reg(15),
      I1 => ctl_reg_downcounter(15),
      I2 => ctl_reg_downcounter(17),
      I3 => clk_counter_reg(17),
      I4 => ctl_reg_downcounter(16),
      I5 => clk_counter_reg(16),
      O => \clk_counter0_carry__0_i_3_n_0\
    );
\clk_counter0_carry__0_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => clk_counter_reg(12),
      I1 => ctl_reg_downcounter(12),
      I2 => ctl_reg_downcounter(14),
      I3 => clk_counter_reg(14),
      I4 => ctl_reg_downcounter(13),
      I5 => clk_counter_reg(13),
      O => \clk_counter0_carry__0_i_4_n_0\
    );
\clk_counter0_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \clk_counter0_carry__0_n_0\,
      CO(3) => \NLW_clk_counter0_carry__1_CO_UNCONNECTED\(3),
      CO(2) => \clk_counter0_carry__1_n_1\,
      CO(1) => \clk_counter0_carry__1_n_2\,
      CO(0) => \clk_counter0_carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_clk_counter0_carry__1_O_UNCONNECTED\(3 downto 0),
      S(3) => '0',
      S(2) => \clk_counter0_carry__1_i_1_n_0\,
      S(1) => \clk_counter0_carry__1_i_2_n_0\,
      S(0) => \clk_counter0_carry__1_i_3_n_0\
    );
\clk_counter0_carry__1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => clk_counter_reg(30),
      I1 => ctl_reg_downcounter(30),
      I2 => clk_counter_reg(31),
      I3 => ctl_reg_downcounter(31),
      O => \clk_counter0_carry__1_i_1_n_0\
    );
\clk_counter0_carry__1_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => clk_counter_reg(27),
      I1 => ctl_reg_downcounter(27),
      I2 => ctl_reg_downcounter(29),
      I3 => clk_counter_reg(29),
      I4 => ctl_reg_downcounter(28),
      I5 => clk_counter_reg(28),
      O => \clk_counter0_carry__1_i_2_n_0\
    );
\clk_counter0_carry__1_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => clk_counter_reg(24),
      I1 => ctl_reg_downcounter(24),
      I2 => ctl_reg_downcounter(26),
      I3 => clk_counter_reg(26),
      I4 => ctl_reg_downcounter(25),
      I5 => clk_counter_reg(25),
      O => \clk_counter0_carry__1_i_3_n_0\
    );
clk_counter0_carry_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => clk_counter_reg(9),
      I1 => ctl_reg_downcounter(9),
      I2 => ctl_reg_downcounter(11),
      I3 => clk_counter_reg(11),
      I4 => ctl_reg_downcounter(10),
      I5 => clk_counter_reg(10),
      O => clk_counter0_carry_i_1_n_0
    );
clk_counter0_carry_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => clk_counter_reg(6),
      I1 => ctl_reg_downcounter(6),
      I2 => ctl_reg_downcounter(8),
      I3 => clk_counter_reg(8),
      I4 => ctl_reg_downcounter(7),
      I5 => clk_counter_reg(7),
      O => clk_counter0_carry_i_2_n_0
    );
clk_counter0_carry_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => clk_counter_reg(3),
      I1 => ctl_reg_downcounter(3),
      I2 => ctl_reg_downcounter(5),
      I3 => clk_counter_reg(5),
      I4 => ctl_reg_downcounter(4),
      I5 => clk_counter_reg(4),
      O => clk_counter0_carry_i_3_n_0
    );
clk_counter0_carry_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => clk_counter_reg(0),
      I1 => ctl_reg_downcounter(0),
      I2 => ctl_reg_downcounter(2),
      I3 => clk_counter_reg(2),
      I4 => ctl_reg_downcounter(1),
      I5 => clk_counter_reg(1),
      O => clk_counter0_carry_i_4_n_0
    );
\clk_counter[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => clk_update_counter_reg_n_0,
      I1 => \clk_counter0_carry__1_n_1\,
      O => \clk_counter[0]_i_1_n_0\
    );
\clk_counter[0]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => clk_counter_reg(0),
      O => \clk_counter[0]_i_3_n_0\
    );
\clk_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[0]_i_2_n_7\,
      Q => clk_counter_reg(0),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \clk_counter_reg[0]_i_2_n_0\,
      CO(2) => \clk_counter_reg[0]_i_2_n_1\,
      CO(1) => \clk_counter_reg[0]_i_2_n_2\,
      CO(0) => \clk_counter_reg[0]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \clk_counter_reg[0]_i_2_n_4\,
      O(2) => \clk_counter_reg[0]_i_2_n_5\,
      O(1) => \clk_counter_reg[0]_i_2_n_6\,
      O(0) => \clk_counter_reg[0]_i_2_n_7\,
      S(3 downto 1) => clk_counter_reg(3 downto 1),
      S(0) => \clk_counter[0]_i_3_n_0\
    );
\clk_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[8]_i_1_n_5\,
      Q => clk_counter_reg(10),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[8]_i_1_n_4\,
      Q => clk_counter_reg(11),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[12]_i_1_n_7\,
      Q => clk_counter_reg(12),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \clk_counter_reg[8]_i_1_n_0\,
      CO(3) => \clk_counter_reg[12]_i_1_n_0\,
      CO(2) => \clk_counter_reg[12]_i_1_n_1\,
      CO(1) => \clk_counter_reg[12]_i_1_n_2\,
      CO(0) => \clk_counter_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \clk_counter_reg[12]_i_1_n_4\,
      O(2) => \clk_counter_reg[12]_i_1_n_5\,
      O(1) => \clk_counter_reg[12]_i_1_n_6\,
      O(0) => \clk_counter_reg[12]_i_1_n_7\,
      S(3 downto 0) => clk_counter_reg(15 downto 12)
    );
\clk_counter_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[12]_i_1_n_6\,
      Q => clk_counter_reg(13),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[12]_i_1_n_5\,
      Q => clk_counter_reg(14),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[12]_i_1_n_4\,
      Q => clk_counter_reg(15),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[16]_i_1_n_7\,
      Q => clk_counter_reg(16),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \clk_counter_reg[12]_i_1_n_0\,
      CO(3) => \clk_counter_reg[16]_i_1_n_0\,
      CO(2) => \clk_counter_reg[16]_i_1_n_1\,
      CO(1) => \clk_counter_reg[16]_i_1_n_2\,
      CO(0) => \clk_counter_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \clk_counter_reg[16]_i_1_n_4\,
      O(2) => \clk_counter_reg[16]_i_1_n_5\,
      O(1) => \clk_counter_reg[16]_i_1_n_6\,
      O(0) => \clk_counter_reg[16]_i_1_n_7\,
      S(3 downto 0) => clk_counter_reg(19 downto 16)
    );
\clk_counter_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[16]_i_1_n_6\,
      Q => clk_counter_reg(17),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[16]_i_1_n_5\,
      Q => clk_counter_reg(18),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[16]_i_1_n_4\,
      Q => clk_counter_reg(19),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[0]_i_2_n_6\,
      Q => clk_counter_reg(1),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[20]_i_1_n_7\,
      Q => clk_counter_reg(20),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[20]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \clk_counter_reg[16]_i_1_n_0\,
      CO(3) => \clk_counter_reg[20]_i_1_n_0\,
      CO(2) => \clk_counter_reg[20]_i_1_n_1\,
      CO(1) => \clk_counter_reg[20]_i_1_n_2\,
      CO(0) => \clk_counter_reg[20]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \clk_counter_reg[20]_i_1_n_4\,
      O(2) => \clk_counter_reg[20]_i_1_n_5\,
      O(1) => \clk_counter_reg[20]_i_1_n_6\,
      O(0) => \clk_counter_reg[20]_i_1_n_7\,
      S(3 downto 0) => clk_counter_reg(23 downto 20)
    );
\clk_counter_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[20]_i_1_n_6\,
      Q => clk_counter_reg(21),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[20]_i_1_n_5\,
      Q => clk_counter_reg(22),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[20]_i_1_n_4\,
      Q => clk_counter_reg(23),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[24]_i_1_n_7\,
      Q => clk_counter_reg(24),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[24]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \clk_counter_reg[20]_i_1_n_0\,
      CO(3) => \clk_counter_reg[24]_i_1_n_0\,
      CO(2) => \clk_counter_reg[24]_i_1_n_1\,
      CO(1) => \clk_counter_reg[24]_i_1_n_2\,
      CO(0) => \clk_counter_reg[24]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \clk_counter_reg[24]_i_1_n_4\,
      O(2) => \clk_counter_reg[24]_i_1_n_5\,
      O(1) => \clk_counter_reg[24]_i_1_n_6\,
      O(0) => \clk_counter_reg[24]_i_1_n_7\,
      S(3 downto 0) => clk_counter_reg(27 downto 24)
    );
\clk_counter_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[24]_i_1_n_6\,
      Q => clk_counter_reg(25),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[24]_i_1_n_5\,
      Q => clk_counter_reg(26),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[24]_i_1_n_4\,
      Q => clk_counter_reg(27),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[28]_i_1_n_7\,
      Q => clk_counter_reg(28),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[28]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \clk_counter_reg[24]_i_1_n_0\,
      CO(3) => \NLW_clk_counter_reg[28]_i_1_CO_UNCONNECTED\(3),
      CO(2) => \clk_counter_reg[28]_i_1_n_1\,
      CO(1) => \clk_counter_reg[28]_i_1_n_2\,
      CO(0) => \clk_counter_reg[28]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \clk_counter_reg[28]_i_1_n_4\,
      O(2) => \clk_counter_reg[28]_i_1_n_5\,
      O(1) => \clk_counter_reg[28]_i_1_n_6\,
      O(0) => \clk_counter_reg[28]_i_1_n_7\,
      S(3 downto 0) => clk_counter_reg(31 downto 28)
    );
\clk_counter_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[28]_i_1_n_6\,
      Q => clk_counter_reg(29),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[0]_i_2_n_5\,
      Q => clk_counter_reg(2),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[28]_i_1_n_5\,
      Q => clk_counter_reg(30),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[28]_i_1_n_4\,
      Q => clk_counter_reg(31),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[0]_i_2_n_4\,
      Q => clk_counter_reg(3),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[4]_i_1_n_7\,
      Q => clk_counter_reg(4),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \clk_counter_reg[0]_i_2_n_0\,
      CO(3) => \clk_counter_reg[4]_i_1_n_0\,
      CO(2) => \clk_counter_reg[4]_i_1_n_1\,
      CO(1) => \clk_counter_reg[4]_i_1_n_2\,
      CO(0) => \clk_counter_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \clk_counter_reg[4]_i_1_n_4\,
      O(2) => \clk_counter_reg[4]_i_1_n_5\,
      O(1) => \clk_counter_reg[4]_i_1_n_6\,
      O(0) => \clk_counter_reg[4]_i_1_n_7\,
      S(3 downto 0) => clk_counter_reg(7 downto 4)
    );
\clk_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[4]_i_1_n_6\,
      Q => clk_counter_reg(5),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[4]_i_1_n_5\,
      Q => clk_counter_reg(6),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[4]_i_1_n_4\,
      Q => clk_counter_reg(7),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[8]_i_1_n_7\,
      Q => clk_counter_reg(8),
      R => \clk_counter[0]_i_1_n_0\
    );
\clk_counter_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \clk_counter_reg[4]_i_1_n_0\,
      CO(3) => \clk_counter_reg[8]_i_1_n_0\,
      CO(2) => \clk_counter_reg[8]_i_1_n_1\,
      CO(1) => \clk_counter_reg[8]_i_1_n_2\,
      CO(0) => \clk_counter_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \clk_counter_reg[8]_i_1_n_4\,
      O(2) => \clk_counter_reg[8]_i_1_n_5\,
      O(1) => \clk_counter_reg[8]_i_1_n_6\,
      O(0) => \clk_counter_reg[8]_i_1_n_7\,
      S(3 downto 0) => clk_counter_reg(11 downto 8)
    );
\clk_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter_reg[8]_i_1_n_6\,
      Q => clk_counter_reg(9),
      R => \clk_counter[0]_i_1_n_0\
    );
clk_en_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \clk_counter0_carry__1_n_1\,
      Q => clk_en,
      R => '0'
    );
clk_update_counter_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0030AAAA0000"
    )
        port map (
      I0 => clk_update_counter_reg_n_0,
      I1 => ctl_addr_i(2),
      I2 => \ctl_reg_downcounter[31]_i_2_n_0\,
      I3 => ctl_addr_i(3),
      I4 => ctl_rst_i,
      I5 => ctl_ena_i,
      O => clk_update_counter_i_1_n_0
    );
clk_update_counter_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => clk_update_counter_i_1_n_0,
      Q => clk_update_counter_reg_n_0,
      R => '0'
    );
cs_o_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFDF0050"
    )
        port map (
      I0 => \fsm_State_reg_n_0_[0]\,
      I1 => \fsm_State_reg_n_0_[2]\,
      I2 => clk_en,
      I3 => \fsm_State_reg_n_0_[1]\,
      I4 => \^cs_o\,
      O => cs_o_i_1_n_0
    );
cs_o_reg: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => cs_o_i_1_n_0,
      Q => \^cs_o\,
      R => '0'
    );
\ctl_reg_bits_to_write[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020000000000000"
    )
        port map (
      I0 => ctl_addr_i(2),
      I1 => ctl_addr_i(3),
      I2 => \ctl_reg_downcounter[31]_i_2_n_0\,
      I3 => ctl_rst_i,
      I4 => ctl_ena_i,
      I5 => ctl_wea_i(1),
      O => \ctl_reg_bits_to_write[15]_i_1_n_0\
    );
\ctl_reg_bits_to_write[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020000000000000"
    )
        port map (
      I0 => ctl_addr_i(2),
      I1 => ctl_addr_i(3),
      I2 => \ctl_reg_downcounter[31]_i_2_n_0\,
      I3 => ctl_rst_i,
      I4 => ctl_ena_i,
      I5 => ctl_wea_i(2),
      O => \ctl_reg_bits_to_write[23]_i_1_n_0\
    );
\ctl_reg_bits_to_write[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020000000000000"
    )
        port map (
      I0 => ctl_addr_i(2),
      I1 => ctl_addr_i(3),
      I2 => \ctl_reg_downcounter[31]_i_2_n_0\,
      I3 => ctl_rst_i,
      I4 => ctl_ena_i,
      I5 => ctl_wea_i(3),
      O => \ctl_reg_bits_to_write[31]_i_1_n_0\
    );
\ctl_reg_bits_to_write[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020000000000000"
    )
        port map (
      I0 => ctl_addr_i(2),
      I1 => ctl_addr_i(3),
      I2 => \ctl_reg_downcounter[31]_i_2_n_0\,
      I3 => ctl_rst_i,
      I4 => ctl_ena_i,
      I5 => ctl_wea_i(0),
      O => \ctl_reg_bits_to_write[7]_i_1_n_0\
    );
\ctl_reg_bits_to_write_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[7]_i_1_n_0\,
      D => ctl_data_i(0),
      Q => ctl_reg_bits_to_write(0),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[15]_i_1_n_0\,
      D => ctl_data_i(10),
      Q => ctl_reg_bits_to_write(10),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[15]_i_1_n_0\,
      D => ctl_data_i(11),
      Q => ctl_reg_bits_to_write(11),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[15]_i_1_n_0\,
      D => ctl_data_i(12),
      Q => ctl_reg_bits_to_write(12),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[15]_i_1_n_0\,
      D => ctl_data_i(13),
      Q => ctl_reg_bits_to_write(13),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[15]_i_1_n_0\,
      D => ctl_data_i(14),
      Q => ctl_reg_bits_to_write(14),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[15]_i_1_n_0\,
      D => ctl_data_i(15),
      Q => ctl_reg_bits_to_write(15),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[23]_i_1_n_0\,
      D => ctl_data_i(16),
      Q => ctl_reg_bits_to_write(16),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[23]_i_1_n_0\,
      D => ctl_data_i(17),
      Q => ctl_reg_bits_to_write(17),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[23]_i_1_n_0\,
      D => ctl_data_i(18),
      Q => ctl_reg_bits_to_write(18),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[23]_i_1_n_0\,
      D => ctl_data_i(19),
      Q => ctl_reg_bits_to_write(19),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[7]_i_1_n_0\,
      D => ctl_data_i(1),
      Q => ctl_reg_bits_to_write(1),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[23]_i_1_n_0\,
      D => ctl_data_i(20),
      Q => ctl_reg_bits_to_write(20),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[23]_i_1_n_0\,
      D => ctl_data_i(21),
      Q => ctl_reg_bits_to_write(21),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[23]_i_1_n_0\,
      D => ctl_data_i(22),
      Q => ctl_reg_bits_to_write(22),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[23]_i_1_n_0\,
      D => ctl_data_i(23),
      Q => ctl_reg_bits_to_write(23),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[31]_i_1_n_0\,
      D => ctl_data_i(24),
      Q => ctl_reg_bits_to_write(24),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[31]_i_1_n_0\,
      D => ctl_data_i(25),
      Q => ctl_reg_bits_to_write(25),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[31]_i_1_n_0\,
      D => ctl_data_i(26),
      Q => ctl_reg_bits_to_write(26),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[31]_i_1_n_0\,
      D => ctl_data_i(27),
      Q => ctl_reg_bits_to_write(27),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[31]_i_1_n_0\,
      D => ctl_data_i(28),
      Q => ctl_reg_bits_to_write(28),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[31]_i_1_n_0\,
      D => ctl_data_i(29),
      Q => ctl_reg_bits_to_write(29),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[7]_i_1_n_0\,
      D => ctl_data_i(2),
      Q => ctl_reg_bits_to_write(2),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[31]_i_1_n_0\,
      D => ctl_data_i(30),
      Q => ctl_reg_bits_to_write(30),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[31]_i_1_n_0\,
      D => ctl_data_i(31),
      Q => ctl_reg_bits_to_write(31),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[7]_i_1_n_0\,
      D => ctl_data_i(3),
      Q => ctl_reg_bits_to_write(3),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[7]_i_1_n_0\,
      D => ctl_data_i(4),
      Q => ctl_reg_bits_to_write(4),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[7]_i_1_n_0\,
      D => ctl_data_i(5),
      Q => ctl_reg_bits_to_write(5),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[7]_i_1_n_0\,
      D => ctl_data_i(6),
      Q => ctl_reg_bits_to_write(6),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[7]_i_1_n_0\,
      D => ctl_data_i(7),
      Q => ctl_reg_bits_to_write(7),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[15]_i_1_n_0\,
      D => ctl_data_i(8),
      Q => ctl_reg_bits_to_write(8),
      R => '0'
    );
\ctl_reg_bits_to_write_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_bits_to_write[15]_i_1_n_0\,
      D => ctl_data_i(9),
      Q => ctl_reg_bits_to_write(9),
      R => '0'
    );
\ctl_reg_control[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF800080"
    )
        port map (
      I0 => ctl_ena_i,
      I1 => \ctl_reg_downcounter[31]_i_2_n_0\,
      I2 => \ctl_reg_control[0]_i_2_n_0\,
      I3 => ctl_rst_i,
      I4 => \ctl_reg_control_reg_n_0_[0]\,
      O => \ctl_reg_control[0]_i_1_n_0\
    );
\ctl_reg_control[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => ctl_wea_i(0),
      I1 => ctl_data_i(0),
      I2 => ctl_addr_i(2),
      I3 => ctl_addr_i(3),
      O => \ctl_reg_control[0]_i_2_n_0\
    );
ctl_reg_control_event_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA00C0AAAA0000"
    )
        port map (
      I0 => ctl_reg_control_event,
      I1 => \ctl_reg_downcounter[31]_i_2_n_0\,
      I2 => ctl_addr_i(3),
      I3 => ctl_addr_i(2),
      I4 => ctl_rst_i,
      I5 => ctl_ena_i,
      O => ctl_reg_control_event_i_1_n_0
    );
ctl_reg_control_event_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => ctl_reg_control_event_i_1_n_0,
      Q => ctl_reg_control_event,
      R => '0'
    );
\ctl_reg_control_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \ctl_reg_control[0]_i_1_n_0\,
      Q => \ctl_reg_control_reg_n_0_[0]\,
      R => '0'
    );
\ctl_reg_downcounter[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010000000000000"
    )
        port map (
      I0 => ctl_addr_i(2),
      I1 => ctl_addr_i(3),
      I2 => \ctl_reg_downcounter[31]_i_2_n_0\,
      I3 => ctl_rst_i,
      I4 => ctl_ena_i,
      I5 => ctl_wea_i(1),
      O => \ctl_reg_downcounter[15]_i_1_n_0\
    );
\ctl_reg_downcounter[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010000000000000"
    )
        port map (
      I0 => ctl_addr_i(2),
      I1 => ctl_addr_i(3),
      I2 => \ctl_reg_downcounter[31]_i_2_n_0\,
      I3 => ctl_rst_i,
      I4 => ctl_ena_i,
      I5 => ctl_wea_i(2),
      O => \ctl_reg_downcounter[23]_i_1_n_0\
    );
\ctl_reg_downcounter[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010000000000000"
    )
        port map (
      I0 => ctl_addr_i(2),
      I1 => ctl_addr_i(3),
      I2 => \ctl_reg_downcounter[31]_i_2_n_0\,
      I3 => ctl_rst_i,
      I4 => ctl_ena_i,
      I5 => ctl_wea_i(3),
      O => \ctl_reg_downcounter[31]_i_1_n_0\
    );
\ctl_reg_downcounter[31]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \ctl_reg_downcounter[31]_i_3_n_0\,
      I1 => \ctl_reg_downcounter[31]_i_4_n_0\,
      I2 => \ctl_reg_downcounter[31]_i_5_n_0\,
      O => \ctl_reg_downcounter[31]_i_2_n_0\
    );
\ctl_reg_downcounter[31]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => ctl_addr_i(4),
      I1 => ctl_addr_i(5),
      I2 => ctl_addr_i(6),
      I3 => ctl_addr_i(7),
      I4 => \ctl_reg_downcounter[31]_i_6_n_0\,
      O => \ctl_reg_downcounter[31]_i_3_n_0\
    );
\ctl_reg_downcounter[31]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => ctl_addr_i(12),
      I1 => ctl_addr_i(13),
      I2 => ctl_addr_i(14),
      I3 => ctl_addr_i(15),
      I4 => \ctl_reg_downcounter[31]_i_7_n_0\,
      O => \ctl_reg_downcounter[31]_i_4_n_0\
    );
\ctl_reg_downcounter[31]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \ctl_reg_downcounter[31]_i_8_n_0\,
      I1 => \ctl_reg_downcounter[31]_i_9_n_0\,
      I2 => ctl_addr_i(23),
      I3 => ctl_addr_i(22),
      I4 => ctl_addr_i(21),
      I5 => ctl_addr_i(20),
      O => \ctl_reg_downcounter[31]_i_5_n_0\
    );
\ctl_reg_downcounter[31]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => ctl_addr_i(11),
      I1 => ctl_addr_i(10),
      I2 => ctl_addr_i(9),
      I3 => ctl_addr_i(8),
      O => \ctl_reg_downcounter[31]_i_6_n_0\
    );
\ctl_reg_downcounter[31]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => ctl_addr_i(19),
      I1 => ctl_addr_i(18),
      I2 => ctl_addr_i(17),
      I3 => ctl_addr_i(16),
      O => \ctl_reg_downcounter[31]_i_7_n_0\
    );
\ctl_reg_downcounter[31]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => ctl_addr_i(28),
      I1 => ctl_addr_i(29),
      I2 => ctl_addr_i(30),
      I3 => ctl_addr_i(31),
      I4 => ctl_addr_i(1),
      I5 => ctl_addr_i(0),
      O => \ctl_reg_downcounter[31]_i_8_n_0\
    );
\ctl_reg_downcounter[31]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => ctl_addr_i(27),
      I1 => ctl_addr_i(26),
      I2 => ctl_addr_i(25),
      I3 => ctl_addr_i(24),
      O => \ctl_reg_downcounter[31]_i_9_n_0\
    );
\ctl_reg_downcounter[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010000000000000"
    )
        port map (
      I0 => ctl_addr_i(2),
      I1 => ctl_addr_i(3),
      I2 => \ctl_reg_downcounter[31]_i_2_n_0\,
      I3 => ctl_rst_i,
      I4 => ctl_ena_i,
      I5 => ctl_wea_i(0),
      O => \ctl_reg_downcounter[7]_i_1_n_0\
    );
\ctl_reg_downcounter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[7]_i_1_n_0\,
      D => ctl_data_i(0),
      Q => ctl_reg_downcounter(0),
      R => '0'
    );
\ctl_reg_downcounter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[15]_i_1_n_0\,
      D => ctl_data_i(10),
      Q => ctl_reg_downcounter(10),
      R => '0'
    );
\ctl_reg_downcounter_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[15]_i_1_n_0\,
      D => ctl_data_i(11),
      Q => ctl_reg_downcounter(11),
      R => '0'
    );
\ctl_reg_downcounter_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[15]_i_1_n_0\,
      D => ctl_data_i(12),
      Q => ctl_reg_downcounter(12),
      R => '0'
    );
\ctl_reg_downcounter_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[15]_i_1_n_0\,
      D => ctl_data_i(13),
      Q => ctl_reg_downcounter(13),
      R => '0'
    );
\ctl_reg_downcounter_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[15]_i_1_n_0\,
      D => ctl_data_i(14),
      Q => ctl_reg_downcounter(14),
      R => '0'
    );
\ctl_reg_downcounter_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[15]_i_1_n_0\,
      D => ctl_data_i(15),
      Q => ctl_reg_downcounter(15),
      R => '0'
    );
\ctl_reg_downcounter_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[23]_i_1_n_0\,
      D => ctl_data_i(16),
      Q => ctl_reg_downcounter(16),
      R => '0'
    );
\ctl_reg_downcounter_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[23]_i_1_n_0\,
      D => ctl_data_i(17),
      Q => ctl_reg_downcounter(17),
      R => '0'
    );
\ctl_reg_downcounter_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[23]_i_1_n_0\,
      D => ctl_data_i(18),
      Q => ctl_reg_downcounter(18),
      R => '0'
    );
\ctl_reg_downcounter_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[23]_i_1_n_0\,
      D => ctl_data_i(19),
      Q => ctl_reg_downcounter(19),
      R => '0'
    );
\ctl_reg_downcounter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[7]_i_1_n_0\,
      D => ctl_data_i(1),
      Q => ctl_reg_downcounter(1),
      R => '0'
    );
\ctl_reg_downcounter_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[23]_i_1_n_0\,
      D => ctl_data_i(20),
      Q => ctl_reg_downcounter(20),
      R => '0'
    );
\ctl_reg_downcounter_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[23]_i_1_n_0\,
      D => ctl_data_i(21),
      Q => ctl_reg_downcounter(21),
      R => '0'
    );
\ctl_reg_downcounter_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[23]_i_1_n_0\,
      D => ctl_data_i(22),
      Q => ctl_reg_downcounter(22),
      R => '0'
    );
\ctl_reg_downcounter_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[23]_i_1_n_0\,
      D => ctl_data_i(23),
      Q => ctl_reg_downcounter(23),
      R => '0'
    );
\ctl_reg_downcounter_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[31]_i_1_n_0\,
      D => ctl_data_i(24),
      Q => ctl_reg_downcounter(24),
      R => '0'
    );
\ctl_reg_downcounter_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[31]_i_1_n_0\,
      D => ctl_data_i(25),
      Q => ctl_reg_downcounter(25),
      R => '0'
    );
\ctl_reg_downcounter_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[31]_i_1_n_0\,
      D => ctl_data_i(26),
      Q => ctl_reg_downcounter(26),
      R => '0'
    );
\ctl_reg_downcounter_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[31]_i_1_n_0\,
      D => ctl_data_i(27),
      Q => ctl_reg_downcounter(27),
      R => '0'
    );
\ctl_reg_downcounter_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[31]_i_1_n_0\,
      D => ctl_data_i(28),
      Q => ctl_reg_downcounter(28),
      R => '0'
    );
\ctl_reg_downcounter_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[31]_i_1_n_0\,
      D => ctl_data_i(29),
      Q => ctl_reg_downcounter(29),
      R => '0'
    );
\ctl_reg_downcounter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[7]_i_1_n_0\,
      D => ctl_data_i(2),
      Q => ctl_reg_downcounter(2),
      R => '0'
    );
\ctl_reg_downcounter_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[31]_i_1_n_0\,
      D => ctl_data_i(30),
      Q => ctl_reg_downcounter(30),
      R => '0'
    );
\ctl_reg_downcounter_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[31]_i_1_n_0\,
      D => ctl_data_i(31),
      Q => ctl_reg_downcounter(31),
      R => '0'
    );
\ctl_reg_downcounter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[7]_i_1_n_0\,
      D => ctl_data_i(3),
      Q => ctl_reg_downcounter(3),
      R => '0'
    );
\ctl_reg_downcounter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[7]_i_1_n_0\,
      D => ctl_data_i(4),
      Q => ctl_reg_downcounter(4),
      R => '0'
    );
\ctl_reg_downcounter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[7]_i_1_n_0\,
      D => ctl_data_i(5),
      Q => ctl_reg_downcounter(5),
      R => '0'
    );
\ctl_reg_downcounter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[7]_i_1_n_0\,
      D => ctl_data_i(6),
      Q => ctl_reg_downcounter(6),
      R => '0'
    );
\ctl_reg_downcounter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[7]_i_1_n_0\,
      D => ctl_data_i(7),
      Q => ctl_reg_downcounter(7),
      R => '0'
    );
\ctl_reg_downcounter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[15]_i_1_n_0\,
      D => ctl_data_i(8),
      Q => ctl_reg_downcounter(8),
      R => '0'
    );
\ctl_reg_downcounter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => \ctl_reg_downcounter[15]_i_1_n_0\,
      D => ctl_data_i(9),
      Q => ctl_reg_downcounter(9),
      R => '0'
    );
\ctl_reg_options[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BF80"
    )
        port map (
      I0 => ctl_data_i(0),
      I1 => \ctl_reg_options[1]_i_2_n_0\,
      I2 => \ctl_reg_downcounter[31]_i_2_n_0\,
      I3 => \ctl_reg_options_reg_n_0_[0]\,
      O => \ctl_reg_options[0]_i_1_n_0\
    );
\ctl_reg_options[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BF80"
    )
        port map (
      I0 => ctl_data_i(1),
      I1 => \ctl_reg_options[1]_i_2_n_0\,
      I2 => \ctl_reg_downcounter[31]_i_2_n_0\,
      I3 => p_0_in,
      O => \ctl_reg_options[1]_i_1_n_0\
    );
\ctl_reg_options[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => ctl_wea_i(0),
      I1 => ctl_addr_i(2),
      I2 => ctl_addr_i(3),
      I3 => ctl_rst_i,
      I4 => ctl_ena_i,
      O => \ctl_reg_options[1]_i_2_n_0\
    );
\ctl_reg_options_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \ctl_reg_options[0]_i_1_n_0\,
      Q => \ctl_reg_options_reg_n_0_[0]\,
      R => '0'
    );
\ctl_reg_options_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \ctl_reg_options[1]_i_1_n_0\,
      Q => p_0_in,
      R => '0'
    );
\datmem_addr_o[31]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \writer_state__0\(1),
      I1 => \writer_state__0\(0),
      I2 => ipc_write,
      I3 => clk_en,
      O => \datmem_addr_o[31]_i_1_n_0\
    );
\datmem_addr_o_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(10),
      Q => datmem_addr_o(9),
      R => '0'
    );
\datmem_addr_o_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(11),
      Q => datmem_addr_o(10),
      R => '0'
    );
\datmem_addr_o_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(12),
      Q => datmem_addr_o(11),
      R => '0'
    );
\datmem_addr_o_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(13),
      Q => datmem_addr_o(12),
      R => '0'
    );
\datmem_addr_o_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(14),
      Q => datmem_addr_o(13),
      R => '0'
    );
\datmem_addr_o_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(15),
      Q => datmem_addr_o(14),
      R => '0'
    );
\datmem_addr_o_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(16),
      Q => datmem_addr_o(15),
      R => '0'
    );
\datmem_addr_o_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(17),
      Q => datmem_addr_o(16),
      R => '0'
    );
\datmem_addr_o_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(18),
      Q => datmem_addr_o(17),
      R => '0'
    );
\datmem_addr_o_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(19),
      Q => datmem_addr_o(18),
      R => '0'
    );
\datmem_addr_o_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(1),
      Q => datmem_addr_o(0),
      R => '0'
    );
\datmem_addr_o_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(20),
      Q => datmem_addr_o(19),
      R => '0'
    );
\datmem_addr_o_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(21),
      Q => datmem_addr_o(20),
      R => '0'
    );
\datmem_addr_o_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(22),
      Q => datmem_addr_o(21),
      R => '0'
    );
\datmem_addr_o_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(23),
      Q => datmem_addr_o(22),
      R => '0'
    );
\datmem_addr_o_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(24),
      Q => datmem_addr_o(23),
      R => '0'
    );
\datmem_addr_o_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(25),
      Q => datmem_addr_o(24),
      R => '0'
    );
\datmem_addr_o_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(26),
      Q => datmem_addr_o(25),
      R => '0'
    );
\datmem_addr_o_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(27),
      Q => datmem_addr_o(26),
      R => '0'
    );
\datmem_addr_o_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(28),
      Q => datmem_addr_o(27),
      R => '0'
    );
\datmem_addr_o_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(29),
      Q => datmem_addr_o(28),
      R => '0'
    );
\datmem_addr_o_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(2),
      Q => datmem_addr_o(1),
      R => '0'
    );
\datmem_addr_o_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(30),
      Q => datmem_addr_o(29),
      R => '0'
    );
\datmem_addr_o_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(31),
      Q => datmem_addr_o(30),
      R => '0'
    );
\datmem_addr_o_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(3),
      Q => datmem_addr_o(2),
      R => '0'
    );
\datmem_addr_o_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(4),
      Q => datmem_addr_o(3),
      R => '0'
    );
\datmem_addr_o_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(5),
      Q => datmem_addr_o(4),
      R => '0'
    );
\datmem_addr_o_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(6),
      Q => datmem_addr_o(5),
      R => '0'
    );
\datmem_addr_o_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(7),
      Q => datmem_addr_o(6),
      R => '0'
    );
\datmem_addr_o_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(8),
      Q => datmem_addr_o(7),
      R => '0'
    );
\datmem_addr_o_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_addr_o[31]_i_1_n_0\,
      D => \writer_address__0\(9),
      Q => datmem_addr_o(8),
      R => '0'
    );
\datmem_data_o[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \writer_state__0\(1),
      I1 => clk_en,
      I2 => \writer_state__0\(0),
      O => \datmem_data_o[31]_i_1_n_0\
    );
\datmem_data_o[31]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E0"
    )
        port map (
      I0 => \writer_state__0\(0),
      I1 => ipc_write,
      I2 => clk_en,
      I3 => \writer_state__0\(1),
      O => \datmem_data_o[31]_i_2_n_0\
    );
\datmem_data_o_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(0),
      Q => datmem_data_o(0),
      R => '0'
    );
\datmem_data_o_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(10),
      Q => datmem_data_o(10),
      R => '0'
    );
\datmem_data_o_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(11),
      Q => datmem_data_o(11),
      R => '0'
    );
\datmem_data_o_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(12),
      Q => datmem_data_o(12),
      R => '0'
    );
\datmem_data_o_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => \ipc_data_reg_n_0_[13]\,
      Q => datmem_data_o(13),
      R => \datmem_data_o[31]_i_1_n_0\
    );
\datmem_data_o_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => \ipc_data_reg_n_0_[14]\,
      Q => datmem_data_o(14),
      R => \datmem_data_o[31]_i_1_n_0\
    );
\datmem_data_o_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => \ipc_data_reg_n_0_[15]\,
      Q => datmem_data_o(15),
      R => \datmem_data_o[31]_i_1_n_0\
    );
\datmem_data_o_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(16),
      Q => datmem_data_o(16),
      R => '0'
    );
\datmem_data_o_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(17),
      Q => datmem_data_o(17),
      R => '0'
    );
\datmem_data_o_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(18),
      Q => datmem_data_o(18),
      R => '0'
    );
\datmem_data_o_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(19),
      Q => datmem_data_o(19),
      R => '0'
    );
\datmem_data_o_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(1),
      Q => datmem_data_o(1),
      R => '0'
    );
\datmem_data_o_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(20),
      Q => datmem_data_o(20),
      R => '0'
    );
\datmem_data_o_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(21),
      Q => datmem_data_o(21),
      R => '0'
    );
\datmem_data_o_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(22),
      Q => datmem_data_o(22),
      R => '0'
    );
\datmem_data_o_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(23),
      Q => datmem_data_o(23),
      R => '0'
    );
\datmem_data_o_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(24),
      Q => datmem_data_o(24),
      R => '0'
    );
\datmem_data_o_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(25),
      Q => datmem_data_o(25),
      R => '0'
    );
\datmem_data_o_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(26),
      Q => datmem_data_o(26),
      R => '0'
    );
\datmem_data_o_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(27),
      Q => datmem_data_o(27),
      R => '0'
    );
\datmem_data_o_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(28),
      Q => datmem_data_o(28),
      R => '0'
    );
\datmem_data_o_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => \ipc_data_reg_n_0_[29]\,
      Q => datmem_data_o(29),
      R => \datmem_data_o[31]_i_1_n_0\
    );
\datmem_data_o_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(2),
      Q => datmem_data_o(2),
      R => '0'
    );
\datmem_data_o_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => \ipc_data_reg_n_0_[30]\,
      Q => datmem_data_o(30),
      R => \datmem_data_o[31]_i_1_n_0\
    );
\datmem_data_o_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => \ipc_data_reg_n_0_[31]\,
      Q => datmem_data_o(31),
      R => \datmem_data_o[31]_i_1_n_0\
    );
\datmem_data_o_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(3),
      Q => datmem_data_o(3),
      R => '0'
    );
\datmem_data_o_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(4),
      Q => datmem_data_o(4),
      R => '0'
    );
\datmem_data_o_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(5),
      Q => datmem_data_o(5),
      R => '0'
    );
\datmem_data_o_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(6),
      Q => datmem_data_o(6),
      R => '0'
    );
\datmem_data_o_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(7),
      Q => datmem_data_o(7),
      R => '0'
    );
\datmem_data_o_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(8),
      Q => datmem_data_o(8),
      R => '0'
    );
\datmem_data_o_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \datmem_data_o[31]_i_2_n_0\,
      D => datmem_data_o0_in(9),
      Q => datmem_data_o(9),
      R => '0'
    );
datmem_ena_o_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \writer_state__0\(1),
      I1 => \writer_state__0\(0),
      O => datmem_ena_o_i_1_n_0
    );
datmem_ena_o_reg: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => datmem_ena_o_i_1_n_0,
      Q => datmem_wea_o(0),
      R => '0'
    );
decode_enable_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000080"
    )
        port map (
      I0 => p_0_in,
      I1 => clk_en,
      I2 => ipc_write,
      I3 => \writer_state__0\(0),
      I4 => \writer_state__0\(1),
      O => decode_enable_i_1_n_0
    );
decode_enable_reg: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => decode_enable_i_1_n_0,
      Q => ena,
      R => '0'
    );
\fsm_State[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"000E"
    )
        port map (
      I0 => \sync_reg_control_reg_n_0_[0]\,
      I1 => \fsm_State_reg_n_0_[1]\,
      I2 => \fsm_State_reg_n_0_[0]\,
      I3 => \fsm_State_reg_n_0_[2]\,
      O => fsm_State(0)
    );
\fsm_State[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"007C"
    )
        port map (
      I0 => \ipc_data1_carry__1_n_1\,
      I1 => \fsm_State_reg_n_0_[0]\,
      I2 => \fsm_State_reg_n_0_[1]\,
      I3 => \fsm_State_reg_n_0_[2]\,
      O => fsm_State(1)
    );
\fsm_State[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \fsm_State_reg_n_0_[2]\,
      I1 => \ipc_data1_carry__1_n_1\,
      I2 => \fsm_State_reg_n_0_[0]\,
      I3 => \fsm_State_reg_n_0_[1]\,
      O => fsm_State(2)
    );
\fsm_State_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => fsm_State(0),
      Q => \fsm_State_reg_n_0_[0]\,
      R => '0'
    );
\fsm_State_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => fsm_State(1),
      Q => \fsm_State_reg_n_0_[1]\,
      R => '0'
    );
\fsm_State_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => fsm_State(2),
      Q => \fsm_State_reg_n_0_[2]\,
      R => '0'
    );
\fsm_bits_sent[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fsm_bits_sent(0),
      O => \fsm_bits_sent[0]_i_1_n_0\
    );
\fsm_bits_sent[31]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \fsm_State_reg_n_0_[0]\,
      I1 => clk_en,
      I2 => \fsm_State_reg_n_0_[2]\,
      I3 => \fsm_State_reg_n_0_[1]\,
      O => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent[31]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4004"
    )
        port map (
      I0 => \fsm_State_reg_n_0_[2]\,
      I1 => clk_en,
      I2 => \fsm_State_reg_n_0_[1]\,
      I3 => \fsm_State_reg_n_0_[0]\,
      O => misobitptr
    );
\fsm_bits_sent_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_bits_sent[0]_i_1_n_0\,
      Q => fsm_bits_sent(0),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(10),
      Q => fsm_bits_sent(10),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(11),
      Q => fsm_bits_sent(11),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(12),
      Q => fsm_bits_sent(12),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \fsm_bits_sent_reg[8]_i_1_n_0\,
      CO(3) => \fsm_bits_sent_reg[12]_i_1_n_0\,
      CO(2) => \fsm_bits_sent_reg[12]_i_1_n_1\,
      CO(1) => \fsm_bits_sent_reg[12]_i_1_n_2\,
      CO(0) => \fsm_bits_sent_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => plusOp(12 downto 9),
      S(3 downto 0) => fsm_bits_sent(12 downto 9)
    );
\fsm_bits_sent_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(13),
      Q => fsm_bits_sent(13),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(14),
      Q => fsm_bits_sent(14),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(15),
      Q => fsm_bits_sent(15),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(16),
      Q => fsm_bits_sent(16),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \fsm_bits_sent_reg[12]_i_1_n_0\,
      CO(3) => \fsm_bits_sent_reg[16]_i_1_n_0\,
      CO(2) => \fsm_bits_sent_reg[16]_i_1_n_1\,
      CO(1) => \fsm_bits_sent_reg[16]_i_1_n_2\,
      CO(0) => \fsm_bits_sent_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => plusOp(16 downto 13),
      S(3 downto 0) => fsm_bits_sent(16 downto 13)
    );
\fsm_bits_sent_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(17),
      Q => fsm_bits_sent(17),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(18),
      Q => fsm_bits_sent(18),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(19),
      Q => fsm_bits_sent(19),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(1),
      Q => fsm_bits_sent(1),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(20),
      Q => fsm_bits_sent(20),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[20]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \fsm_bits_sent_reg[16]_i_1_n_0\,
      CO(3) => \fsm_bits_sent_reg[20]_i_1_n_0\,
      CO(2) => \fsm_bits_sent_reg[20]_i_1_n_1\,
      CO(1) => \fsm_bits_sent_reg[20]_i_1_n_2\,
      CO(0) => \fsm_bits_sent_reg[20]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => plusOp(20 downto 17),
      S(3 downto 0) => fsm_bits_sent(20 downto 17)
    );
\fsm_bits_sent_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(21),
      Q => fsm_bits_sent(21),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(22),
      Q => fsm_bits_sent(22),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(23),
      Q => fsm_bits_sent(23),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(24),
      Q => fsm_bits_sent(24),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[24]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \fsm_bits_sent_reg[20]_i_1_n_0\,
      CO(3) => \fsm_bits_sent_reg[24]_i_1_n_0\,
      CO(2) => \fsm_bits_sent_reg[24]_i_1_n_1\,
      CO(1) => \fsm_bits_sent_reg[24]_i_1_n_2\,
      CO(0) => \fsm_bits_sent_reg[24]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => plusOp(24 downto 21),
      S(3 downto 0) => fsm_bits_sent(24 downto 21)
    );
\fsm_bits_sent_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(25),
      Q => fsm_bits_sent(25),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(26),
      Q => fsm_bits_sent(26),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(27),
      Q => fsm_bits_sent(27),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(28),
      Q => fsm_bits_sent(28),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[28]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \fsm_bits_sent_reg[24]_i_1_n_0\,
      CO(3) => \fsm_bits_sent_reg[28]_i_1_n_0\,
      CO(2) => \fsm_bits_sent_reg[28]_i_1_n_1\,
      CO(1) => \fsm_bits_sent_reg[28]_i_1_n_2\,
      CO(0) => \fsm_bits_sent_reg[28]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => plusOp(28 downto 25),
      S(3 downto 0) => fsm_bits_sent(28 downto 25)
    );
\fsm_bits_sent_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(29),
      Q => fsm_bits_sent(29),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(2),
      Q => fsm_bits_sent(2),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(30),
      Q => fsm_bits_sent(30),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(31),
      Q => fsm_bits_sent(31),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[31]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => \fsm_bits_sent_reg[28]_i_1_n_0\,
      CO(3 downto 2) => \NLW_fsm_bits_sent_reg[31]_i_3_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \fsm_bits_sent_reg[31]_i_3_n_2\,
      CO(0) => \fsm_bits_sent_reg[31]_i_3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_fsm_bits_sent_reg[31]_i_3_O_UNCONNECTED\(3),
      O(2 downto 0) => plusOp(31 downto 29),
      S(3) => '0',
      S(2 downto 0) => fsm_bits_sent(31 downto 29)
    );
\fsm_bits_sent_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(3),
      Q => fsm_bits_sent(3),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(4),
      Q => fsm_bits_sent(4),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \fsm_bits_sent_reg[4]_i_1_n_0\,
      CO(2) => \fsm_bits_sent_reg[4]_i_1_n_1\,
      CO(1) => \fsm_bits_sent_reg[4]_i_1_n_2\,
      CO(0) => \fsm_bits_sent_reg[4]_i_1_n_3\,
      CYINIT => fsm_bits_sent(0),
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => plusOp(4 downto 1),
      S(3 downto 0) => fsm_bits_sent(4 downto 1)
    );
\fsm_bits_sent_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(5),
      Q => fsm_bits_sent(5),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(6),
      Q => fsm_bits_sent(6),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(7),
      Q => fsm_bits_sent(7),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(8),
      Q => fsm_bits_sent(8),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_bits_sent_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \fsm_bits_sent_reg[4]_i_1_n_0\,
      CO(3) => \fsm_bits_sent_reg[8]_i_1_n_0\,
      CO(2) => \fsm_bits_sent_reg[8]_i_1_n_1\,
      CO(1) => \fsm_bits_sent_reg[8]_i_1_n_2\,
      CO(0) => \fsm_bits_sent_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => plusOp(8 downto 5),
      S(3 downto 0) => fsm_bits_sent(8 downto 5)
    );
\fsm_bits_sent_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => plusOp(9),
      Q => fsm_bits_sent(9),
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_skip_counter[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \fsm_skip_counter_reg_n_0_[0]\,
      O => \fsm_skip_counter[0]_i_1_n_0\
    );
\fsm_skip_counter[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000200F0000"
    )
        port map (
      I0 => \fsm_skip_counter[31]_i_3_n_0\,
      I1 => \fsm_skip_counter[31]_i_4_n_0\,
      I2 => \fsm_State_reg_n_0_[0]\,
      I3 => \fsm_State_reg_n_0_[1]\,
      I4 => clk_en,
      I5 => \fsm_State_reg_n_0_[2]\,
      O => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter[31]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \fsm_skip_counter[31]_i_5_n_0\,
      I1 => \fsm_skip_counter[31]_i_6_n_0\,
      I2 => \fsm_skip_counter_reg_n_0_[15]\,
      I3 => \fsm_skip_counter_reg_n_0_[17]\,
      I4 => \fsm_skip_counter_reg_n_0_[14]\,
      O => \fsm_skip_counter[31]_i_3_n_0\
    );
\fsm_skip_counter[31]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBFFFFFFF"
    )
        port map (
      I0 => \fsm_skip_counter[31]_i_7_n_0\,
      I1 => \fsm_skip_counter_reg_n_0_[2]\,
      I2 => \fsm_skip_counter_reg_n_0_[1]\,
      I3 => \fsm_skip_counter_reg_n_0_[9]\,
      I4 => \fsm_skip_counter_reg_n_0_[0]\,
      I5 => \misobitptr[4]_i_4_n_0\,
      O => \fsm_skip_counter[31]_i_4_n_0\
    );
\fsm_skip_counter[31]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \fsm_skip_counter_reg_n_0_[27]\,
      I1 => \fsm_skip_counter_reg_n_0_[20]\,
      I2 => \fsm_skip_counter_reg_n_0_[19]\,
      I3 => \fsm_skip_counter_reg_n_0_[23]\,
      I4 => \fsm_skip_counter[31]_i_8_n_0\,
      O => \fsm_skip_counter[31]_i_5_n_0\
    );
\fsm_skip_counter[31]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \fsm_skip_counter_reg_n_0_[13]\,
      I1 => \fsm_skip_counter_reg_n_0_[21]\,
      I2 => \fsm_skip_counter_reg_n_0_[7]\,
      I3 => \fsm_skip_counter_reg_n_0_[22]\,
      I4 => \fsm_skip_counter[31]_i_9_n_0\,
      O => \fsm_skip_counter[31]_i_6_n_0\
    );
\fsm_skip_counter[31]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \fsm_skip_counter_reg_n_0_[4]\,
      I1 => \fsm_skip_counter_reg_n_0_[3]\,
      I2 => \fsm_skip_counter_reg_n_0_[8]\,
      I3 => \ctl_reg_options_reg_n_0_[0]\,
      I4 => \fsm_skip_counter_reg_n_0_[5]\,
      I5 => \fsm_skip_counter_reg_n_0_[6]\,
      O => \fsm_skip_counter[31]_i_7_n_0\
    );
\fsm_skip_counter[31]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \fsm_skip_counter_reg_n_0_[18]\,
      I1 => \fsm_skip_counter_reg_n_0_[29]\,
      I2 => \fsm_skip_counter_reg_n_0_[12]\,
      I3 => \fsm_skip_counter_reg_n_0_[10]\,
      O => \fsm_skip_counter[31]_i_8_n_0\
    );
\fsm_skip_counter[31]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \fsm_skip_counter_reg_n_0_[11]\,
      I1 => \fsm_skip_counter_reg_n_0_[31]\,
      I2 => \fsm_skip_counter_reg_n_0_[16]\,
      I3 => \fsm_skip_counter_reg_n_0_[26]\,
      O => \fsm_skip_counter[31]_i_9_n_0\
    );
\fsm_skip_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter[0]_i_1_n_0\,
      Q => \fsm_skip_counter_reg_n_0_[0]\,
      R => \fsm_bits_sent[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[12]_i_1_n_6\,
      Q => \fsm_skip_counter_reg_n_0_[10]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[12]_i_1_n_5\,
      Q => \fsm_skip_counter_reg_n_0_[11]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[12]_i_1_n_4\,
      Q => \fsm_skip_counter_reg_n_0_[12]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \fsm_skip_counter_reg[8]_i_1_n_0\,
      CO(3) => \fsm_skip_counter_reg[12]_i_1_n_0\,
      CO(2) => \fsm_skip_counter_reg[12]_i_1_n_1\,
      CO(1) => \fsm_skip_counter_reg[12]_i_1_n_2\,
      CO(0) => \fsm_skip_counter_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \fsm_skip_counter_reg[12]_i_1_n_4\,
      O(2) => \fsm_skip_counter_reg[12]_i_1_n_5\,
      O(1) => \fsm_skip_counter_reg[12]_i_1_n_6\,
      O(0) => \fsm_skip_counter_reg[12]_i_1_n_7\,
      S(3) => \fsm_skip_counter_reg_n_0_[12]\,
      S(2) => \fsm_skip_counter_reg_n_0_[11]\,
      S(1) => \fsm_skip_counter_reg_n_0_[10]\,
      S(0) => \fsm_skip_counter_reg_n_0_[9]\
    );
\fsm_skip_counter_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[16]_i_1_n_7\,
      Q => \fsm_skip_counter_reg_n_0_[13]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[16]_i_1_n_6\,
      Q => \fsm_skip_counter_reg_n_0_[14]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[16]_i_1_n_5\,
      Q => \fsm_skip_counter_reg_n_0_[15]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[16]_i_1_n_4\,
      Q => \fsm_skip_counter_reg_n_0_[16]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \fsm_skip_counter_reg[12]_i_1_n_0\,
      CO(3) => \fsm_skip_counter_reg[16]_i_1_n_0\,
      CO(2) => \fsm_skip_counter_reg[16]_i_1_n_1\,
      CO(1) => \fsm_skip_counter_reg[16]_i_1_n_2\,
      CO(0) => \fsm_skip_counter_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \fsm_skip_counter_reg[16]_i_1_n_4\,
      O(2) => \fsm_skip_counter_reg[16]_i_1_n_5\,
      O(1) => \fsm_skip_counter_reg[16]_i_1_n_6\,
      O(0) => \fsm_skip_counter_reg[16]_i_1_n_7\,
      S(3) => \fsm_skip_counter_reg_n_0_[16]\,
      S(2) => \fsm_skip_counter_reg_n_0_[15]\,
      S(1) => \fsm_skip_counter_reg_n_0_[14]\,
      S(0) => \fsm_skip_counter_reg_n_0_[13]\
    );
\fsm_skip_counter_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[20]_i_1_n_7\,
      Q => \fsm_skip_counter_reg_n_0_[17]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[20]_i_1_n_6\,
      Q => \fsm_skip_counter_reg_n_0_[18]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[20]_i_1_n_5\,
      Q => \fsm_skip_counter_reg_n_0_[19]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[4]_i_1_n_7\,
      Q => \fsm_skip_counter_reg_n_0_[1]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[20]_i_1_n_4\,
      Q => \fsm_skip_counter_reg_n_0_[20]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[20]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \fsm_skip_counter_reg[16]_i_1_n_0\,
      CO(3) => \fsm_skip_counter_reg[20]_i_1_n_0\,
      CO(2) => \fsm_skip_counter_reg[20]_i_1_n_1\,
      CO(1) => \fsm_skip_counter_reg[20]_i_1_n_2\,
      CO(0) => \fsm_skip_counter_reg[20]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \fsm_skip_counter_reg[20]_i_1_n_4\,
      O(2) => \fsm_skip_counter_reg[20]_i_1_n_5\,
      O(1) => \fsm_skip_counter_reg[20]_i_1_n_6\,
      O(0) => \fsm_skip_counter_reg[20]_i_1_n_7\,
      S(3) => \fsm_skip_counter_reg_n_0_[20]\,
      S(2) => \fsm_skip_counter_reg_n_0_[19]\,
      S(1) => \fsm_skip_counter_reg_n_0_[18]\,
      S(0) => \fsm_skip_counter_reg_n_0_[17]\
    );
\fsm_skip_counter_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[24]_i_1_n_7\,
      Q => \fsm_skip_counter_reg_n_0_[21]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[24]_i_1_n_6\,
      Q => \fsm_skip_counter_reg_n_0_[22]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[24]_i_1_n_5\,
      Q => \fsm_skip_counter_reg_n_0_[23]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[24]_i_1_n_4\,
      Q => \fsm_skip_counter_reg_n_0_[24]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[24]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \fsm_skip_counter_reg[20]_i_1_n_0\,
      CO(3) => \fsm_skip_counter_reg[24]_i_1_n_0\,
      CO(2) => \fsm_skip_counter_reg[24]_i_1_n_1\,
      CO(1) => \fsm_skip_counter_reg[24]_i_1_n_2\,
      CO(0) => \fsm_skip_counter_reg[24]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \fsm_skip_counter_reg[24]_i_1_n_4\,
      O(2) => \fsm_skip_counter_reg[24]_i_1_n_5\,
      O(1) => \fsm_skip_counter_reg[24]_i_1_n_6\,
      O(0) => \fsm_skip_counter_reg[24]_i_1_n_7\,
      S(3) => \fsm_skip_counter_reg_n_0_[24]\,
      S(2) => \fsm_skip_counter_reg_n_0_[23]\,
      S(1) => \fsm_skip_counter_reg_n_0_[22]\,
      S(0) => \fsm_skip_counter_reg_n_0_[21]\
    );
\fsm_skip_counter_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[28]_i_1_n_7\,
      Q => \fsm_skip_counter_reg_n_0_[25]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[28]_i_1_n_6\,
      Q => \fsm_skip_counter_reg_n_0_[26]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[28]_i_1_n_5\,
      Q => \fsm_skip_counter_reg_n_0_[27]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[28]_i_1_n_4\,
      Q => \fsm_skip_counter_reg_n_0_[28]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[28]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \fsm_skip_counter_reg[24]_i_1_n_0\,
      CO(3) => \fsm_skip_counter_reg[28]_i_1_n_0\,
      CO(2) => \fsm_skip_counter_reg[28]_i_1_n_1\,
      CO(1) => \fsm_skip_counter_reg[28]_i_1_n_2\,
      CO(0) => \fsm_skip_counter_reg[28]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \fsm_skip_counter_reg[28]_i_1_n_4\,
      O(2) => \fsm_skip_counter_reg[28]_i_1_n_5\,
      O(1) => \fsm_skip_counter_reg[28]_i_1_n_6\,
      O(0) => \fsm_skip_counter_reg[28]_i_1_n_7\,
      S(3) => \fsm_skip_counter_reg_n_0_[28]\,
      S(2) => \fsm_skip_counter_reg_n_0_[27]\,
      S(1) => \fsm_skip_counter_reg_n_0_[26]\,
      S(0) => \fsm_skip_counter_reg_n_0_[25]\
    );
\fsm_skip_counter_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[31]_i_2_n_7\,
      Q => \fsm_skip_counter_reg_n_0_[29]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[4]_i_1_n_6\,
      Q => \fsm_skip_counter_reg_n_0_[2]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[31]_i_2_n_6\,
      Q => \fsm_skip_counter_reg_n_0_[30]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[31]_i_2_n_5\,
      Q => \fsm_skip_counter_reg_n_0_[31]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[31]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \fsm_skip_counter_reg[28]_i_1_n_0\,
      CO(3 downto 2) => \NLW_fsm_skip_counter_reg[31]_i_2_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \fsm_skip_counter_reg[31]_i_2_n_2\,
      CO(0) => \fsm_skip_counter_reg[31]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_fsm_skip_counter_reg[31]_i_2_O_UNCONNECTED\(3),
      O(2) => \fsm_skip_counter_reg[31]_i_2_n_5\,
      O(1) => \fsm_skip_counter_reg[31]_i_2_n_6\,
      O(0) => \fsm_skip_counter_reg[31]_i_2_n_7\,
      S(3) => '0',
      S(2) => \fsm_skip_counter_reg_n_0_[31]\,
      S(1) => \fsm_skip_counter_reg_n_0_[30]\,
      S(0) => \fsm_skip_counter_reg_n_0_[29]\
    );
\fsm_skip_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[4]_i_1_n_5\,
      Q => \fsm_skip_counter_reg_n_0_[3]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[4]_i_1_n_4\,
      Q => \fsm_skip_counter_reg_n_0_[4]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \fsm_skip_counter_reg[4]_i_1_n_0\,
      CO(2) => \fsm_skip_counter_reg[4]_i_1_n_1\,
      CO(1) => \fsm_skip_counter_reg[4]_i_1_n_2\,
      CO(0) => \fsm_skip_counter_reg[4]_i_1_n_3\,
      CYINIT => \fsm_skip_counter_reg_n_0_[0]\,
      DI(3 downto 0) => B"0000",
      O(3) => \fsm_skip_counter_reg[4]_i_1_n_4\,
      O(2) => \fsm_skip_counter_reg[4]_i_1_n_5\,
      O(1) => \fsm_skip_counter_reg[4]_i_1_n_6\,
      O(0) => \fsm_skip_counter_reg[4]_i_1_n_7\,
      S(3) => \fsm_skip_counter_reg_n_0_[4]\,
      S(2) => \fsm_skip_counter_reg_n_0_[3]\,
      S(1) => \fsm_skip_counter_reg_n_0_[2]\,
      S(0) => \fsm_skip_counter_reg_n_0_[1]\
    );
\fsm_skip_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[8]_i_1_n_7\,
      Q => \fsm_skip_counter_reg_n_0_[5]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[8]_i_1_n_6\,
      Q => \fsm_skip_counter_reg_n_0_[6]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[8]_i_1_n_5\,
      Q => \fsm_skip_counter_reg_n_0_[7]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[8]_i_1_n_4\,
      Q => \fsm_skip_counter_reg_n_0_[8]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
\fsm_skip_counter_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \fsm_skip_counter_reg[4]_i_1_n_0\,
      CO(3) => \fsm_skip_counter_reg[8]_i_1_n_0\,
      CO(2) => \fsm_skip_counter_reg[8]_i_1_n_1\,
      CO(1) => \fsm_skip_counter_reg[8]_i_1_n_2\,
      CO(0) => \fsm_skip_counter_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \fsm_skip_counter_reg[8]_i_1_n_4\,
      O(2) => \fsm_skip_counter_reg[8]_i_1_n_5\,
      O(1) => \fsm_skip_counter_reg[8]_i_1_n_6\,
      O(0) => \fsm_skip_counter_reg[8]_i_1_n_7\,
      S(3) => \fsm_skip_counter_reg_n_0_[8]\,
      S(2) => \fsm_skip_counter_reg_n_0_[7]\,
      S(1) => \fsm_skip_counter_reg_n_0_[6]\,
      S(0) => \fsm_skip_counter_reg_n_0_[5]\
    );
\fsm_skip_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \fsm_skip_counter_reg[12]_i_1_n_7\,
      Q => \fsm_skip_counter_reg_n_0_[9]\,
      R => \fsm_skip_counter[31]_i_1_n_0\
    );
fsm_start_ack_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFBFFFF00000400"
    )
        port map (
      I0 => \fsm_State_reg_n_0_[2]\,
      I1 => clk_en,
      I2 => \fsm_State_reg_n_0_[1]\,
      I3 => \sync_reg_control_reg_n_0_[0]\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \fsm_start_ack__0\,
      O => fsm_start_ack_i_1_n_0
    );
fsm_start_ack_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => fsm_start_ack_i_1_n_0,
      Q => \fsm_start_ack__0\,
      R => '0'
    );
\i__carry_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \mosiaddress_reg_n_0_[2]\,
      O => \i__carry_i_1_n_0\
    );
\i__carry_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \writer_address__0\(2),
      O => \i__carry_i_1__0_n_0\
    );
ipc_data1_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => ipc_data1_carry_n_0,
      CO(2) => ipc_data1_carry_n_1,
      CO(1) => ipc_data1_carry_n_2,
      CO(0) => ipc_data1_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_ipc_data1_carry_O_UNCONNECTED(3 downto 0),
      S(3) => ipc_data1_carry_i_1_n_0,
      S(2) => ipc_data1_carry_i_2_n_0,
      S(1) => ipc_data1_carry_i_3_n_0,
      S(0) => ipc_data1_carry_i_4_n_0
    );
\ipc_data1_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => ipc_data1_carry_n_0,
      CO(3) => \ipc_data1_carry__0_n_0\,
      CO(2) => \ipc_data1_carry__0_n_1\,
      CO(1) => \ipc_data1_carry__0_n_2\,
      CO(0) => \ipc_data1_carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_ipc_data1_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3) => \ipc_data1_carry__0_i_1_n_0\,
      S(2) => \ipc_data1_carry__0_i_2_n_0\,
      S(1) => \ipc_data1_carry__0_i_3_n_0\,
      S(0) => \ipc_data1_carry__0_i_4_n_0\
    );
\ipc_data1_carry__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => minusOp(21),
      I1 => fsm_bits_sent(21),
      I2 => minusOp(22),
      I3 => fsm_bits_sent(22),
      I4 => fsm_bits_sent(23),
      I5 => minusOp(23),
      O => \ipc_data1_carry__0_i_1_n_0\
    );
\ipc_data1_carry__0_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => minusOp(18),
      I1 => fsm_bits_sent(18),
      I2 => minusOp(19),
      I3 => fsm_bits_sent(19),
      I4 => fsm_bits_sent(20),
      I5 => minusOp(20),
      O => \ipc_data1_carry__0_i_2_n_0\
    );
\ipc_data1_carry__0_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => minusOp(15),
      I1 => fsm_bits_sent(15),
      I2 => minusOp(16),
      I3 => fsm_bits_sent(16),
      I4 => fsm_bits_sent(17),
      I5 => minusOp(17),
      O => \ipc_data1_carry__0_i_3_n_0\
    );
\ipc_data1_carry__0_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => minusOp(12),
      I1 => fsm_bits_sent(12),
      I2 => minusOp(13),
      I3 => fsm_bits_sent(13),
      I4 => fsm_bits_sent(14),
      I5 => minusOp(14),
      O => \ipc_data1_carry__0_i_4_n_0\
    );
\ipc_data1_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \ipc_data1_carry__0_n_0\,
      CO(3) => \NLW_ipc_data1_carry__1_CO_UNCONNECTED\(3),
      CO(2) => \ipc_data1_carry__1_n_1\,
      CO(1) => \ipc_data1_carry__1_n_2\,
      CO(0) => \ipc_data1_carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_ipc_data1_carry__1_O_UNCONNECTED\(3 downto 0),
      S(3) => '0',
      S(2) => \ipc_data1_carry__1_i_1_n_0\,
      S(1) => \ipc_data1_carry__1_i_2_n_0\,
      S(0) => \ipc_data1_carry__1_i_3_n_0\
    );
\ipc_data1_carry__1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => fsm_bits_sent(31),
      I1 => minusOp(31),
      I2 => fsm_bits_sent(30),
      I3 => minusOp(30),
      O => \ipc_data1_carry__1_i_1_n_0\
    );
\ipc_data1_carry__1_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => minusOp(28),
      I1 => fsm_bits_sent(28),
      I2 => minusOp(27),
      I3 => fsm_bits_sent(27),
      I4 => fsm_bits_sent(29),
      I5 => minusOp(29),
      O => \ipc_data1_carry__1_i_2_n_0\
    );
\ipc_data1_carry__1_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => minusOp(24),
      I1 => fsm_bits_sent(24),
      I2 => minusOp(25),
      I3 => fsm_bits_sent(25),
      I4 => fsm_bits_sent(26),
      I5 => minusOp(26),
      O => \ipc_data1_carry__1_i_3_n_0\
    );
ipc_data1_carry_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => minusOp(9),
      I1 => fsm_bits_sent(9),
      I2 => minusOp(10),
      I3 => fsm_bits_sent(10),
      I4 => fsm_bits_sent(11),
      I5 => minusOp(11),
      O => ipc_data1_carry_i_1_n_0
    );
ipc_data1_carry_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => minusOp(6),
      I1 => fsm_bits_sent(6),
      I2 => minusOp(7),
      I3 => fsm_bits_sent(7),
      I4 => fsm_bits_sent(8),
      I5 => minusOp(8),
      O => ipc_data1_carry_i_2_n_0
    );
ipc_data1_carry_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => minusOp(3),
      I1 => fsm_bits_sent(3),
      I2 => minusOp(4),
      I3 => fsm_bits_sent(4),
      I4 => fsm_bits_sent(5),
      I5 => minusOp(5),
      O => ipc_data1_carry_i_3_n_0
    );
ipc_data1_carry_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6006000000006006"
    )
        port map (
      I0 => fsm_bits_sent(0),
      I1 => ctl_reg_bits_to_write(0),
      I2 => minusOp(2),
      I3 => fsm_bits_sent(2),
      I4 => minusOp(1),
      I5 => fsm_bits_sent(1),
      O => ipc_data1_carry_i_4_n_0
    );
\ipc_data[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFBFBFFF00000000"
    )
        port map (
      I0 => \fsm_State_reg_n_0_[2]\,
      I1 => \fsm_State_reg_n_0_[1]\,
      I2 => \fsm_State_reg_n_0_[0]\,
      I3 => \ipc_data1_carry__1_n_1\,
      I4 => \misodata[31]_i_2_n_0\,
      I5 => clk_en,
      O => \ipc_data[30]_i_1_n_0\
    );
\ipc_data[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20000000"
    )
        port map (
      I0 => \ipc_data[31]_i_2_n_0\,
      I1 => \fsm_State_reg_n_0_[2]\,
      I2 => data0,
      I3 => \fsm_State_reg_n_0_[0]\,
      I4 => \fsm_State_reg_n_0_[1]\,
      O => \ipc_data[31]_i_1_n_0\
    );
\ipc_data[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAB"
    )
        port map (
      I0 => \ipc_data1_carry__1_n_1\,
      I1 => \misobitptr_reg_n_0_[3]\,
      I2 => \misobitptr_reg_n_0_[4]\,
      I3 => \misobitptr_reg_n_0_[2]\,
      I4 => \misobitptr_reg_n_0_[0]\,
      I5 => \misobitptr_reg_n_0_[1]\,
      O => \ipc_data[31]_i_2_n_0\
    );
\ipc_data_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[0]\,
      Q => \ipc_data_reg_n_0_[0]\,
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[10]\,
      Q => \ipc_data_reg_n_0_[10]\,
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[11]\,
      Q => \ipc_data_reg_n_0_[11]\,
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[12]\,
      Q => \ipc_data_reg_n_0_[12]\,
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[13]\,
      Q => \ipc_data_reg_n_0_[13]\,
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[14]\,
      Q => \ipc_data_reg_n_0_[14]\,
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[15]\,
      Q => \ipc_data_reg_n_0_[15]\,
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[16]\,
      Q => LFSR_in(0),
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[17]\,
      Q => LFSR_in(1),
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[18]\,
      Q => LFSR_in(2),
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[19]\,
      Q => LFSR_in(3),
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[1]\,
      Q => \ipc_data_reg_n_0_[1]\,
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[20]\,
      Q => LFSR_in(4),
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[21]\,
      Q => LFSR_in(5),
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[22]\,
      Q => LFSR_in(6),
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[23]\,
      Q => LFSR_in(7),
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[24]\,
      Q => LFSR_in(8),
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[25]\,
      Q => LFSR_in(9),
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[26]\,
      Q => LFSR_in(10),
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[27]\,
      Q => LFSR_in(11),
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[28]\,
      Q => LFSR_in(12),
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[29]\,
      Q => \ipc_data_reg_n_0_[29]\,
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[2]\,
      Q => \ipc_data_reg_n_0_[2]\,
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[30]\,
      Q => \ipc_data_reg_n_0_[30]\,
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \ipc_data[31]_i_1_n_0\,
      Q => \ipc_data_reg_n_0_[31]\,
      R => '0'
    );
\ipc_data_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[3]\,
      Q => \ipc_data_reg_n_0_[3]\,
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[4]\,
      Q => \ipc_data_reg_n_0_[4]\,
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[5]\,
      Q => \ipc_data_reg_n_0_[5]\,
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[6]\,
      Q => \ipc_data_reg_n_0_[6]\,
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[7]\,
      Q => \ipc_data_reg_n_0_[7]\,
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[8]\,
      Q => \ipc_data_reg_n_0_[8]\,
      R => \ipc_data[30]_i_1_n_0\
    );
\ipc_data_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => \misodata_reg_n_0_[9]\,
      Q => \ipc_data_reg_n_0_[9]\,
      R => \ipc_data[30]_i_1_n_0\
    );
ipc_reset_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \fsm_State_reg_n_0_[1]\,
      I1 => \fsm_State_reg_n_0_[0]\,
      I2 => \fsm_State_reg_n_0_[2]\,
      O => ipc_reset_i_1_n_0
    );
ipc_reset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => ipc_reset_i_1_n_0,
      Q => ipc_reset,
      R => '0'
    );
ipc_write_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
        port map (
      I0 => \misobitptr[4]_i_3_n_0\,
      I1 => \fsm_skip_counter_reg_n_0_[25]\,
      I2 => \fsm_skip_counter_reg_n_0_[28]\,
      I3 => \fsm_skip_counter_reg_n_0_[30]\,
      I4 => \fsm_skip_counter_reg_n_0_[24]\,
      I5 => \fsm_skip_counter[31]_i_3_n_0\,
      O => ipc_write_i_1_n_0
    );
ipc_write_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => clk_en,
      D => ipc_write_i_1_n_0,
      Q => ipc_write,
      R => \ipc_data[30]_i_1_n_0\
    );
lfsr_decoder_h: entity work.blok_controller_0_0_LFSR_convert_LUT
     port map (
      D(12 downto 0) => LFSR_in(12 downto 0),
      Q(12 downto 0) => LFSR_in_i(12 downto 0),
      ctl_clk_i => ctl_clk_i,
      ena => ena
    );
lfsr_decoder_l: entity work.blok_controller_0_0_LFSR_convert_LUT_0
     port map (
      D(25 downto 13) => datmem_data_o0_in(28 downto 16),
      D(12 downto 0) => datmem_data_o0_in(12 downto 0),
      \LFSR_in_i_reg[12]_0\(12) => \ipc_data_reg_n_0_[12]\,
      \LFSR_in_i_reg[12]_0\(11) => \ipc_data_reg_n_0_[11]\,
      \LFSR_in_i_reg[12]_0\(10) => \ipc_data_reg_n_0_[10]\,
      \LFSR_in_i_reg[12]_0\(9) => \ipc_data_reg_n_0_[9]\,
      \LFSR_in_i_reg[12]_0\(8) => \ipc_data_reg_n_0_[8]\,
      \LFSR_in_i_reg[12]_0\(7) => \ipc_data_reg_n_0_[7]\,
      \LFSR_in_i_reg[12]_0\(6) => \ipc_data_reg_n_0_[6]\,
      \LFSR_in_i_reg[12]_0\(5) => \ipc_data_reg_n_0_[5]\,
      \LFSR_in_i_reg[12]_0\(4) => \ipc_data_reg_n_0_[4]\,
      \LFSR_in_i_reg[12]_0\(3) => \ipc_data_reg_n_0_[3]\,
      \LFSR_in_i_reg[12]_0\(2) => \ipc_data_reg_n_0_[2]\,
      \LFSR_in_i_reg[12]_0\(1) => \ipc_data_reg_n_0_[1]\,
      \LFSR_in_i_reg[12]_0\(0) => \ipc_data_reg_n_0_[0]\,
      Q(12 downto 0) => LFSR_in_i(12 downto 0),
      ctl_clk_i => ctl_clk_i,
      \datmem_data_o_reg[28]\(12 downto 0) => LFSR_in(12 downto 0),
      ena => ena,
      \writer_state__0\(0) => \writer_state__0\(0)
    );
minusOp_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => minusOp_carry_n_0,
      CO(2) => minusOp_carry_n_1,
      CO(1) => minusOp_carry_n_2,
      CO(0) => minusOp_carry_n_3,
      CYINIT => ctl_reg_bits_to_write(0),
      DI(3 downto 0) => ctl_reg_bits_to_write(4 downto 1),
      O(3 downto 0) => minusOp(4 downto 1),
      S(3) => minusOp_carry_i_1_n_0,
      S(2) => minusOp_carry_i_2_n_0,
      S(1) => minusOp_carry_i_3_n_0,
      S(0) => minusOp_carry_i_4_n_0
    );
\minusOp_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => minusOp_carry_n_0,
      CO(3) => \minusOp_carry__0_n_0\,
      CO(2) => \minusOp_carry__0_n_1\,
      CO(1) => \minusOp_carry__0_n_2\,
      CO(0) => \minusOp_carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => ctl_reg_bits_to_write(8 downto 5),
      O(3 downto 0) => minusOp(8 downto 5),
      S(3) => \minusOp_carry__0_i_1_n_0\,
      S(2) => \minusOp_carry__0_i_2_n_0\,
      S(1) => \minusOp_carry__0_i_3_n_0\,
      S(0) => \minusOp_carry__0_i_4_n_0\
    );
\minusOp_carry__0_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(8),
      O => \minusOp_carry__0_i_1_n_0\
    );
\minusOp_carry__0_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(7),
      O => \minusOp_carry__0_i_2_n_0\
    );
\minusOp_carry__0_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(6),
      O => \minusOp_carry__0_i_3_n_0\
    );
\minusOp_carry__0_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(5),
      O => \minusOp_carry__0_i_4_n_0\
    );
\minusOp_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \minusOp_carry__0_n_0\,
      CO(3) => \minusOp_carry__1_n_0\,
      CO(2) => \minusOp_carry__1_n_1\,
      CO(1) => \minusOp_carry__1_n_2\,
      CO(0) => \minusOp_carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => ctl_reg_bits_to_write(12 downto 9),
      O(3 downto 0) => minusOp(12 downto 9),
      S(3) => \minusOp_carry__1_i_1_n_0\,
      S(2) => \minusOp_carry__1_i_2_n_0\,
      S(1) => \minusOp_carry__1_i_3_n_0\,
      S(0) => \minusOp_carry__1_i_4_n_0\
    );
\minusOp_carry__1_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(12),
      O => \minusOp_carry__1_i_1_n_0\
    );
\minusOp_carry__1_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(11),
      O => \minusOp_carry__1_i_2_n_0\
    );
\minusOp_carry__1_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(10),
      O => \minusOp_carry__1_i_3_n_0\
    );
\minusOp_carry__1_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(9),
      O => \minusOp_carry__1_i_4_n_0\
    );
\minusOp_carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \minusOp_carry__1_n_0\,
      CO(3) => \minusOp_carry__2_n_0\,
      CO(2) => \minusOp_carry__2_n_1\,
      CO(1) => \minusOp_carry__2_n_2\,
      CO(0) => \minusOp_carry__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => ctl_reg_bits_to_write(16 downto 13),
      O(3 downto 0) => minusOp(16 downto 13),
      S(3) => \minusOp_carry__2_i_1_n_0\,
      S(2) => \minusOp_carry__2_i_2_n_0\,
      S(1) => \minusOp_carry__2_i_3_n_0\,
      S(0) => \minusOp_carry__2_i_4_n_0\
    );
\minusOp_carry__2_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(16),
      O => \minusOp_carry__2_i_1_n_0\
    );
\minusOp_carry__2_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(15),
      O => \minusOp_carry__2_i_2_n_0\
    );
\minusOp_carry__2_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(14),
      O => \minusOp_carry__2_i_3_n_0\
    );
\minusOp_carry__2_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(13),
      O => \minusOp_carry__2_i_4_n_0\
    );
\minusOp_carry__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \minusOp_carry__2_n_0\,
      CO(3) => \minusOp_carry__3_n_0\,
      CO(2) => \minusOp_carry__3_n_1\,
      CO(1) => \minusOp_carry__3_n_2\,
      CO(0) => \minusOp_carry__3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => ctl_reg_bits_to_write(20 downto 17),
      O(3 downto 0) => minusOp(20 downto 17),
      S(3) => \minusOp_carry__3_i_1_n_0\,
      S(2) => \minusOp_carry__3_i_2_n_0\,
      S(1) => \minusOp_carry__3_i_3_n_0\,
      S(0) => \minusOp_carry__3_i_4_n_0\
    );
\minusOp_carry__3_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(20),
      O => \minusOp_carry__3_i_1_n_0\
    );
\minusOp_carry__3_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(19),
      O => \minusOp_carry__3_i_2_n_0\
    );
\minusOp_carry__3_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(18),
      O => \minusOp_carry__3_i_3_n_0\
    );
\minusOp_carry__3_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(17),
      O => \minusOp_carry__3_i_4_n_0\
    );
\minusOp_carry__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \minusOp_carry__3_n_0\,
      CO(3) => \minusOp_carry__4_n_0\,
      CO(2) => \minusOp_carry__4_n_1\,
      CO(1) => \minusOp_carry__4_n_2\,
      CO(0) => \minusOp_carry__4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => ctl_reg_bits_to_write(24 downto 21),
      O(3 downto 0) => minusOp(24 downto 21),
      S(3) => \minusOp_carry__4_i_1_n_0\,
      S(2) => \minusOp_carry__4_i_2_n_0\,
      S(1) => \minusOp_carry__4_i_3_n_0\,
      S(0) => \minusOp_carry__4_i_4_n_0\
    );
\minusOp_carry__4_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(24),
      O => \minusOp_carry__4_i_1_n_0\
    );
\minusOp_carry__4_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(23),
      O => \minusOp_carry__4_i_2_n_0\
    );
\minusOp_carry__4_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(22),
      O => \minusOp_carry__4_i_3_n_0\
    );
\minusOp_carry__4_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(21),
      O => \minusOp_carry__4_i_4_n_0\
    );
\minusOp_carry__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \minusOp_carry__4_n_0\,
      CO(3) => \minusOp_carry__5_n_0\,
      CO(2) => \minusOp_carry__5_n_1\,
      CO(1) => \minusOp_carry__5_n_2\,
      CO(0) => \minusOp_carry__5_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => ctl_reg_bits_to_write(28 downto 25),
      O(3 downto 0) => minusOp(28 downto 25),
      S(3) => \minusOp_carry__5_i_1_n_0\,
      S(2) => \minusOp_carry__5_i_2_n_0\,
      S(1) => \minusOp_carry__5_i_3_n_0\,
      S(0) => \minusOp_carry__5_i_4_n_0\
    );
\minusOp_carry__5_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(28),
      O => \minusOp_carry__5_i_1_n_0\
    );
\minusOp_carry__5_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(27),
      O => \minusOp_carry__5_i_2_n_0\
    );
\minusOp_carry__5_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(26),
      O => \minusOp_carry__5_i_3_n_0\
    );
\minusOp_carry__5_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(25),
      O => \minusOp_carry__5_i_4_n_0\
    );
\minusOp_carry__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \minusOp_carry__5_n_0\,
      CO(3 downto 2) => \NLW_minusOp_carry__6_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \minusOp_carry__6_n_2\,
      CO(0) => \minusOp_carry__6_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => ctl_reg_bits_to_write(30 downto 29),
      O(3) => \NLW_minusOp_carry__6_O_UNCONNECTED\(3),
      O(2 downto 0) => minusOp(31 downto 29),
      S(3) => '0',
      S(2) => \minusOp_carry__6_i_1_n_0\,
      S(1) => \minusOp_carry__6_i_2_n_0\,
      S(0) => \minusOp_carry__6_i_3_n_0\
    );
\minusOp_carry__6_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(31),
      O => \minusOp_carry__6_i_1_n_0\
    );
\minusOp_carry__6_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(30),
      O => \minusOp_carry__6_i_2_n_0\
    );
\minusOp_carry__6_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(29),
      O => \minusOp_carry__6_i_3_n_0\
    );
minusOp_carry_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(4),
      O => minusOp_carry_i_1_n_0
    );
minusOp_carry_i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(3),
      O => minusOp_carry_i_2_n_0
    );
minusOp_carry_i_3: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(2),
      O => minusOp_carry_i_3_n_0
    );
minusOp_carry_i_4: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ctl_reg_bits_to_write(1),
      O => minusOp_carry_i_4_n_0
    );
\misobitptr[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000A8AA"
    )
        port map (
      I0 => \fsm_State_reg_n_0_[1]\,
      I1 => \misobitptr[4]_i_3_n_0\,
      I2 => \misobitptr[4]_i_4_n_0\,
      I3 => \fsm_skip_counter[31]_i_3_n_0\,
      I4 => \misobitptr_reg_n_0_[0]\,
      O => \misobitptr[0]_i_1_n_0\
    );
\misobitptr[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000A8AAA8AA0000"
    )
        port map (
      I0 => \fsm_State_reg_n_0_[1]\,
      I1 => \misobitptr[4]_i_3_n_0\,
      I2 => \misobitptr[4]_i_4_n_0\,
      I3 => \fsm_skip_counter[31]_i_3_n_0\,
      I4 => \misobitptr_reg_n_0_[1]\,
      I5 => \misobitptr_reg_n_0_[0]\,
      O => \misobitptr[1]_i_1_n_0\
    );
\misobitptr[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \misobitptr_reg_n_0_[2]\,
      I1 => \misobitptr_reg_n_0_[0]\,
      I2 => \misobitptr_reg_n_0_[1]\,
      O => \misobitptr[2]_i_1_n_0\
    );
\misobitptr[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \misobitptr_reg_n_0_[3]\,
      I1 => \misobitptr_reg_n_0_[1]\,
      I2 => \misobitptr_reg_n_0_[0]\,
      I3 => \misobitptr_reg_n_0_[2]\,
      O => \misobitptr[3]_i_1_n_0\
    );
\misobitptr[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"222A2222"
    )
        port map (
      I0 => misobitptr,
      I1 => \fsm_State_reg_n_0_[1]\,
      I2 => \misobitptr[4]_i_3_n_0\,
      I3 => \misobitptr[4]_i_4_n_0\,
      I4 => \fsm_skip_counter[31]_i_3_n_0\,
      O => \misobitptr[4]_i_1_n_0\
    );
\misobitptr[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \misobitptr_reg_n_0_[4]\,
      I1 => \misobitptr_reg_n_0_[3]\,
      I2 => \misobitptr_reg_n_0_[2]\,
      I3 => \misobitptr_reg_n_0_[0]\,
      I4 => \misobitptr_reg_n_0_[1]\,
      O => \misobitptr[4]_i_2_n_0\
    );
\misobitptr[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF8880"
    )
        port map (
      I0 => \fsm_skip_counter_reg_n_0_[5]\,
      I1 => \fsm_skip_counter_reg_n_0_[6]\,
      I2 => \fsm_skip_counter_reg_n_0_[3]\,
      I3 => \fsm_skip_counter_reg_n_0_[4]\,
      I4 => \misobitptr[4]_i_5_n_0\,
      I5 => \fsm_skip_counter_reg_n_0_[9]\,
      O => \misobitptr[4]_i_3_n_0\
    );
\misobitptr[4]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \fsm_skip_counter_reg_n_0_[25]\,
      I1 => \fsm_skip_counter_reg_n_0_[28]\,
      I2 => \fsm_skip_counter_reg_n_0_[30]\,
      I3 => \fsm_skip_counter_reg_n_0_[24]\,
      O => \misobitptr[4]_i_4_n_0\
    );
\misobitptr[4]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \fsm_skip_counter_reg_n_0_[8]\,
      I1 => \ctl_reg_options_reg_n_0_[0]\,
      O => \misobitptr[4]_i_5_n_0\
    );
\misobitptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \misobitptr[0]_i_1_n_0\,
      Q => \misobitptr_reg_n_0_[0]\,
      R => '0'
    );
\misobitptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \misobitptr[1]_i_1_n_0\,
      Q => \misobitptr_reg_n_0_[1]\,
      R => '0'
    );
\misobitptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \misobitptr[2]_i_1_n_0\,
      Q => \misobitptr_reg_n_0_[2]\,
      R => \misobitptr[4]_i_1_n_0\
    );
\misobitptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \misobitptr[3]_i_1_n_0\,
      Q => \misobitptr_reg_n_0_[3]\,
      R => \misobitptr[4]_i_1_n_0\
    );
\misobitptr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => misobitptr,
      D => \misobitptr[4]_i_2_n_0\,
      Q => \misobitptr_reg_n_0_[4]\,
      R => \misobitptr[4]_i_1_n_0\
    );
\misodata[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8FFF8F8F80008080"
    )
        port map (
      I0 => miso_i,
      I1 => \fsm_State_reg_n_0_[1]\,
      I2 => misobitptr,
      I3 => \misodata[0]_i_2_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[0]\,
      O => \misodata[0]_i_1_n_0\
    );
\misodata[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \misobitptr_reg_n_0_[1]\,
      I1 => \misobitptr_reg_n_0_[0]\,
      I2 => \misobitptr_reg_n_0_[2]\,
      I3 => \misobitptr_reg_n_0_[4]\,
      I4 => \misobitptr_reg_n_0_[3]\,
      O => \misodata[0]_i_2_n_0\
    );
\misodata[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[26]_i_2_n_0\,
      I3 => \misodata[15]_i_2_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[10]\,
      O => \misodata[10]_i_1_n_0\
    );
\misodata[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[27]_i_2_n_0\,
      I3 => \misodata[15]_i_2_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[11]\,
      O => \misodata[11]_i_1_n_0\
    );
\misodata[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[28]_i_2_n_0\,
      I3 => \misodata[15]_i_2_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[12]\,
      O => \misodata[12]_i_1_n_0\
    );
\misodata[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[29]_i_2_n_0\,
      I3 => \misodata[15]_i_2_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[13]\,
      O => \misodata[13]_i_1_n_0\
    );
\misodata[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[30]_i_4_n_0\,
      I3 => \misodata[15]_i_2_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[14]\,
      O => \misodata[14]_i_1_n_0\
    );
\misodata[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[23]_i_2_n_0\,
      I3 => \misodata[15]_i_2_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[15]\,
      O => \misodata[15]_i_1_n_0\
    );
\misodata[15]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \misobitptr_reg_n_0_[4]\,
      I1 => \misobitptr_reg_n_0_[3]\,
      I2 => \fsm_State_reg_n_0_[1]\,
      O => \misodata[15]_i_2_n_0\
    );
\misodata[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[24]_i_2_n_0\,
      I3 => \misodata[23]_i_3_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[16]\,
      O => \misodata[16]_i_1_n_0\
    );
\misodata[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[25]_i_2_n_0\,
      I3 => \misodata[23]_i_3_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[17]\,
      O => \misodata[17]_i_1_n_0\
    );
\misodata[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[26]_i_2_n_0\,
      I3 => \misodata[23]_i_3_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[18]\,
      O => \misodata[18]_i_1_n_0\
    );
\misodata[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[27]_i_2_n_0\,
      I3 => \misodata[23]_i_3_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[19]\,
      O => \misodata[19]_i_1_n_0\
    );
\misodata[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[25]_i_2_n_0\,
      I3 => \misodata[7]_i_2_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[1]\,
      O => \misodata[1]_i_1_n_0\
    );
\misodata[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[28]_i_2_n_0\,
      I3 => \misodata[23]_i_3_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[20]\,
      O => \misodata[20]_i_1_n_0\
    );
\misodata[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[29]_i_2_n_0\,
      I3 => \misodata[23]_i_3_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[21]\,
      O => \misodata[21]_i_1_n_0\
    );
\misodata[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[30]_i_4_n_0\,
      I3 => \misodata[23]_i_3_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[22]\,
      O => \misodata[22]_i_1_n_0\
    );
\misodata[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[23]_i_2_n_0\,
      I3 => \misodata[23]_i_3_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[23]\,
      O => \misodata[23]_i_1_n_0\
    );
\misodata[23]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \misobitptr_reg_n_0_[2]\,
      I1 => \misobitptr_reg_n_0_[0]\,
      I2 => \misobitptr_reg_n_0_[1]\,
      O => \misodata[23]_i_2_n_0\
    );
\misodata[23]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \fsm_State_reg_n_0_[1]\,
      I1 => \misobitptr_reg_n_0_[3]\,
      I2 => \misobitptr_reg_n_0_[4]\,
      O => \misodata[23]_i_3_n_0\
    );
\misodata[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[24]_i_2_n_0\,
      I3 => \misodata[30]_i_5_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[24]\,
      O => \misodata[24]_i_1_n_0\
    );
\misodata[24]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \misobitptr_reg_n_0_[2]\,
      I1 => \misobitptr_reg_n_0_[0]\,
      I2 => \misobitptr_reg_n_0_[1]\,
      O => \misodata[24]_i_2_n_0\
    );
\misodata[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[25]_i_2_n_0\,
      I3 => \misodata[30]_i_5_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[25]\,
      O => \misodata[25]_i_1_n_0\
    );
\misodata[25]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \misobitptr_reg_n_0_[2]\,
      I1 => \misobitptr_reg_n_0_[0]\,
      I2 => \misobitptr_reg_n_0_[1]\,
      O => \misodata[25]_i_2_n_0\
    );
\misodata[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[26]_i_2_n_0\,
      I3 => \misodata[30]_i_5_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[26]\,
      O => \misodata[26]_i_1_n_0\
    );
\misodata[26]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \misobitptr_reg_n_0_[2]\,
      I1 => \misobitptr_reg_n_0_[1]\,
      I2 => \misobitptr_reg_n_0_[0]\,
      O => \misodata[26]_i_2_n_0\
    );
\misodata[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[27]_i_2_n_0\,
      I3 => \misodata[30]_i_5_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[27]\,
      O => \misodata[27]_i_1_n_0\
    );
\misodata[27]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \misobitptr_reg_n_0_[2]\,
      I1 => \misobitptr_reg_n_0_[0]\,
      I2 => \misobitptr_reg_n_0_[1]\,
      O => \misodata[27]_i_2_n_0\
    );
\misodata[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[28]_i_2_n_0\,
      I3 => \misodata[30]_i_5_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[28]\,
      O => \misodata[28]_i_1_n_0\
    );
\misodata[28]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \misobitptr_reg_n_0_[2]\,
      I1 => \misobitptr_reg_n_0_[0]\,
      I2 => \misobitptr_reg_n_0_[1]\,
      O => \misodata[28]_i_2_n_0\
    );
\misodata[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[29]_i_2_n_0\,
      I3 => \misodata[30]_i_5_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[29]\,
      O => \misodata[29]_i_1_n_0\
    );
\misodata[29]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \misobitptr_reg_n_0_[2]\,
      I1 => \misobitptr_reg_n_0_[0]\,
      I2 => \misobitptr_reg_n_0_[1]\,
      O => \misodata[29]_i_2_n_0\
    );
\misodata[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[26]_i_2_n_0\,
      I3 => \misodata[7]_i_2_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[2]\,
      O => \misodata[2]_i_1_n_0\
    );
\misodata[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[30]_i_4_n_0\,
      I3 => \misodata[30]_i_5_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[30]\,
      O => \misodata[30]_i_1_n_0\
    );
\misodata[30]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => miso_i,
      I1 => \fsm_State_reg_n_0_[1]\,
      O => \misodata[30]_i_2_n_0\
    );
\misodata[30]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00B0"
    )
        port map (
      I0 => \fsm_State_reg_n_0_[0]\,
      I1 => \fsm_State_reg_n_0_[1]\,
      I2 => clk_en,
      I3 => \fsm_State_reg_n_0_[2]\,
      O => \misodata[30]_i_3_n_0\
    );
\misodata[30]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \misobitptr_reg_n_0_[2]\,
      I1 => \misobitptr_reg_n_0_[1]\,
      I2 => \misobitptr_reg_n_0_[0]\,
      O => \misodata[30]_i_4_n_0\
    );
\misodata[30]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \misobitptr_reg_n_0_[3]\,
      I1 => \fsm_State_reg_n_0_[1]\,
      I2 => \misobitptr_reg_n_0_[4]\,
      O => \misodata[30]_i_5_n_0\
    );
\misodata[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8FFF8F8F80008080"
    )
        port map (
      I0 => miso_i,
      I1 => \fsm_State_reg_n_0_[1]\,
      I2 => misobitptr,
      I3 => \misodata[31]_i_2_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => data0,
      O => \misodata[31]_i_1_n_0\
    );
\misodata[31]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \misobitptr_reg_n_0_[3]\,
      I1 => \misobitptr_reg_n_0_[2]\,
      I2 => \misobitptr_reg_n_0_[0]\,
      I3 => \misobitptr_reg_n_0_[1]\,
      I4 => \misobitptr_reg_n_0_[4]\,
      O => \misodata[31]_i_2_n_0\
    );
\misodata[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[27]_i_2_n_0\,
      I3 => \misodata[7]_i_2_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[3]\,
      O => \misodata[3]_i_1_n_0\
    );
\misodata[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[28]_i_2_n_0\,
      I3 => \misodata[7]_i_2_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[4]\,
      O => \misodata[4]_i_1_n_0\
    );
\misodata[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[29]_i_2_n_0\,
      I3 => \misodata[7]_i_2_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[5]\,
      O => \misodata[5]_i_1_n_0\
    );
\misodata[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[30]_i_4_n_0\,
      I3 => \misodata[7]_i_2_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[6]\,
      O => \misodata[6]_i_1_n_0\
    );
\misodata[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[23]_i_2_n_0\,
      I3 => \misodata[7]_i_2_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[7]\,
      O => \misodata[7]_i_1_n_0\
    );
\misodata[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \misobitptr_reg_n_0_[4]\,
      I1 => \fsm_State_reg_n_0_[1]\,
      I2 => \misobitptr_reg_n_0_[3]\,
      O => \misodata[7]_i_2_n_0\
    );
\misodata[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[24]_i_2_n_0\,
      I3 => \misodata[15]_i_2_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[8]\,
      O => \misodata[8]_i_1_n_0\
    );
\misodata[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFBBBB00808888"
    )
        port map (
      I0 => \misodata[30]_i_2_n_0\,
      I1 => \misodata[30]_i_3_n_0\,
      I2 => \misodata[25]_i_2_n_0\,
      I3 => \misodata[15]_i_2_n_0\,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \misodata_reg_n_0_[9]\,
      O => \misodata[9]_i_1_n_0\
    );
\misodata_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[0]_i_1_n_0\,
      Q => \misodata_reg_n_0_[0]\,
      R => '0'
    );
\misodata_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[10]_i_1_n_0\,
      Q => \misodata_reg_n_0_[10]\,
      R => '0'
    );
\misodata_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[11]_i_1_n_0\,
      Q => \misodata_reg_n_0_[11]\,
      R => '0'
    );
\misodata_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[12]_i_1_n_0\,
      Q => \misodata_reg_n_0_[12]\,
      R => '0'
    );
\misodata_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[13]_i_1_n_0\,
      Q => \misodata_reg_n_0_[13]\,
      R => '0'
    );
\misodata_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[14]_i_1_n_0\,
      Q => \misodata_reg_n_0_[14]\,
      R => '0'
    );
\misodata_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[15]_i_1_n_0\,
      Q => \misodata_reg_n_0_[15]\,
      R => '0'
    );
\misodata_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[16]_i_1_n_0\,
      Q => \misodata_reg_n_0_[16]\,
      R => '0'
    );
\misodata_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[17]_i_1_n_0\,
      Q => \misodata_reg_n_0_[17]\,
      R => '0'
    );
\misodata_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[18]_i_1_n_0\,
      Q => \misodata_reg_n_0_[18]\,
      R => '0'
    );
\misodata_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[19]_i_1_n_0\,
      Q => \misodata_reg_n_0_[19]\,
      R => '0'
    );
\misodata_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[1]_i_1_n_0\,
      Q => \misodata_reg_n_0_[1]\,
      R => '0'
    );
\misodata_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[20]_i_1_n_0\,
      Q => \misodata_reg_n_0_[20]\,
      R => '0'
    );
\misodata_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[21]_i_1_n_0\,
      Q => \misodata_reg_n_0_[21]\,
      R => '0'
    );
\misodata_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[22]_i_1_n_0\,
      Q => \misodata_reg_n_0_[22]\,
      R => '0'
    );
\misodata_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[23]_i_1_n_0\,
      Q => \misodata_reg_n_0_[23]\,
      R => '0'
    );
\misodata_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[24]_i_1_n_0\,
      Q => \misodata_reg_n_0_[24]\,
      R => '0'
    );
\misodata_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[25]_i_1_n_0\,
      Q => \misodata_reg_n_0_[25]\,
      R => '0'
    );
\misodata_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[26]_i_1_n_0\,
      Q => \misodata_reg_n_0_[26]\,
      R => '0'
    );
\misodata_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[27]_i_1_n_0\,
      Q => \misodata_reg_n_0_[27]\,
      R => '0'
    );
\misodata_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[28]_i_1_n_0\,
      Q => \misodata_reg_n_0_[28]\,
      R => '0'
    );
\misodata_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[29]_i_1_n_0\,
      Q => \misodata_reg_n_0_[29]\,
      R => '0'
    );
\misodata_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[2]_i_1_n_0\,
      Q => \misodata_reg_n_0_[2]\,
      R => '0'
    );
\misodata_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[30]_i_1_n_0\,
      Q => \misodata_reg_n_0_[30]\,
      R => '0'
    );
\misodata_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[31]_i_1_n_0\,
      Q => data0,
      R => '0'
    );
\misodata_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[3]_i_1_n_0\,
      Q => \misodata_reg_n_0_[3]\,
      R => '0'
    );
\misodata_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[4]_i_1_n_0\,
      Q => \misodata_reg_n_0_[4]\,
      R => '0'
    );
\misodata_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[5]_i_1_n_0\,
      Q => \misodata_reg_n_0_[5]\,
      R => '0'
    );
\misodata_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[6]_i_1_n_0\,
      Q => \misodata_reg_n_0_[6]\,
      R => '0'
    );
\misodata_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[7]_i_1_n_0\,
      Q => \misodata_reg_n_0_[7]\,
      R => '0'
    );
\misodata_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[8]_i_1_n_0\,
      Q => \misodata_reg_n_0_[8]\,
      R => '0'
    );
\misodata_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \misodata[9]_i_1_n_0\,
      Q => \misodata_reg_n_0_[9]\,
      R => '0'
    );
mosi_o_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E2FFFFFFE2FF0000"
    )
        port map (
      I0 => mosi_o_reg_i_2_n_0,
      I1 => sel0(4),
      I2 => mosi_o_reg_i_3_n_0,
      I3 => \fsm_State_reg_n_0_[1]\,
      I4 => \mosibitptr[4]_i_2_n_0\,
      I5 => \^mosi_o\,
      O => mosi_o_i_1_n_0
    );
mosi_o_i_10: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \mosidata_reg_n_0_[11]\,
      I1 => \mosidata_reg_n_0_[10]\,
      I2 => sel0(1),
      I3 => \mosidata_reg_n_0_[9]\,
      I4 => sel0(0),
      I5 => \mosidata_reg_n_0_[8]\,
      O => mosi_o_i_10_n_0
    );
mosi_o_i_11: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \mosidata_reg_n_0_[15]\,
      I1 => \mosidata_reg_n_0_[14]\,
      I2 => sel0(1),
      I3 => \mosidata_reg_n_0_[13]\,
      I4 => sel0(0),
      I5 => \mosidata_reg_n_0_[12]\,
      O => mosi_o_i_11_n_0
    );
mosi_o_i_12: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \mosidata_reg_n_0_[19]\,
      I1 => \mosidata_reg_n_0_[18]\,
      I2 => sel0(1),
      I3 => \mosidata_reg_n_0_[17]\,
      I4 => sel0(0),
      I5 => \mosidata_reg_n_0_[16]\,
      O => mosi_o_i_12_n_0
    );
mosi_o_i_13: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \mosidata_reg_n_0_[23]\,
      I1 => \mosidata_reg_n_0_[22]\,
      I2 => sel0(1),
      I3 => \mosidata_reg_n_0_[21]\,
      I4 => sel0(0),
      I5 => \mosidata_reg_n_0_[20]\,
      O => mosi_o_i_13_n_0
    );
mosi_o_i_14: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \mosidata_reg_n_0_[27]\,
      I1 => \mosidata_reg_n_0_[26]\,
      I2 => sel0(1),
      I3 => \mosidata_reg_n_0_[25]\,
      I4 => sel0(0),
      I5 => \mosidata_reg_n_0_[24]\,
      O => mosi_o_i_14_n_0
    );
mosi_o_i_15: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \mosidata_reg_n_0_[31]\,
      I1 => \mosidata_reg_n_0_[30]\,
      I2 => sel0(1),
      I3 => \mosidata_reg_n_0_[29]\,
      I4 => sel0(0),
      I5 => \mosidata_reg_n_0_[28]\,
      O => mosi_o_i_15_n_0
    );
mosi_o_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \mosidata_reg_n_0_[3]\,
      I1 => \mosidata_reg_n_0_[2]\,
      I2 => sel0(1),
      I3 => \mosidata_reg_n_0_[1]\,
      I4 => sel0(0),
      I5 => \mosidata_reg_n_0_[0]\,
      O => mosi_o_i_8_n_0
    );
mosi_o_i_9: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \mosidata_reg_n_0_[7]\,
      I1 => \mosidata_reg_n_0_[6]\,
      I2 => sel0(1),
      I3 => \mosidata_reg_n_0_[5]\,
      I4 => sel0(0),
      I5 => \mosidata_reg_n_0_[4]\,
      O => mosi_o_i_9_n_0
    );
mosi_o_reg: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => mosi_o_i_1_n_0,
      Q => \^mosi_o\,
      R => '0'
    );
mosi_o_reg_i_2: unisim.vcomponents.MUXF8
     port map (
      I0 => mosi_o_reg_i_4_n_0,
      I1 => mosi_o_reg_i_5_n_0,
      O => mosi_o_reg_i_2_n_0,
      S => sel0(3)
    );
mosi_o_reg_i_3: unisim.vcomponents.MUXF8
     port map (
      I0 => mosi_o_reg_i_6_n_0,
      I1 => mosi_o_reg_i_7_n_0,
      O => mosi_o_reg_i_3_n_0,
      S => sel0(3)
    );
mosi_o_reg_i_4: unisim.vcomponents.MUXF7
     port map (
      I0 => mosi_o_i_8_n_0,
      I1 => mosi_o_i_9_n_0,
      O => mosi_o_reg_i_4_n_0,
      S => sel0(2)
    );
mosi_o_reg_i_5: unisim.vcomponents.MUXF7
     port map (
      I0 => mosi_o_i_10_n_0,
      I1 => mosi_o_i_11_n_0,
      O => mosi_o_reg_i_5_n_0,
      S => sel0(2)
    );
mosi_o_reg_i_6: unisim.vcomponents.MUXF7
     port map (
      I0 => mosi_o_i_12_n_0,
      I1 => mosi_o_i_13_n_0,
      O => mosi_o_reg_i_6_n_0,
      S => sel0(2)
    );
mosi_o_reg_i_7: unisim.vcomponents.MUXF7
     port map (
      I0 => mosi_o_i_14_n_0,
      I1 => mosi_o_i_15_n_0,
      O => mosi_o_reg_i_7_n_0,
      S => sel0(2)
    );
\mosiaddress[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \mosibitptr[4]_i_2_n_0\,
      I1 => \fsm_State_reg_n_0_[1]\,
      O => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress[31]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0080AAAA"
    )
        port map (
      I0 => \mosibitptr[4]_i_2_n_0\,
      I1 => \mosiaddress[31]_i_3_n_0\,
      I2 => sel0(0),
      I3 => sel0(1),
      I4 => \fsm_State_reg_n_0_[1]\,
      O => mosiaddress
    );
\mosiaddress[31]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => sel0(3),
      I1 => sel0(2),
      I2 => sel0(4),
      O => \mosiaddress[31]_i_3_n_0\
    );
\mosiaddress_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__1_n_6\,
      Q => \mosiaddress_reg_n_0_[10]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__1_n_5\,
      Q => \mosiaddress_reg_n_0_[11]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__1_n_4\,
      Q => \mosiaddress_reg_n_0_[12]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__2_n_7\,
      Q => \mosiaddress_reg_n_0_[13]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__2_n_6\,
      Q => \mosiaddress_reg_n_0_[14]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__2_n_5\,
      Q => \mosiaddress_reg_n_0_[15]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__2_n_4\,
      Q => \mosiaddress_reg_n_0_[16]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__3_n_7\,
      Q => \mosiaddress_reg_n_0_[17]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__3_n_6\,
      Q => \mosiaddress_reg_n_0_[18]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__3_n_5\,
      Q => \mosiaddress_reg_n_0_[19]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry_n_7\,
      Q => \mosiaddress_reg_n_0_[1]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__3_n_4\,
      Q => \mosiaddress_reg_n_0_[20]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__4_n_7\,
      Q => \mosiaddress_reg_n_0_[21]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__4_n_6\,
      Q => \mosiaddress_reg_n_0_[22]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__4_n_5\,
      Q => \mosiaddress_reg_n_0_[23]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__4_n_4\,
      Q => \mosiaddress_reg_n_0_[24]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__5_n_7\,
      Q => \mosiaddress_reg_n_0_[25]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__5_n_6\,
      Q => \mosiaddress_reg_n_0_[26]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__5_n_5\,
      Q => \mosiaddress_reg_n_0_[27]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__5_n_4\,
      Q => \mosiaddress_reg_n_0_[28]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__6_n_7\,
      Q => \mosiaddress_reg_n_0_[29]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry_n_6\,
      Q => \mosiaddress_reg_n_0_[2]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__6_n_6\,
      Q => \mosiaddress_reg_n_0_[30]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__6_n_5\,
      Q => \mosiaddress_reg_n_0_[31]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry_n_5\,
      Q => \mosiaddress_reg_n_0_[3]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry_n_4\,
      Q => \mosiaddress_reg_n_0_[4]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__0_n_7\,
      Q => \mosiaddress_reg_n_0_[5]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__0_n_6\,
      Q => \mosiaddress_reg_n_0_[6]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__0_n_5\,
      Q => \mosiaddress_reg_n_0_[7]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__0_n_4\,
      Q => \mosiaddress_reg_n_0_[8]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosiaddress_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosiaddress,
      D => \plusOp_inferred__1/i__carry__1_n_7\,
      Q => \mosiaddress_reg_n_0_[9]\,
      R => \mosiaddress[31]_i_1_n_0\
    );
\mosibitptr[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => sel0(0),
      O => \mosibitptr[0]_i_1_n_0\
    );
\mosibitptr[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF4F00000080"
    )
        port map (
      I0 => sel0(0),
      I1 => \fsm_State_reg_n_0_[1]\,
      I2 => clk_en,
      I3 => \fsm_State_reg_n_0_[0]\,
      I4 => \fsm_State_reg_n_0_[2]\,
      I5 => sel0(1),
      O => \mosibitptr[1]_i_1_n_0\
    );
\mosibitptr[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => sel0(2),
      I1 => sel0(1),
      I2 => sel0(0),
      O => \mosibitptr[2]_i_1_n_0\
    );
\mosibitptr[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => sel0(3),
      I1 => sel0(0),
      I2 => sel0(1),
      I3 => sel0(2),
      O => \mosibitptr[3]_i_1_n_0\
    );
\mosibitptr[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \fsm_State_reg_n_0_[2]\,
      I1 => \fsm_State_reg_n_0_[0]\,
      I2 => clk_en,
      I3 => \fsm_State_reg_n_0_[1]\,
      O => \mosibitptr[4]_i_1_n_0\
    );
\mosibitptr[4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => clk_en,
      I1 => \fsm_State_reg_n_0_[0]\,
      I2 => \fsm_State_reg_n_0_[2]\,
      O => \mosibitptr[4]_i_2_n_0\
    );
\mosibitptr[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => sel0(4),
      I1 => sel0(3),
      I2 => sel0(2),
      I3 => sel0(1),
      I4 => sel0(0),
      O => \mosibitptr[4]_i_3_n_0\
    );
\mosibitptr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \mosibitptr[4]_i_2_n_0\,
      D => \mosibitptr[0]_i_1_n_0\,
      Q => sel0(0),
      R => \mosibitptr[4]_i_1_n_0\
    );
\mosibitptr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => \mosibitptr[1]_i_1_n_0\,
      Q => sel0(1),
      R => '0'
    );
\mosibitptr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \mosibitptr[4]_i_2_n_0\,
      D => \mosibitptr[2]_i_1_n_0\,
      Q => sel0(2),
      R => \mosibitptr[4]_i_1_n_0\
    );
\mosibitptr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \mosibitptr[4]_i_2_n_0\,
      D => \mosibitptr[3]_i_1_n_0\,
      Q => sel0(3),
      R => \mosibitptr[4]_i_1_n_0\
    );
\mosibitptr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \mosibitptr[4]_i_2_n_0\,
      D => \mosibitptr[4]_i_3_n_0\,
      Q => sel0(4),
      R => \mosibitptr[4]_i_1_n_0\
    );
\mosidata[31]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \fsm_State_reg_n_0_[1]\,
      I1 => clk_en,
      I2 => \fsm_State_reg_n_0_[0]\,
      I3 => \fsm_State_reg_n_0_[2]\,
      O => \mosidata[31]_i_1_n_0\
    );
\mosidata[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000055007500"
    )
        port map (
      I0 => \fsm_State_reg_n_0_[1]\,
      I1 => cfgmem_ena_o_i_2_n_0,
      I2 => sel0(0),
      I3 => clk_en,
      I4 => \fsm_State_reg_n_0_[0]\,
      I5 => \fsm_State_reg_n_0_[2]\,
      O => mosidata
    );
\mosidata_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(0),
      Q => \mosidata_reg_n_0_[0]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(10),
      Q => \mosidata_reg_n_0_[10]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(11),
      Q => \mosidata_reg_n_0_[11]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(12),
      Q => \mosidata_reg_n_0_[12]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(13),
      Q => \mosidata_reg_n_0_[13]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(14),
      Q => \mosidata_reg_n_0_[14]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(15),
      Q => \mosidata_reg_n_0_[15]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(16),
      Q => \mosidata_reg_n_0_[16]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(17),
      Q => \mosidata_reg_n_0_[17]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(18),
      Q => \mosidata_reg_n_0_[18]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(19),
      Q => \mosidata_reg_n_0_[19]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(1),
      Q => \mosidata_reg_n_0_[1]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(20),
      Q => \mosidata_reg_n_0_[20]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(21),
      Q => \mosidata_reg_n_0_[21]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(22),
      Q => \mosidata_reg_n_0_[22]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(23),
      Q => \mosidata_reg_n_0_[23]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(24),
      Q => \mosidata_reg_n_0_[24]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(25),
      Q => \mosidata_reg_n_0_[25]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(26),
      Q => \mosidata_reg_n_0_[26]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(27),
      Q => \mosidata_reg_n_0_[27]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(28),
      Q => \mosidata_reg_n_0_[28]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(29),
      Q => \mosidata_reg_n_0_[29]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(2),
      Q => \mosidata_reg_n_0_[2]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(30),
      Q => \mosidata_reg_n_0_[30]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(31),
      Q => \mosidata_reg_n_0_[31]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(3),
      Q => \mosidata_reg_n_0_[3]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(4),
      Q => \mosidata_reg_n_0_[4]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(5),
      Q => \mosidata_reg_n_0_[5]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(6),
      Q => \mosidata_reg_n_0_[6]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(7),
      Q => \mosidata_reg_n_0_[7]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(8),
      Q => \mosidata_reg_n_0_[8]\,
      R => \mosidata[31]_i_1_n_0\
    );
\mosidata_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => mosidata,
      D => cfgmem_data_i(9),
      Q => \mosidata_reg_n_0_[9]\,
      R => \mosidata[31]_i_1_n_0\
    );
\plusOp_inferred__1/i__carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \plusOp_inferred__1/i__carry_n_0\,
      CO(2) => \plusOp_inferred__1/i__carry_n_1\,
      CO(1) => \plusOp_inferred__1/i__carry_n_2\,
      CO(0) => \plusOp_inferred__1/i__carry_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => \mosiaddress_reg_n_0_[2]\,
      DI(0) => '0',
      O(3) => \plusOp_inferred__1/i__carry_n_4\,
      O(2) => \plusOp_inferred__1/i__carry_n_5\,
      O(1) => \plusOp_inferred__1/i__carry_n_6\,
      O(0) => \plusOp_inferred__1/i__carry_n_7\,
      S(3) => \mosiaddress_reg_n_0_[4]\,
      S(2) => \mosiaddress_reg_n_0_[3]\,
      S(1) => \i__carry_i_1_n_0\,
      S(0) => \mosiaddress_reg_n_0_[1]\
    );
\plusOp_inferred__1/i__carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \plusOp_inferred__1/i__carry_n_0\,
      CO(3) => \plusOp_inferred__1/i__carry__0_n_0\,
      CO(2) => \plusOp_inferred__1/i__carry__0_n_1\,
      CO(1) => \plusOp_inferred__1/i__carry__0_n_2\,
      CO(0) => \plusOp_inferred__1/i__carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \plusOp_inferred__1/i__carry__0_n_4\,
      O(2) => \plusOp_inferred__1/i__carry__0_n_5\,
      O(1) => \plusOp_inferred__1/i__carry__0_n_6\,
      O(0) => \plusOp_inferred__1/i__carry__0_n_7\,
      S(3) => \mosiaddress_reg_n_0_[8]\,
      S(2) => \mosiaddress_reg_n_0_[7]\,
      S(1) => \mosiaddress_reg_n_0_[6]\,
      S(0) => \mosiaddress_reg_n_0_[5]\
    );
\plusOp_inferred__1/i__carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \plusOp_inferred__1/i__carry__0_n_0\,
      CO(3) => \plusOp_inferred__1/i__carry__1_n_0\,
      CO(2) => \plusOp_inferred__1/i__carry__1_n_1\,
      CO(1) => \plusOp_inferred__1/i__carry__1_n_2\,
      CO(0) => \plusOp_inferred__1/i__carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \plusOp_inferred__1/i__carry__1_n_4\,
      O(2) => \plusOp_inferred__1/i__carry__1_n_5\,
      O(1) => \plusOp_inferred__1/i__carry__1_n_6\,
      O(0) => \plusOp_inferred__1/i__carry__1_n_7\,
      S(3) => \mosiaddress_reg_n_0_[12]\,
      S(2) => \mosiaddress_reg_n_0_[11]\,
      S(1) => \mosiaddress_reg_n_0_[10]\,
      S(0) => \mosiaddress_reg_n_0_[9]\
    );
\plusOp_inferred__1/i__carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \plusOp_inferred__1/i__carry__1_n_0\,
      CO(3) => \plusOp_inferred__1/i__carry__2_n_0\,
      CO(2) => \plusOp_inferred__1/i__carry__2_n_1\,
      CO(1) => \plusOp_inferred__1/i__carry__2_n_2\,
      CO(0) => \plusOp_inferred__1/i__carry__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \plusOp_inferred__1/i__carry__2_n_4\,
      O(2) => \plusOp_inferred__1/i__carry__2_n_5\,
      O(1) => \plusOp_inferred__1/i__carry__2_n_6\,
      O(0) => \plusOp_inferred__1/i__carry__2_n_7\,
      S(3) => \mosiaddress_reg_n_0_[16]\,
      S(2) => \mosiaddress_reg_n_0_[15]\,
      S(1) => \mosiaddress_reg_n_0_[14]\,
      S(0) => \mosiaddress_reg_n_0_[13]\
    );
\plusOp_inferred__1/i__carry__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \plusOp_inferred__1/i__carry__2_n_0\,
      CO(3) => \plusOp_inferred__1/i__carry__3_n_0\,
      CO(2) => \plusOp_inferred__1/i__carry__3_n_1\,
      CO(1) => \plusOp_inferred__1/i__carry__3_n_2\,
      CO(0) => \plusOp_inferred__1/i__carry__3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \plusOp_inferred__1/i__carry__3_n_4\,
      O(2) => \plusOp_inferred__1/i__carry__3_n_5\,
      O(1) => \plusOp_inferred__1/i__carry__3_n_6\,
      O(0) => \plusOp_inferred__1/i__carry__3_n_7\,
      S(3) => \mosiaddress_reg_n_0_[20]\,
      S(2) => \mosiaddress_reg_n_0_[19]\,
      S(1) => \mosiaddress_reg_n_0_[18]\,
      S(0) => \mosiaddress_reg_n_0_[17]\
    );
\plusOp_inferred__1/i__carry__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \plusOp_inferred__1/i__carry__3_n_0\,
      CO(3) => \plusOp_inferred__1/i__carry__4_n_0\,
      CO(2) => \plusOp_inferred__1/i__carry__4_n_1\,
      CO(1) => \plusOp_inferred__1/i__carry__4_n_2\,
      CO(0) => \plusOp_inferred__1/i__carry__4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \plusOp_inferred__1/i__carry__4_n_4\,
      O(2) => \plusOp_inferred__1/i__carry__4_n_5\,
      O(1) => \plusOp_inferred__1/i__carry__4_n_6\,
      O(0) => \plusOp_inferred__1/i__carry__4_n_7\,
      S(3) => \mosiaddress_reg_n_0_[24]\,
      S(2) => \mosiaddress_reg_n_0_[23]\,
      S(1) => \mosiaddress_reg_n_0_[22]\,
      S(0) => \mosiaddress_reg_n_0_[21]\
    );
\plusOp_inferred__1/i__carry__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \plusOp_inferred__1/i__carry__4_n_0\,
      CO(3) => \plusOp_inferred__1/i__carry__5_n_0\,
      CO(2) => \plusOp_inferred__1/i__carry__5_n_1\,
      CO(1) => \plusOp_inferred__1/i__carry__5_n_2\,
      CO(0) => \plusOp_inferred__1/i__carry__5_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \plusOp_inferred__1/i__carry__5_n_4\,
      O(2) => \plusOp_inferred__1/i__carry__5_n_5\,
      O(1) => \plusOp_inferred__1/i__carry__5_n_6\,
      O(0) => \plusOp_inferred__1/i__carry__5_n_7\,
      S(3) => \mosiaddress_reg_n_0_[28]\,
      S(2) => \mosiaddress_reg_n_0_[27]\,
      S(1) => \mosiaddress_reg_n_0_[26]\,
      S(0) => \mosiaddress_reg_n_0_[25]\
    );
\plusOp_inferred__1/i__carry__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \plusOp_inferred__1/i__carry__5_n_0\,
      CO(3 downto 2) => \NLW_plusOp_inferred__1/i__carry__6_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \plusOp_inferred__1/i__carry__6_n_2\,
      CO(0) => \plusOp_inferred__1/i__carry__6_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_plusOp_inferred__1/i__carry__6_O_UNCONNECTED\(3),
      O(2) => \plusOp_inferred__1/i__carry__6_n_5\,
      O(1) => \plusOp_inferred__1/i__carry__6_n_6\,
      O(0) => \plusOp_inferred__1/i__carry__6_n_7\,
      S(3) => '0',
      S(2) => \mosiaddress_reg_n_0_[31]\,
      S(1) => \mosiaddress_reg_n_0_[30]\,
      S(0) => \mosiaddress_reg_n_0_[29]\
    );
\plusOp_inferred__4/i__carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \plusOp_inferred__4/i__carry_n_0\,
      CO(2) => \plusOp_inferred__4/i__carry_n_1\,
      CO(1) => \plusOp_inferred__4/i__carry_n_2\,
      CO(0) => \plusOp_inferred__4/i__carry_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => \writer_address__0\(2),
      DI(0) => '0',
      O(3 downto 0) => in9(4 downto 1),
      S(3 downto 2) => \writer_address__0\(4 downto 3),
      S(1) => \i__carry_i_1__0_n_0\,
      S(0) => \writer_address__0\(1)
    );
\plusOp_inferred__4/i__carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \plusOp_inferred__4/i__carry_n_0\,
      CO(3) => \plusOp_inferred__4/i__carry__0_n_0\,
      CO(2) => \plusOp_inferred__4/i__carry__0_n_1\,
      CO(1) => \plusOp_inferred__4/i__carry__0_n_2\,
      CO(0) => \plusOp_inferred__4/i__carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in9(8 downto 5),
      S(3 downto 0) => \writer_address__0\(8 downto 5)
    );
\plusOp_inferred__4/i__carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \plusOp_inferred__4/i__carry__0_n_0\,
      CO(3) => \plusOp_inferred__4/i__carry__1_n_0\,
      CO(2) => \plusOp_inferred__4/i__carry__1_n_1\,
      CO(1) => \plusOp_inferred__4/i__carry__1_n_2\,
      CO(0) => \plusOp_inferred__4/i__carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in9(12 downto 9),
      S(3 downto 0) => \writer_address__0\(12 downto 9)
    );
\plusOp_inferred__4/i__carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \plusOp_inferred__4/i__carry__1_n_0\,
      CO(3) => \plusOp_inferred__4/i__carry__2_n_0\,
      CO(2) => \plusOp_inferred__4/i__carry__2_n_1\,
      CO(1) => \plusOp_inferred__4/i__carry__2_n_2\,
      CO(0) => \plusOp_inferred__4/i__carry__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in9(16 downto 13),
      S(3 downto 0) => \writer_address__0\(16 downto 13)
    );
\plusOp_inferred__4/i__carry__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \plusOp_inferred__4/i__carry__2_n_0\,
      CO(3) => \plusOp_inferred__4/i__carry__3_n_0\,
      CO(2) => \plusOp_inferred__4/i__carry__3_n_1\,
      CO(1) => \plusOp_inferred__4/i__carry__3_n_2\,
      CO(0) => \plusOp_inferred__4/i__carry__3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in9(20 downto 17),
      S(3 downto 0) => \writer_address__0\(20 downto 17)
    );
\plusOp_inferred__4/i__carry__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \plusOp_inferred__4/i__carry__3_n_0\,
      CO(3) => \plusOp_inferred__4/i__carry__4_n_0\,
      CO(2) => \plusOp_inferred__4/i__carry__4_n_1\,
      CO(1) => \plusOp_inferred__4/i__carry__4_n_2\,
      CO(0) => \plusOp_inferred__4/i__carry__4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in9(24 downto 21),
      S(3 downto 0) => \writer_address__0\(24 downto 21)
    );
\plusOp_inferred__4/i__carry__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \plusOp_inferred__4/i__carry__4_n_0\,
      CO(3) => \plusOp_inferred__4/i__carry__5_n_0\,
      CO(2) => \plusOp_inferred__4/i__carry__5_n_1\,
      CO(1) => \plusOp_inferred__4/i__carry__5_n_2\,
      CO(0) => \plusOp_inferred__4/i__carry__5_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in9(28 downto 25),
      S(3 downto 0) => \writer_address__0\(28 downto 25)
    );
\plusOp_inferred__4/i__carry__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \plusOp_inferred__4/i__carry__5_n_0\,
      CO(3 downto 2) => \NLW_plusOp_inferred__4/i__carry__6_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \plusOp_inferred__4/i__carry__6_n_2\,
      CO(0) => \plusOp_inferred__4/i__carry__6_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_plusOp_inferred__4/i__carry__6_O_UNCONNECTED\(3),
      O(2 downto 0) => in9(31 downto 29),
      S(3) => '0',
      S(2 downto 0) => \writer_address__0\(31 downto 29)
    );
sck_o_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0090"
    )
        port map (
      I0 => \fsm_State_reg_n_0_[0]\,
      I1 => \fsm_State_reg_n_0_[1]\,
      I2 => clk_en,
      I3 => \fsm_State_reg_n_0_[2]\,
      I4 => \^sck_o\,
      O => sck_o_i_1_n_0
    );
sck_o_reg: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => '1',
      D => sck_o_i_1_n_0,
      Q => \^sck_o\,
      R => '0'
    );
\sync_reg_control[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => \sync_reg_control_reg_n_0_[0]\,
      I1 => ctl_reg_control_event,
      I2 => \ctl_reg_control_reg_n_0_[0]\,
      I3 => \fsm_start_ack__0\,
      O => \sync_reg_control[0]_i_1_n_0\
    );
\sync_reg_control_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ctl_clk_i,
      CE => '1',
      D => \sync_reg_control[0]_i_1_n_0\,
      Q => \sync_reg_control_reg_n_0_[0]\,
      R => '0'
    );
\writer_address[31]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2AAA"
    )
        port map (
      I0 => ipc_reset,
      I1 => \writer_state__0\(0),
      I2 => \writer_state__0\(1),
      I3 => clk_en,
      O => \writer_address[31]_i_1_n_0\
    );
\writer_address[31]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EAAA"
    )
        port map (
      I0 => ipc_reset,
      I1 => \writer_state__0\(0),
      I2 => \writer_state__0\(1),
      I3 => clk_en,
      O => \writer_address[31]_i_2_n_0\
    );
\writer_address_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(10),
      Q => \writer_address__0\(10),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(11),
      Q => \writer_address__0\(11),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(12),
      Q => \writer_address__0\(12),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(13),
      Q => \writer_address__0\(13),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(14),
      Q => \writer_address__0\(14),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(15),
      Q => \writer_address__0\(15),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(16),
      Q => \writer_address__0\(16),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(17),
      Q => \writer_address__0\(17),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(18),
      Q => \writer_address__0\(18),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(19),
      Q => \writer_address__0\(19),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(1),
      Q => \writer_address__0\(1),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(20),
      Q => \writer_address__0\(20),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(21),
      Q => \writer_address__0\(21),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(22),
      Q => \writer_address__0\(22),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(23),
      Q => \writer_address__0\(23),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(24),
      Q => \writer_address__0\(24),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(25),
      Q => \writer_address__0\(25),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(26),
      Q => \writer_address__0\(26),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(27),
      Q => \writer_address__0\(27),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(28),
      Q => \writer_address__0\(28),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(29),
      Q => \writer_address__0\(29),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(2),
      Q => \writer_address__0\(2),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(30),
      Q => \writer_address__0\(30),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(31),
      Q => \writer_address__0\(31),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(3),
      Q => \writer_address__0\(3),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(4),
      Q => \writer_address__0\(4),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(5),
      Q => \writer_address__0\(5),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(6),
      Q => \writer_address__0\(6),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(7),
      Q => \writer_address__0\(7),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(8),
      Q => \writer_address__0\(8),
      R => \writer_address[31]_i_1_n_0\
    );
\writer_address_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => ctl_clk_i,
      CE => \writer_address[31]_i_2_n_0\,
      D => in9(9),
      Q => \writer_address__0\(9),
      R => \writer_address[31]_i_1_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blok_controller_0_0 is
  port (
    cfgmem_clk_o : out STD_LOGIC;
    cfgmem_rst_o : out STD_LOGIC;
    cfgmem_data_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfgmem_data_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
    cfgmem_ena_o : out STD_LOGIC;
    cfgmem_wea_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
    cfgmem_addr_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
    datmem_clk_o : out STD_LOGIC;
    datmem_rst_o : out STD_LOGIC;
    datmem_data_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
    datmem_data_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
    datmem_ena_o : out STD_LOGIC;
    datmem_wea_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
    datmem_addr_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ctl_clk_i : in STD_LOGIC;
    ctl_rst_i : in STD_LOGIC;
    ctl_data_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
    ctl_data_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ctl_ena_i : in STD_LOGIC;
    ctl_wea_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
    ctl_addr_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
    mosi_o : out STD_LOGIC;
    miso_i : in STD_LOGIC;
    sck_o : out STD_LOGIC;
    cs_o : out STD_LOGIC;
    leds_o : out STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of blok_controller_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of blok_controller_0_0 : entity is "blok_controller_0_0,controller,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of blok_controller_0_0 : entity is "yes";
  attribute IP_DEFINITION_SOURCE : string;
  attribute IP_DEFINITION_SOURCE of blok_controller_0_0 : entity is "module_ref";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of blok_controller_0_0 : entity is "controller,Vivado 2020.2";
end blok_controller_0_0;

architecture STRUCTURE of blok_controller_0_0 is
  signal \<const0>\ : STD_LOGIC;
  signal \^cfgmem_addr_o\ : STD_LOGIC_VECTOR ( 31 downto 1 );
  signal \^ctl_clk_i\ : STD_LOGIC;
  signal \^datmem_addr_o\ : STD_LOGIC_VECTOR ( 31 downto 1 );
  signal \^datmem_wea_o\ : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of ctl_clk_i : signal is "xilinx.com:interface:bram:1.0 ctl_BRAM CLK";
  attribute X_INTERFACE_INFO of ctl_ena_i : signal is "xilinx.com:interface:bram:1.0 ctl_BRAM EN";
  attribute X_INTERFACE_INFO of ctl_rst_i : signal is "xilinx.com:interface:bram:1.0 ctl_BRAM RST";
  attribute X_INTERFACE_INFO of ctl_addr_i : signal is "xilinx.com:interface:bram:1.0 ctl_BRAM ADDR";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of ctl_addr_i : signal is "XIL_INTERFACENAME ctl_BRAM, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute X_INTERFACE_INFO of ctl_data_i : signal is "xilinx.com:interface:bram:1.0 ctl_BRAM DIN";
  attribute X_INTERFACE_INFO of ctl_data_o : signal is "xilinx.com:interface:bram:1.0 ctl_BRAM DOUT";
  attribute X_INTERFACE_INFO of ctl_wea_i : signal is "xilinx.com:interface:bram:1.0 ctl_BRAM WE";
begin
  \^ctl_clk_i\ <= ctl_clk_i;
  cfgmem_addr_o(31 downto 1) <= \^cfgmem_addr_o\(31 downto 1);
  cfgmem_addr_o(0) <= \<const0>\;
  cfgmem_clk_o <= \^ctl_clk_i\;
  cfgmem_data_o(31) <= \<const0>\;
  cfgmem_data_o(30) <= \<const0>\;
  cfgmem_data_o(29) <= \<const0>\;
  cfgmem_data_o(28) <= \<const0>\;
  cfgmem_data_o(27) <= \<const0>\;
  cfgmem_data_o(26) <= \<const0>\;
  cfgmem_data_o(25) <= \<const0>\;
  cfgmem_data_o(24) <= \<const0>\;
  cfgmem_data_o(23) <= \<const0>\;
  cfgmem_data_o(22) <= \<const0>\;
  cfgmem_data_o(21) <= \<const0>\;
  cfgmem_data_o(20) <= \<const0>\;
  cfgmem_data_o(19) <= \<const0>\;
  cfgmem_data_o(18) <= \<const0>\;
  cfgmem_data_o(17) <= \<const0>\;
  cfgmem_data_o(16) <= \<const0>\;
  cfgmem_data_o(15) <= \<const0>\;
  cfgmem_data_o(14) <= \<const0>\;
  cfgmem_data_o(13) <= \<const0>\;
  cfgmem_data_o(12) <= \<const0>\;
  cfgmem_data_o(11) <= \<const0>\;
  cfgmem_data_o(10) <= \<const0>\;
  cfgmem_data_o(9) <= \<const0>\;
  cfgmem_data_o(8) <= \<const0>\;
  cfgmem_data_o(7) <= \<const0>\;
  cfgmem_data_o(6) <= \<const0>\;
  cfgmem_data_o(5) <= \<const0>\;
  cfgmem_data_o(4) <= \<const0>\;
  cfgmem_data_o(3) <= \<const0>\;
  cfgmem_data_o(2) <= \<const0>\;
  cfgmem_data_o(1) <= \<const0>\;
  cfgmem_data_o(0) <= \<const0>\;
  cfgmem_rst_o <= \<const0>\;
  cfgmem_wea_o(3) <= \<const0>\;
  cfgmem_wea_o(2) <= \<const0>\;
  cfgmem_wea_o(1) <= \<const0>\;
  cfgmem_wea_o(0) <= \<const0>\;
  ctl_data_o(31) <= \<const0>\;
  ctl_data_o(30) <= \<const0>\;
  ctl_data_o(29) <= \<const0>\;
  ctl_data_o(28) <= \<const0>\;
  ctl_data_o(27) <= \<const0>\;
  ctl_data_o(26) <= \<const0>\;
  ctl_data_o(25) <= \<const0>\;
  ctl_data_o(24) <= \<const0>\;
  ctl_data_o(23) <= \<const0>\;
  ctl_data_o(22) <= \<const0>\;
  ctl_data_o(21) <= \<const0>\;
  ctl_data_o(20) <= \<const0>\;
  ctl_data_o(19) <= \<const0>\;
  ctl_data_o(18) <= \<const0>\;
  ctl_data_o(17) <= \<const0>\;
  ctl_data_o(16) <= \<const0>\;
  ctl_data_o(15) <= \<const0>\;
  ctl_data_o(14) <= \<const0>\;
  ctl_data_o(13) <= \<const0>\;
  ctl_data_o(12) <= \<const0>\;
  ctl_data_o(11) <= \<const0>\;
  ctl_data_o(10) <= \<const0>\;
  ctl_data_o(9) <= \<const0>\;
  ctl_data_o(8) <= \<const0>\;
  ctl_data_o(7) <= \<const0>\;
  ctl_data_o(6) <= \<const0>\;
  ctl_data_o(5) <= \<const0>\;
  ctl_data_o(4) <= \<const0>\;
  ctl_data_o(3) <= \<const0>\;
  ctl_data_o(2) <= \<const0>\;
  ctl_data_o(1) <= \<const0>\;
  ctl_data_o(0) <= \<const0>\;
  datmem_addr_o(31 downto 1) <= \^datmem_addr_o\(31 downto 1);
  datmem_addr_o(0) <= \<const0>\;
  datmem_clk_o <= \^ctl_clk_i\;
  datmem_ena_o <= \^datmem_wea_o\(3);
  datmem_rst_o <= \<const0>\;
  datmem_wea_o(3) <= \^datmem_wea_o\(3);
  datmem_wea_o(2) <= \^datmem_wea_o\(3);
  datmem_wea_o(1) <= \^datmem_wea_o\(3);
  datmem_wea_o(0) <= \^datmem_wea_o\(3);
  leds_o(7) <= \<const0>\;
  leds_o(6) <= \<const0>\;
  leds_o(5) <= \<const0>\;
  leds_o(4) <= \<const0>\;
  leds_o(3) <= \<const0>\;
  leds_o(2) <= \<const0>\;
  leds_o(1) <= \<const0>\;
  leds_o(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
inst: entity work.blok_controller_0_0_controller
     port map (
      cfgmem_addr_o(30 downto 0) => \^cfgmem_addr_o\(31 downto 1),
      cfgmem_data_i(31 downto 0) => cfgmem_data_i(31 downto 0),
      cfgmem_ena_o => cfgmem_ena_o,
      cs_o => cs_o,
      ctl_addr_i(31 downto 0) => ctl_addr_i(31 downto 0),
      ctl_clk_i => \^ctl_clk_i\,
      ctl_data_i(31 downto 0) => ctl_data_i(31 downto 0),
      ctl_ena_i => ctl_ena_i,
      ctl_rst_i => ctl_rst_i,
      ctl_wea_i(3 downto 0) => ctl_wea_i(3 downto 0),
      datmem_addr_o(30 downto 0) => \^datmem_addr_o\(31 downto 1),
      datmem_data_o(31 downto 0) => datmem_data_o(31 downto 0),
      datmem_wea_o(0) => \^datmem_wea_o\(3),
      miso_i => miso_i,
      mosi_o => mosi_o,
      sck_o => sck_o
    );
end STRUCTURE;
