GPS0.1 Project Status (04/05/2010 - 21:09:05)
Project File: | GPS0.1.ise | Implementation State: | Placed and Routed (Stopped)
Module Name: | GPS_main | Errors: |
Target Device: | xc3s200-5vq100 | Warnings: |
Product Version: | ISE 11.1 | Routing Results: |
Design Goal: | Balanced | Timing Constraints: |
Design Strategy: | Xilinx Default (unlocked) | Final Timing Score: |

Device Utilization Summary | [-]
Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Flip Flops | 202 | 1,536 | 13% |
Number of 4 input LUTs | 69 | 1,536 | 4% |
Number of occupied Slices | 109 | 768 | 14% |
Number of Slices containing only related logic | 109 | 109 | 100% |
Number of Slices containing unrelated logic | 0 | 109 | 0% |
Total Number of 4 input LUTs | 129 | 1,536 | 8% |
Number used as logic | 68 |  |  |
Number used as a route-thru | 60 |  |  |
Number used as Shift registers | 1 |  |  |
Number of bonded IOBs | 123 | 124 | 99% |
Number of BUFGMUXs | 2 | 8 | 25% |
Number of RPM macros | 1 |  |  |
Average Fanout of Non-Clock Nets | 2.10 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report |  |  |  |  |
Translation Report | Current | po 12. X 11:04:10 2009 |  |  |
Map Report | Current | po 12. X 11:04:17 2009 |  |  |
Place and Route Report | Current | po 12. X 11:04:34 2009 |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Out of Date | po 12. X 10:46:25 2009 |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated

Date Generated: 04/05/2010 - 21:09:07