// *****************************************************************************
//                         Cadence C-to-Silicon Compiler
//          Version 12.20-s303  (32 bit), build 46678 Wed, 17 Jul 2013
// 
// Copyright notice: Copyright 2006-2013 Cadence Design Systems, Inc. All
// rights reserved worldwide.
// 
// Patent notice: Protected by U.S. Patents 7472361, 7587687, 7673259,
// 7711536; other U.S. patents pending.
//*****************************************************************************
// 
// **********************************************************
// SystemC structure port(s) --> RTL flattened representation
// **********************************************************
// coef0_sc_fl.man maps to coef0_sc_fl[22:0]
// coef0_sc_fl.exp maps to coef0_sc_fl[30:23]
// coef0_sc_fl.sign maps to coef0_sc_fl[31:31]
// coef1_sc_fl.man maps to coef1_sc_fl[22:0]
// coef1_sc_fl.exp maps to coef1_sc_fl[30:23]
// coef1_sc_fl.sign maps to coef1_sc_fl[31:31]
// Uz_sc_fl.man maps to Uz_sc_fl[22:0]
// Uz_sc_fl.exp maps to Uz_sc_fl[30:23]
// Uz_sc_fl.sign maps to Uz_sc_fl[31:31]
// outp.man maps to outp[22:0]
// outp.exp maps to outp[30:23]
// outp.sign maps to outp[31:31]

module BlackBox_rtl(coef0_sc_fl, coef1_sc_fl, Uz_sc_fl, clk, rst, en, outp);
  input [31:0] coef0_sc_fl;
  input [31:0] coef1_sc_fl;
  input [31:0] Uz_sc_fl;
  input clk;
  input rst;
  input en;
  output reg [31:0] outp;
  wire [22:0] operatortimes__operatortimes__man_out;
  wire [7:0] operatortimes__operatortimes__exp_out;
  wire operatortimes__operatortimes__sign_out;
  wire [22:0] operatorplus__ln17_operatorplus__man_out;
  wire [7:0] operatorplus__ln17_operatorplus__exp_out;
  wire operatorplus__ln17_operatorplus__sign_out;
  reg [2:0] state_BlackBox_expFUNC;
  reg [2:0] state_BlackBox_expFUNC_next;
  reg [31:0] read_BlackBox_coef1_sc_fl_ln73_q;
  reg read_BlackBox_en_ln79_q;
  reg mux_value_Q_sign_ln52_q;
  reg [7:0] operatortimes__ln17_operatortimes__exp_out_q;
  reg [22:0] operatortimes__ln17_operatortimes__man_out_q;
  reg operatortimes__ln17_operatortimes__sign_out_q;
  reg [8:0] operatorplus__ln17_operatorplus__man_out_q;
  reg [22:0] mux_value_D_man_ln52_q;
  reg mux_value_Q_sign_ln52_z;
  reg [31:0] outp_d;
  reg [22:0] operatortimes__rhs_man_in;
  reg operatortimes__rhs_sign_in;
  reg [7:0] operatortimes__this__exp_in;
  reg [22:0] operatortimes__this__man_in;
  reg operatortimes__this__sign_in;
  reg [7:0] operatortimes__rhs_exp_in;
  reg [31:0] operatorplus__ln17_operatorplus__man_out_d;

  // pragma sync_set_reset_local BlackBox_expFUNC_seq_block rst
  always @(posedge clk) // BlackBox_expFUNC_sequential
    begin : BlackBox_expFUNC_seq_block
      if (rst) // Initialize state and outputs
      state_BlackBox_expFUNC <= 3'h1;
      else // Update Q values
      state_BlackBox_expFUNC <= state_BlackBox_expFUNC_next;
    end
  always @(posedge clk) // BlackBox_expFUNC_0_sequential
    begin
      read_BlackBox_coef1_sc_fl_ln73_q <= coef1_sc_fl;
      read_BlackBox_en_ln79_q <= en;
      mux_value_Q_sign_ln52_q <= mux_value_Q_sign_ln52_z;
      outp <= outp_d;
      operatortimes__ln17_operatortimes__exp_out_q <= 
      operatortimes__operatortimes__exp_out;
      operatortimes__ln17_operatortimes__man_out_q <= 
      operatortimes__operatortimes__man_out;
      operatortimes__ln17_operatortimes__sign_out_q <= 
      operatortimes__operatortimes__sign_out;
      operatorplus__ln17_operatorplus__man_out_q <= 
      operatorplus__ln17_operatorplus__man_out_d[8:0];
      mux_value_D_man_ln52_q <= operatorplus__ln17_operatorplus__man_out_d[31:9];
    end
  operatortimes_ operatortimes_(.this__man_in(operatortimes__this__man_in), .this__exp_in(
                 operatortimes__this__exp_in), .this__sign_in(
                 operatortimes__this__sign_in), .rhs_man_in(
                 operatortimes__rhs_man_in), .rhs_exp_in(
                 operatortimes__rhs_exp_in), .rhs_sign_in(
                 operatortimes__rhs_sign_in), .operatortimes__man_out(
                 operatortimes__operatortimes__man_out), .operatortimes__exp_out(
                 operatortimes__operatortimes__exp_out), .operatortimes__sign_out(
                 operatortimes__operatortimes__sign_out));
  operatorplus_ operatorplus_(.this__man_in(
                operatortimes__ln17_operatortimes__man_out_q), .this__exp_in(
                operatortimes__ln17_operatortimes__exp_out_q), .this__sign_in(
                operatortimes__ln17_operatortimes__sign_out_q), .rhs_man_in(
                operatortimes__operatortimes__man_out), .rhs_exp_in(
                operatortimes__operatortimes__exp_out), .rhs_sign_in(
                operatortimes__operatortimes__sign_out), .operatorplus__man_out(
                operatorplus__ln17_operatorplus__man_out), .operatorplus__exp_out(
                operatorplus__ln17_operatorplus__exp_out), .operatorplus__sign_out(
                operatorplus__ln17_operatorplus__sign_out));
  always @(*) begin : BlackBox_expFUNC_combinational
      reg ctrlAnd_0_ln14_z;
      reg [22:0] mux_value_D_man_ln14_z;
      reg mux_value_D_sign_ln14_z;
      reg [7:0] mux_value_D_exp_ln14_z;
      reg operatortimes__ln17_0_en;
      reg ctrlAnd_1_ln14_z;
      reg [22:0] mux_value_D_man_ln52_z;
      reg mux_value_D_sign_ln52_z;
      reg [7:0] mux_value_D_exp_ln52_z;
      reg ctrlOr_ln14_z;
      reg write_BlackBox_outp_ln84_en;
      reg ctrlOr_ln52_z;
      reg operatortimes__ln17_en;

      state_BlackBox_expFUNC_next = 3'h0;
      ctrlAnd_0_ln14_z = read_BlackBox_en_ln79_q & state_BlackBox_expFUNC[1];
      if (state_BlackBox_expFUNC[2]) 
        mux_value_D_man_ln14_z = {mux_value_D_man_ln52_q[13:0], 
        operatorplus__ln17_operatorplus__man_out_q};
      else 
        mux_value_D_man_ln14_z = mux_value_D_man_ln52_q;
      if (state_BlackBox_expFUNC[2]) 
        mux_value_D_sign_ln14_z = mux_value_D_man_ln52_q[22];
      else 
        mux_value_D_sign_ln14_z = operatorplus__ln17_operatorplus__man_out_q[0];
      if (state_BlackBox_expFUNC[2]) 
        mux_value_D_exp_ln14_z = mux_value_D_man_ln52_q[21:14];
      else 
        mux_value_D_exp_ln14_z = operatorplus__ln17_operatorplus__man_out_q[8:1];
      operatortimes__ln17_0_en = read_BlackBox_en_ln79_q & ctrlAnd_0_ln14_z;
      ctrlAnd_1_ln14_z = !read_BlackBox_en_ln79_q & state_BlackBox_expFUNC[1];
      if (state_BlackBox_expFUNC[0]) 
        mux_value_D_man_ln52_z = 23'h0;
      else 
        mux_value_D_man_ln52_z = mux_value_D_man_ln14_z;
      if (state_BlackBox_expFUNC[0]) 
        mux_value_Q_sign_ln52_z = 1'b0;
      else 
        mux_value_Q_sign_ln52_z = mux_value_D_sign_ln14_z;
      if (state_BlackBox_expFUNC[0]) 
        mux_value_D_sign_ln52_z = 1'b0;
      else 
        mux_value_D_sign_ln52_z = mux_value_D_sign_ln14_z;
      if (state_BlackBox_expFUNC[0]) 
        mux_value_D_exp_ln52_z = 8'h0;
      else 
        mux_value_D_exp_ln52_z = mux_value_D_exp_ln14_z;
      ctrlOr_ln14_z = ctrlAnd_1_ln14_z | state_BlackBox_expFUNC[2];
      write_BlackBox_outp_ln84_en = !rst & ctrlOr_ln14_z;
      ctrlOr_ln52_z = ctrlOr_ln14_z | state_BlackBox_expFUNC[0];
      operatortimes__ln17_en = en & ctrlOr_ln52_z;
      if (write_BlackBox_outp_ln84_en) 
        outp_d = {mux_value_D_sign_ln14_z, mux_value_D_exp_ln14_z, 
        mux_value_D_man_ln14_z};
      else 
        outp_d = outp;
      case (1'b1)// pragma parallel_case
        operatortimes__ln17_en: operatortimes__rhs_man_in = Uz_sc_fl[22:0];
        operatortimes__ln17_0_en: operatortimes__rhs_man_in = 
          mux_value_D_man_ln52_q;
        default: operatortimes__rhs_man_in = 23'hX;
      endcase
      case (1'b1)// pragma parallel_case
        operatortimes__ln17_en: operatortimes__rhs_sign_in = Uz_sc_fl[31];
        operatortimes__ln17_0_en: operatortimes__rhs_sign_in = 
          mux_value_Q_sign_ln52_q;
        default: operatortimes__rhs_sign_in = 1'bX;
      endcase
      case (1'b1)// pragma parallel_case
        operatortimes__ln17_en: operatortimes__this__exp_in = coef0_sc_fl[30:23];
        operatortimes__ln17_0_en: operatortimes__this__exp_in = 
          read_BlackBox_coef1_sc_fl_ln73_q[30:23];
        default: operatortimes__this__exp_in = 8'hX;
      endcase
      case (1'b1)// pragma parallel_case
        operatortimes__ln17_en: operatortimes__this__man_in = coef0_sc_fl[22:0];
        operatortimes__ln17_0_en: operatortimes__this__man_in = 
          read_BlackBox_coef1_sc_fl_ln73_q[22:0];
        default: operatortimes__this__man_in = 23'hX;
      endcase
      case (1'b1)// pragma parallel_case
        operatortimes__ln17_en: operatortimes__this__sign_in = coef0_sc_fl[31];
        operatortimes__ln17_0_en: operatortimes__this__sign_in = 
          read_BlackBox_coef1_sc_fl_ln73_q[31];
        default: operatortimes__this__sign_in = 1'bX;
      endcase
      case (1'b1)// pragma parallel_case
        operatortimes__ln17_en: operatortimes__rhs_exp_in = Uz_sc_fl[30:23];
        operatortimes__ln17_0_en: operatortimes__rhs_exp_in = 
          operatorplus__ln17_operatorplus__man_out_q[8:1];
        default: operatortimes__rhs_exp_in = 8'hX;
      endcase
      case (1'b1)// pragma parallel_case
        ctrlOr_ln52_z: operatorplus__ln17_operatorplus__man_out_d = {
          mux_value_D_man_ln52_z, mux_value_D_exp_ln52_z, 
          mux_value_D_sign_ln52_z};
        ctrlAnd_0_ln14_z: operatorplus__ln17_operatorplus__man_out_d = {
          operatorplus__ln17_operatorplus__sign_out, 
          operatorplus__ln17_operatorplus__exp_out, 
          operatorplus__ln17_operatorplus__man_out};
        default: operatorplus__ln17_operatorplus__man_out_d = 32'hX;
      endcase
      case (1'b1)// pragma parallel_case
        state_BlackBox_expFUNC[0]: // Wait_ln49
          state_BlackBox_expFUNC_next[1] = 1'b1;
        state_BlackBox_expFUNC[1]: // Wait_0_ln18
          begin
            case (1'b1)// pragma parallel_case
              ctrlAnd_0_ln14_z: state_BlackBox_expFUNC_next[2] = 1'b1;
              ctrlOr_ln52_z: state_BlackBox_expFUNC_next[1] = 1'b1;
              default: state_BlackBox_expFUNC_next = 3'hX;
            endcase
          end
        state_BlackBox_expFUNC[2]: // Wait_1_ln18
          state_BlackBox_expFUNC_next[1] = 1'b1;
        default: // Don't care
          state_BlackBox_expFUNC_next = 3'hX;
      endcase
    end
endmodule


module operatortimes_(this__man_in, this__exp_in, this__sign_in, rhs_man_in, 
rhs_exp_in, rhs_sign_in, operatortimes__man_out, operatortimes__exp_out, 
operatortimes__sign_out);
  input [22:0] this__man_in;
  input [7:0] this__exp_in;
  input this__sign_in;
  input [22:0] rhs_man_in;
  input [7:0] rhs_exp_in;
  input rhs_sign_in;
  output reg [22:0] operatortimes__man_out;
  output reg [7:0] operatortimes__exp_out;
  output reg operatortimes__sign_out;
  wire [22:0] multiply_exceptions_ln536_multiply_exceptions_man_out;
  wire [7:0] multiply_exceptions_ln536_multiply_exceptions_exp_out;
  wire multiply_exceptions_ln536_multiply_exceptions_sign_out;

  multiply_exceptions multiply_exceptions_ln536(.mul1_man_in(this__man_in), .mul1_exp_in(
                      this__exp_in), .mul1_sign_in(this__sign_in), .mul2_man_in(
                      rhs_man_in), .mul2_exp_in(rhs_exp_in), .mul2_sign_in(
                      rhs_sign_in), .multiply_exceptions_man_out(
                      multiply_exceptions_ln536_multiply_exceptions_man_out), .multiply_exceptions_exp_out(
                      multiply_exceptions_ln536_multiply_exceptions_exp_out), .multiply_exceptions_sign_out(
                      multiply_exceptions_ln536_multiply_exceptions_sign_out));
  always @(*) begin : operatortimes__combinational
      operatortimes__man_out = 
      multiply_exceptions_ln536_multiply_exceptions_man_out;
      operatortimes__sign_out = 
      multiply_exceptions_ln536_multiply_exceptions_sign_out;
      operatortimes__exp_out = 
      multiply_exceptions_ln536_multiply_exceptions_exp_out;
    end
endmodule


module multiply_exceptions(mul1_man_in, mul1_exp_in, mul1_sign_in, mul2_man_in, 
mul2_exp_in, mul2_sign_in, multiply_exceptions_man_out, 
multiply_exceptions_exp_out, multiply_exceptions_sign_out);
  input [22:0] mul1_man_in;
  input [7:0] mul1_exp_in;
  input mul1_sign_in;
  input [22:0] mul2_man_in;
  input [7:0] mul2_exp_in;
  input mul2_sign_in;
  output reg [22:0] multiply_exceptions_man_out;
  output reg [7:0] multiply_exceptions_exp_out;
  output reg multiply_exceptions_sign_out;
  wire is_NaN_ln87_z;
  wire is_NaN_ln87_0_z;
  wire is_zero_or_denormal_ln101_z;
  wire is_zero_or_denormal_ln101_0_z;
  wire is_inf_ln109_z;
  wire is_inf_ln109_0_z;
  wire is_inf_ln123_z;
  wire is_inf_ln123_0_z;
  wire is_inf_ln130_z;
  wire is_inf_ln130_0_z;
  wire [22:0] multiply_ln144_multiply_man_out;
  wire [7:0] multiply_ln144_multiply_exp_out;
  wire multiply_ln144_multiply_sign_out;

  is_zero_or_denormal is_zero_or_denormal_ln101(.fp_exp_in(mul1_exp_in), .is_zero_or_denormal_out(
                      is_zero_or_denormal_ln101_z));
  is_inf is_inf_ln109(.fp_man_in(mul1_man_in), .fp_exp_in(mul1_exp_in), .is_inf_out(
         is_inf_ln109_z));
  is_inf is_inf_ln123(.fp_man_in(mul1_man_in), .fp_exp_in(mul1_exp_in), .is_inf_out(
         is_inf_ln123_z));
  is_inf is_inf_ln130(.fp_man_in(mul1_man_in), .fp_exp_in(mul1_exp_in), .is_inf_out(
         is_inf_ln130_z));
  is_NaN is_NaN_ln87(.fp_man_in(mul1_man_in), .fp_exp_in(mul1_exp_in), .is_NaN_out(
         is_NaN_ln87_z));
  is_NaN is_NaN_ln87_0(.fp_man_in(mul2_man_in), .fp_exp_in(mul2_exp_in), .is_NaN_out(
         is_NaN_ln87_0_z));
  is_inf is_inf_ln109_0(.fp_man_in(mul2_man_in), .fp_exp_in(mul2_exp_in), .is_inf_out(
         is_inf_ln109_0_z));
  is_inf is_inf_ln123_0(.fp_man_in(mul2_man_in), .fp_exp_in(mul2_exp_in), .is_inf_out(
         is_inf_ln123_0_z));
  is_inf is_inf_ln130_0(.fp_man_in(mul2_man_in), .fp_exp_in(mul2_exp_in), .is_inf_out(
         is_inf_ln130_0_z));
  is_zero_or_denormal is_zero_or_denormal_ln101_0(.fp_exp_in(mul2_exp_in), .is_zero_or_denormal_out(
                      is_zero_or_denormal_ln101_0_z));
  multiply multiply_ln144(.mul1_man_in(mul1_man_in), .mul1_exp_in(mul1_exp_in), 
           .mul1_sign_in(mul1_sign_in), .mul2_man_in(mul2_man_in), .mul2_exp_in(
           mul2_exp_in), .mul2_sign_in(mul2_sign_in), .multiply_man_out(
           multiply_ln144_multiply_man_out), .multiply_exp_out(
           multiply_ln144_multiply_exp_out), .multiply_sign_out(
           multiply_ln144_multiply_sign_out));
  always @(*) begin : multiply_exceptions_combinational
      reg xor_ln83_z;
      reg ternaryMux_ln101_0_z;
      reg ternaryMux_ln109_0_z;
      reg ternaryMux_ln123_0_z;
      reg ternaryMux_ln130_0_z;
      reg ternaryMux_ln87_0_z;
      reg [2:0] case_mux_res_sign_ln101_z;
      reg and_case_mux_res_man_ln101_0_z;
      reg and_case_mux_res_sign_ln101_1_z;
      reg or_if_ln87_0_Z_0_z;
      reg or_if_ln87_0_Z_0_0_z;
      reg and_case_mux_res_exp_ln101_z;
      reg mux_res_sign_ln87_z;
      reg [22:0] mux_res_man_ln87_z;
      reg [7:0] mux_res_exp_ln87_z;

      xor_ln83_z = mul2_sign_in ^ mul1_sign_in;
      ternaryMux_ln101_0_z = is_zero_or_denormal_ln101_z | 
      is_zero_or_denormal_ln101_0_z;
      ternaryMux_ln109_0_z = is_inf_ln109_z | is_inf_ln109_0_z;
      ternaryMux_ln123_0_z = is_inf_ln123_z | is_inf_ln123_0_z;
      ternaryMux_ln130_0_z = is_inf_ln130_z & is_inf_ln130_0_z;
      ternaryMux_ln87_0_z = is_NaN_ln87_z | is_NaN_ln87_0_z;
      case (1'b1)
        ternaryMux_ln101_0_z: case_mux_res_sign_ln101_z = 3'h1;
        ternaryMux_ln123_0_z: case_mux_res_sign_ln101_z = 3'h2;
        default: case_mux_res_sign_ln101_z = 3'h4;
      endcase
      and_case_mux_res_man_ln101_0_z = !ternaryMux_ln87_0_z & 
      case_mux_res_sign_ln101_z[1];
      and_case_mux_res_sign_ln101_1_z = !ternaryMux_ln87_0_z & 
      case_mux_res_sign_ln101_z[2];
      or_if_ln87_0_Z_0_z = |case_mux_res_sign_ln101_z[1:0] | ternaryMux_ln87_0_z;
      or_if_ln87_0_Z_0_0_z = case_mux_res_sign_ln101_z[1] | ternaryMux_ln87_0_z;
      and_case_mux_res_exp_ln101_z = !ternaryMux_ln87_0_z & 
      case_mux_res_sign_ln101_z[0];
      case (1'b1)// pragma parallel_case
        or_if_ln87_0_Z_0_z: mux_res_sign_ln87_z = xor_ln83_z;
        and_case_mux_res_sign_ln101_1_z: mux_res_sign_ln87_z = 
          multiply_ln144_multiply_sign_out;
        default: mux_res_sign_ln87_z = 1'bX;
      endcase
      case (1'b1)// pragma parallel_case
        ternaryMux_ln87_0_z: mux_res_man_ln87_z = 23'h1;
        and_case_mux_res_exp_ln101_z: mux_res_man_ln87_z = {22'h0, 
          ternaryMux_ln109_0_z};
        and_case_mux_res_man_ln101_0_z: mux_res_man_ln87_z = {22'h0, 
          ternaryMux_ln130_0_z};
        and_case_mux_res_sign_ln101_1_z: mux_res_man_ln87_z = 
          multiply_ln144_multiply_man_out;
        default: mux_res_man_ln87_z = 23'hX;
      endcase
      case (1'b1)// pragma parallel_case
        or_if_ln87_0_Z_0_0_z: mux_res_exp_ln87_z = 8'hff;
        and_case_mux_res_exp_ln101_z: mux_res_exp_ln87_z = {8{
          ternaryMux_ln109_0_z}};
        and_case_mux_res_sign_ln101_1_z: mux_res_exp_ln87_z = 
          multiply_ln144_multiply_exp_out;
        default: mux_res_exp_ln87_z = 8'hX;
      endcase
      multiply_exceptions_sign_out = mux_res_sign_ln87_z;
      multiply_exceptions_man_out = mux_res_man_ln87_z;
      multiply_exceptions_exp_out = mux_res_exp_ln87_z;
    end
endmodule


module is_NaN(fp_man_in, fp_exp_in, is_NaN_out);
  input [22:0] fp_man_in;
  input [7:0] fp_exp_in;
  output reg is_NaN_out;

  always @(*) begin : is_NaN_combinational
      reg eq_ln50_z;
      reg ne_ln50_z;
      reg ternaryMux_ln50_0_z;

      eq_ln50_z = fp_exp_in == 8'hff;
      ne_ln50_z = fp_man_in == 23'h0;
      ternaryMux_ln50_0_z = eq_ln50_z & !ne_ln50_z;
      is_NaN_out = ternaryMux_ln50_0_z;
    end
endmodule


module is_zero_or_denormal(fp_exp_in, is_zero_or_denormal_out);
  input [7:0] fp_exp_in;
  output reg is_zero_or_denormal_out;

  always @(*) begin : is_zero_or_denormal_combinational
      reg eq_ln70_z;

      eq_ln70_z = fp_exp_in == 8'h0;
      is_zero_or_denormal_out = eq_ln70_z;
    end
endmodule


module is_inf(fp_man_in, fp_exp_in, is_inf_out);
  input [22:0] fp_man_in;
  input [7:0] fp_exp_in;
  output reg is_inf_out;

  always @(*) begin : is_inf_combinational
      reg eq_ln40_z;
      reg eq_ln40_0_z;
      reg ternaryMux_ln40_0_z;

      eq_ln40_z = fp_exp_in == 8'hff;
      eq_ln40_0_z = fp_man_in == 23'h0;
      ternaryMux_ln40_0_z = eq_ln40_z & eq_ln40_0_z;
      is_inf_out = ternaryMux_ln40_0_z;
    end
endmodule


module multiply(mul1_man_in, mul1_exp_in, mul1_sign_in, mul2_man_in, mul2_exp_in, 
mul2_sign_in, multiply_man_out, multiply_exp_out, multiply_sign_out);
  input [22:0] mul1_man_in;
  input [7:0] mul1_exp_in;
  input mul1_sign_in;
  input [22:0] mul2_man_in;
  input [7:0] mul2_exp_in;
  input mul2_sign_in;
  output reg [22:0] multiply_man_out;
  output reg [7:0] multiply_exp_out;
  output reg multiply_sign_out;

  always @(*) begin : multiply_combinational
      reg [8:0] add_ln238_z;
      reg [47:0] mul_ln239_z;
      reg xor_ln164_z;
      reg [9:0] sub_ln269_z;
      reg lt_ln251_z;
      reg [23:0] add_ln336_z;
      reg and_ln325_z;
      reg and_ln335_z;
      reg [21:0] add_ln326_z;
      reg [9:0] add_ln344_z;
      reg [9:0] add_ln328_z;
      reg [2:0] case_mux_man_ln321_z;
      reg [24:0] mux_man_ln335_z;
      reg [2:0] case_mux_exp_ln321_z;
      reg [9:0] mux_exp_ln321_z;
      reg ternaryMux_ln348_1_z;
      reg eq_ln348_z;
      reg ternaryMux_ln348_0_0_z;
      reg if_ln348_1_z;
      reg or_if_ln251_Z_0_z;
      reg [2:0] case_mux_exp_ln251_z;
      reg and_case_mux_man_ln321_1_z;
      reg and_if_ln338_0_0_0_z;
      reg and_if_ln338_1_0_z;
      reg and_case_mux_man_ln321_0_0_z;
      reg [7:0] mux_exp_ln251_z;
      reg [22:0] mux_man_ln251_z;

      add_ln238_z = {1'b0, mul1_exp_in} + mul2_exp_in;
      mul_ln239_z = {1'b1, mul1_man_in} * {1'b1, mul2_man_in};
      xor_ln164_z = mul2_sign_in ^ mul1_sign_in;
      sub_ln269_z = {1'b0, add_ln238_z} - 10'h7f;
      lt_ln251_z = add_ln238_z <= 9'h7e;
      add_ln336_z = {1'b0, mul_ln239_z[46:24]} + 24'h1;
      and_ln325_z = &{mul_ln239_z[23], mul_ln239_z[24]};
      and_ln335_z = &{mul_ln239_z[22], mul_ln239_z[23]};
      add_ln326_z = mul_ln239_z[46:25] + 22'h1;
      multiply_sign_out = xor_ln164_z;
      add_ln344_z = sub_ln269_z + 10'h1;
      add_ln328_z = sub_ln269_z + 10'h1;
      case (1'b1)
        !mul_ln239_z[47]: case_mux_man_ln321_z = 3'h1;
        and_ln325_z: case_mux_man_ln321_z = 3'h2;
        default: case_mux_man_ln321_z = 3'h4;
      endcase
      if (and_ln335_z) 
        mux_man_ln335_z = {add_ln336_z, 1'b0};
      else 
        mux_man_ln335_z = {1'b0, mul_ln239_z[46:23]};
      case (1'b1)
        mul_ln239_z[47]: case_mux_exp_ln321_z = 3'h1;
        mux_man_ln335_z[24]: case_mux_exp_ln321_z = 3'h2;
        default: case_mux_exp_ln321_z = 3'h4;
      endcase
      case (1'b1)// pragma parallel_case
        case_mux_exp_ln321_z[0]: mux_exp_ln321_z = add_ln328_z;
        case_mux_exp_ln321_z[1]: mux_exp_ln321_z = add_ln344_z;
        case_mux_exp_ln321_z[2]: mux_exp_ln321_z = sub_ln269_z;
        default: mux_exp_ln321_z = 10'hX;
      endcase
      ternaryMux_ln348_1_z = |{mux_exp_ln321_z[8], mux_exp_ln321_z[9]};
      eq_ln348_z = mux_exp_ln321_z[7:0] == 8'hff;
      ternaryMux_ln348_0_0_z = ternaryMux_ln348_1_z | eq_ln348_z;
      if_ln348_1_z = ~ternaryMux_ln348_0_0_z;
      or_if_ln251_Z_0_z = ternaryMux_ln348_0_0_z | lt_ln251_z;
      case (1'b1)
        lt_ln251_z: case_mux_exp_ln251_z = 3'h1;
        ternaryMux_ln348_0_0_z: case_mux_exp_ln251_z = 3'h2;
        default: case_mux_exp_ln251_z = 3'h4;
      endcase
      and_case_mux_man_ln321_1_z = if_ln348_1_z & case_mux_man_ln321_z[1] & !
      lt_ln251_z;
      and_if_ln338_0_0_0_z = case_mux_man_ln321_z[0] & !mux_man_ln335_z[24] & 
      if_ln348_1_z & !lt_ln251_z;
      and_if_ln338_1_0_z = case_mux_man_ln321_z[0] & mux_man_ln335_z[24] & 
      if_ln348_1_z & !lt_ln251_z;
      and_case_mux_man_ln321_0_0_z = if_ln348_1_z & case_mux_man_ln321_z[2] & !
      lt_ln251_z;
      case (1'b1)// pragma parallel_case
        case_mux_exp_ln251_z[0]: mux_exp_ln251_z = 8'h0;
        case_mux_exp_ln251_z[1]: mux_exp_ln251_z = 8'hff;
        case_mux_exp_ln251_z[2]: mux_exp_ln251_z = mux_exp_ln321_z[7:0];
        default: mux_exp_ln251_z = 8'hX;
      endcase
      case (1'b1)// pragma parallel_case
        or_if_ln251_Z_0_z: mux_man_ln251_z = 23'h0;
        and_case_mux_man_ln321_1_z: mux_man_ln251_z = {add_ln326_z, 1'b0};
        and_case_mux_man_ln321_0_0_z: mux_man_ln251_z = mul_ln239_z[46:24];
        and_if_ln338_1_0_z: mux_man_ln251_z = mux_man_ln335_z[23:1];
        and_if_ln338_0_0_0_z: mux_man_ln251_z = mux_man_ln335_z[22:0];
        default: mux_man_ln251_z = 23'hX;
      endcase
      multiply_exp_out = mux_exp_ln251_z;
      multiply_man_out = mux_man_ln251_z;
    end
endmodule


module operatorplus_(this__man_in, this__exp_in, this__sign_in, rhs_man_in, 
rhs_exp_in, rhs_sign_in, operatorplus__man_out, operatorplus__exp_out, 
operatorplus__sign_out);
  input [22:0] this__man_in;
  input [7:0] this__exp_in;
  input this__sign_in;
  input [22:0] rhs_man_in;
  input [7:0] rhs_exp_in;
  input rhs_sign_in;
  output reg [22:0] operatorplus__man_out;
  output reg [7:0] operatorplus__exp_out;
  output reg operatorplus__sign_out;
  wire [22:0] add_sub_exceptions_ln638_add_sub_exceptions_man_out;
  wire [7:0] add_sub_exceptions_ln638_add_sub_exceptions_exp_out;
  wire add_sub_exceptions_ln638_add_sub_exceptions_sign_out;

  add_sub_exceptions add_sub_exceptions_ln638(.add1_man_in(this__man_in), .add1_exp_in(
                     this__exp_in), .add1_sign_in(this__sign_in), .add2_man_in(
                     rhs_man_in), .add2_exp_in(rhs_exp_in), .add2_sign_in(
                     rhs_sign_in), .add_sub_exceptions_man_out(
                     add_sub_exceptions_ln638_add_sub_exceptions_man_out), .add_sub_exceptions_exp_out(
                     add_sub_exceptions_ln638_add_sub_exceptions_exp_out), .add_sub_exceptions_sign_out(
                     add_sub_exceptions_ln638_add_sub_exceptions_sign_out));
  always @(*) begin : operatorplus__combinational
      operatorplus__man_out = 
      add_sub_exceptions_ln638_add_sub_exceptions_man_out;
      operatorplus__sign_out = 
      add_sub_exceptions_ln638_add_sub_exceptions_sign_out;
      operatorplus__exp_out = 
      add_sub_exceptions_ln638_add_sub_exceptions_exp_out;
    end
endmodule


module add_sub_exceptions(add1_man_in, add1_exp_in, add1_sign_in, add2_man_in, 
add2_exp_in, add2_sign_in, add_sub_exceptions_man_out, 
add_sub_exceptions_exp_out, add_sub_exceptions_sign_out);
  input [22:0] add1_man_in;
  input [7:0] add1_exp_in;
  input add1_sign_in;
  input [22:0] add2_man_in;
  input [7:0] add2_exp_in;
  input add2_sign_in;
  output reg [22:0] add_sub_exceptions_man_out;
  output reg [7:0] add_sub_exceptions_exp_out;
  output reg add_sub_exceptions_sign_out;
  wire is_NaN_ln381_z;
  wire is_NaN_ln381_0_z;
  wire is_inf_ln389_z;
  wire is_inf_ln389_0_z;
  wire is_inf_ln394_z;
  wire is_inf_ln394_0_z;
  wire is_inf_ln403_z;
  wire is_zero_or_denormal_ln413_z;
  wire is_zero_or_denormal_ln419_z;
  wire is_zero_or_denormal_ln433_z;
  wire is_zero_or_denormal_ln439_z;
  wire [22:0] add_sub_ln451_add_sub_man_out;
  wire [7:0] add_sub_ln451_add_sub_exp_out;
  wire add_sub_ln451_add_sub_sign_out;

  add_sub add_sub_ln451(.num1_man_in(add1_man_in), .num1_exp_in(add1_exp_in), .num1_sign_in(
          add1_sign_in), .num2_man_in(add2_man_in), .num2_exp_in(add2_exp_in), .num2_sign_in(
          add2_sign_in), .add_sub_man_out(add_sub_ln451_add_sub_man_out), .add_sub_exp_out(
          add_sub_ln451_add_sub_exp_out), .add_sub_sign_out(
          add_sub_ln451_add_sub_sign_out));
  is_zero_or_denormal is_zero_or_denormal_ln419(.fp_exp_in(add2_exp_in), .is_zero_or_denormal_out(
                      is_zero_or_denormal_ln419_z));
  is_zero_or_denormal is_zero_or_denormal_ln439(.fp_exp_in(add1_exp_in), .is_zero_or_denormal_out(
                      is_zero_or_denormal_ln439_z));
  is_inf is_inf_ln403(.fp_man_in(add1_man_in), .fp_exp_in(add1_exp_in), .is_inf_out(
         is_inf_ln403_z));
  is_NaN is_NaN_ln381(.fp_man_in(add1_man_in), .fp_exp_in(add1_exp_in), .is_NaN_out(
         is_NaN_ln381_z));
  is_inf is_inf_ln389(.fp_man_in(add1_man_in), .fp_exp_in(add1_exp_in), .is_inf_out(
         is_inf_ln389_z));
  is_inf is_inf_ln394(.fp_man_in(add1_man_in), .fp_exp_in(add1_exp_in), .is_inf_out(
         is_inf_ln394_z));
  is_zero_or_denormal is_zero_or_denormal_ln413(.fp_exp_in(add1_exp_in), .is_zero_or_denormal_out(
                      is_zero_or_denormal_ln413_z));
  is_zero_or_denormal is_zero_or_denormal_ln433(.fp_exp_in(add2_exp_in), .is_zero_or_denormal_out(
                      is_zero_or_denormal_ln433_z));
  is_NaN is_NaN_ln381_0(.fp_man_in(add2_man_in), .fp_exp_in(add2_exp_in), .is_NaN_out(
         is_NaN_ln381_0_z));
  is_inf is_inf_ln389_0(.fp_man_in(add2_man_in), .fp_exp_in(add2_exp_in), .is_inf_out(
         is_inf_ln389_0_z));
  is_inf is_inf_ln394_0(.fp_man_in(add2_man_in), .fp_exp_in(add2_exp_in), .is_inf_out(
         is_inf_ln394_0_z));
  always @(*) begin : add_sub_exceptions_combinational
      reg ne_ln394_z;
      reg ternaryMux_ln381_0_z;
      reg ternaryMux_ln389_0_z;
      reg ternaryMux_ln394_1_z;
      reg [2:0] case_mux_res_exp_ln381_zip_0_z;
      reg [2:0] case_mux_res_sign_ln381_zip_z;
      reg and_case_mux_res_exp_ln381_zip_0_1_0_z;
      reg and_case_mux_res_exp_ln381_zip_0_2_0_z;
      reg and_case_mux_res_exp_ln381_zip_1_0_0_z;
      reg and_case_mux_res_exp_ln381_zip_2_0_z;
      reg and_case_mux_res_sign_ln381_zip_0_0_0_z;
      reg and_case_mux_res_sign_ln381_zip_1_0_0_z;
      reg and_case_mux_res_sign_ln381_zip_2_0_z;
      reg and_if_ln389_0_z;
      reg and_if_ln413_0_z;
      reg or_if_ln381_0_Z_0_0_z;
      reg and_case_mux_res_exp_ln381_zip_0_0_0_z;
      reg ternaryMux_ln394_0_0_z;
      reg or_and_case_mux_res_exp_ln381_zip_0_0_0_Z_0_z;
      reg [7:0] mux_res_exp_ln381_z;
      reg [22:0] mux_res_man_ln381_z;
      reg [2:0] case_mux_res_sign_ln394_z;
      reg and_case_mux_res_sign_ln394_1_0_z;
      reg and_case_mux_res_sign_ln394_2_z;
      reg and_case_mux_res_sign_ln394_0_0_z;
      reg or_and_case_mux_res_sign_ln394_1_0_Z_0_z;
      reg or_if_ln381_0_Z_0_z;
      reg or_and_case_mux_res_sign_ln394_0_0_Z_0_z;
      reg mux_res_sign_ln381_z;

      ne_ln394_z = add2_sign_in ^ add1_sign_in;
      ternaryMux_ln381_0_z = is_NaN_ln381_z | is_NaN_ln381_0_z;
      ternaryMux_ln389_0_z = is_inf_ln389_z | is_inf_ln389_0_z;
      ternaryMux_ln394_1_z = is_inf_ln394_z & is_inf_ln394_0_z;
      case (1'b1)
        !is_zero_or_denormal_ln413_z: case_mux_res_exp_ln381_zip_0_z = 3'h1;
        is_zero_or_denormal_ln419_z: case_mux_res_exp_ln381_zip_0_z = 3'h2;
        default: case_mux_res_exp_ln381_zip_0_z = 3'h4;
      endcase
      case (1'b1)
        !is_zero_or_denormal_ln433_z: case_mux_res_sign_ln381_zip_z = 3'h1;
        is_zero_or_denormal_ln439_z: case_mux_res_sign_ln381_zip_z = 3'h2;
        default: case_mux_res_sign_ln381_zip_z = 3'h4;
      endcase
      and_case_mux_res_exp_ln381_zip_0_1_0_z = !ternaryMux_ln389_0_z & 
      case_mux_res_exp_ln381_zip_0_z[2] & !ternaryMux_ln381_0_z;
      and_case_mux_res_exp_ln381_zip_0_2_0_z = case_mux_res_exp_ln381_zip_0_z[0] & 
      case_mux_res_sign_ln381_zip_z[1] & !ternaryMux_ln389_0_z & !
      ternaryMux_ln381_0_z;
      and_case_mux_res_exp_ln381_zip_1_0_0_z = case_mux_res_exp_ln381_zip_0_z[0] & 
      case_mux_res_sign_ln381_zip_z[2] & !ternaryMux_ln389_0_z & !
      ternaryMux_ln381_0_z;
      and_case_mux_res_exp_ln381_zip_2_0_z = case_mux_res_exp_ln381_zip_0_z[0] & 
      case_mux_res_sign_ln381_zip_z[0] & !ternaryMux_ln389_0_z & !
      ternaryMux_ln381_0_z;
      and_case_mux_res_sign_ln381_zip_0_0_0_z = !is_zero_or_denormal_ln413_z & 
      case_mux_res_sign_ln381_zip_z[1] & !ternaryMux_ln389_0_z & !
      ternaryMux_ln381_0_z;
      and_case_mux_res_sign_ln381_zip_1_0_0_z = !is_zero_or_denormal_ln413_z & 
      case_mux_res_sign_ln381_zip_z[2] & !ternaryMux_ln389_0_z & !
      ternaryMux_ln381_0_z;
      and_case_mux_res_sign_ln381_zip_2_0_z = !is_zero_or_denormal_ln413_z & 
      case_mux_res_sign_ln381_zip_z[0] & !ternaryMux_ln389_0_z & !
      ternaryMux_ln381_0_z;
      and_if_ln389_0_z = !ternaryMux_ln381_0_z & ternaryMux_ln389_0_z;
      and_if_ln413_0_z = !ternaryMux_ln389_0_z & is_zero_or_denormal_ln413_z & !
      ternaryMux_ln381_0_z;
      or_if_ln381_0_Z_0_0_z = ternaryMux_ln389_0_z | ternaryMux_ln381_0_z;
      and_case_mux_res_exp_ln381_zip_0_0_0_z = !ternaryMux_ln389_0_z & 
      case_mux_res_exp_ln381_zip_0_z[1] & !ternaryMux_ln381_0_z;
      ternaryMux_ln394_0_0_z = ternaryMux_ln394_1_z & ne_ln394_z;
      or_and_case_mux_res_exp_ln381_zip_0_0_0_Z_0_z = 
      and_case_mux_res_exp_ln381_zip_0_2_0_z | 
      and_case_mux_res_exp_ln381_zip_0_0_0_z;
      case (1'b1)// pragma parallel_case
        or_if_ln381_0_Z_0_0_z: mux_res_exp_ln381_z = 8'hff;
        or_and_case_mux_res_exp_ln381_zip_0_0_0_Z_0_z: mux_res_exp_ln381_z = 
          8'h0;
        and_case_mux_res_exp_ln381_zip_0_1_0_z: mux_res_exp_ln381_z = 
          add2_exp_in;
        and_case_mux_res_exp_ln381_zip_2_0_z: mux_res_exp_ln381_z = 
          add_sub_ln451_add_sub_exp_out;
        and_case_mux_res_exp_ln381_zip_1_0_0_z: mux_res_exp_ln381_z = 
          add1_exp_in;
        default: mux_res_exp_ln381_z = 8'hX;
      endcase
      case (1'b1)// pragma parallel_case
        ternaryMux_ln381_0_z: mux_res_man_ln381_z = 23'h1;
        and_if_ln389_0_z: mux_res_man_ln381_z = {22'h0, ternaryMux_ln394_0_0_z};
        or_and_case_mux_res_exp_ln381_zip_0_0_0_Z_0_z: mux_res_man_ln381_z = 
          23'h0;
        and_case_mux_res_exp_ln381_zip_0_1_0_z: mux_res_man_ln381_z = 
          add2_man_in;
        and_case_mux_res_exp_ln381_zip_2_0_z: mux_res_man_ln381_z = 
          add_sub_ln451_add_sub_man_out;
        and_case_mux_res_exp_ln381_zip_1_0_0_z: mux_res_man_ln381_z = 
          add1_man_in;
        default: mux_res_man_ln381_z = 23'hX;
      endcase
      case (1'b1)
        ternaryMux_ln394_0_0_z: case_mux_res_sign_ln394_z = 3'h1;
        is_inf_ln403_z: case_mux_res_sign_ln394_z = 3'h2;
        default: case_mux_res_sign_ln394_z = 3'h4;
      endcase
      add_sub_exceptions_exp_out = mux_res_exp_ln381_z;
      add_sub_exceptions_man_out = mux_res_man_ln381_z;
      and_case_mux_res_sign_ln394_1_0_z = ternaryMux_ln389_0_z & 
      case_mux_res_sign_ln394_z[2] & !ternaryMux_ln381_0_z;
      and_case_mux_res_sign_ln394_2_z = ternaryMux_ln389_0_z & 
      case_mux_res_sign_ln394_z[0] & !ternaryMux_ln381_0_z;
      and_case_mux_res_sign_ln394_0_0_z = ternaryMux_ln389_0_z & 
      case_mux_res_sign_ln394_z[1] & !ternaryMux_ln381_0_z;
      or_and_case_mux_res_sign_ln394_1_0_Z_0_z = 
      and_case_mux_res_sign_ln381_zip_0_0_0_z | and_if_ln413_0_z | 
      and_case_mux_res_sign_ln394_1_0_z;
      or_if_ln381_0_Z_0_z = and_case_mux_res_sign_ln394_2_z | 
      ternaryMux_ln381_0_z;
      or_and_case_mux_res_sign_ln394_0_0_Z_0_z = 
      and_case_mux_res_sign_ln381_zip_1_0_0_z | 
      and_case_mux_res_sign_ln394_0_0_z;
      case (1'b1)// pragma parallel_case
        or_if_ln381_0_Z_0_z: mux_res_sign_ln381_z = 1'b0;
        or_and_case_mux_res_sign_ln394_0_0_Z_0_z: mux_res_sign_ln381_z = 
          add1_sign_in;
        or_and_case_mux_res_sign_ln394_1_0_Z_0_z: mux_res_sign_ln381_z = 
          add2_sign_in;
        and_case_mux_res_sign_ln381_zip_2_0_z: mux_res_sign_ln381_z = 
          add_sub_ln451_add_sub_sign_out;
        default: mux_res_sign_ln381_z = 1'bX;
      endcase
      add_sub_exceptions_sign_out = mux_res_sign_ln381_z;
    end
endmodule


module add_sub(num1_man_in, num1_exp_in, num1_sign_in, num2_man_in, num2_exp_in, 
num2_sign_in, add_sub_man_out, add_sub_exp_out, add_sub_sign_out);
  input [22:0] num1_man_in;
  input [7:0] num1_exp_in;
  input num1_sign_in;
  input [22:0] num2_man_in;
  input [7:0] num2_exp_in;
  input num2_sign_in;
  output reg [22:0] add_sub_man_out;
  output reg [7:0] add_sub_exp_out;
  output reg add_sub_sign_out;

  always @(*) begin : add_sub_combinational
      reg eq_ln545_z;
      reg gt_ln499_z;
      reg [7:0] mux_sub_ln501_ln501_0_z;
      reg [7:0] ternaryMux_ln500_z;
      reg [8:0] sub_ln501_z;
      reg [23:0] rsh_ln516_z;
      reg [23:0] rsh_ln523_z;
      reg gt_ln509_z;
      reg [23:0] mux_man1_ln514_z;
      reg [23:0] mux_man2_ln514_z;
      reg and_if_ln500_0_z;
      reg if_ln509_z;
      reg and_if_ln500_z;
      reg gt_ln535_z;
      reg [23:0] ternaryMux_ln536_z;
      reg [23:0] ternaryMux_ln537_z;
      reg [1:0] case_ternaryMux_ln659_0_z;
      reg [24:0] add_ln546_z;
      reg [24:0] sub_ln548_z;
      reg [2:0] case_mux_res_sign_ln509_z;
      reg [25:0] mux_man_ln545_z;
      reg and_if_ln500_2_z;
      reg and_if_ln500_1_z;
      reg and_ln570_z;
      reg eq_ln558_z;
      reg eq_ln585_z;
      reg eq_ln593_unr1_z;
      reg eq_ln593_unr10_z;
      reg eq_ln593_unr11_z;
      reg eq_ln593_unr12_z;
      reg eq_ln593_unr13_z;
      reg eq_ln593_unr14_z;
      reg eq_ln593_unr15_z;
      reg eq_ln593_unr16_z;
      reg eq_ln593_unr17_z;
      reg eq_ln593_unr18_z;
      reg eq_ln593_unr19_z;
      reg eq_ln593_unr2_z;
      reg eq_ln593_unr20_z;
      reg eq_ln593_unr21_z;
      reg eq_ln593_unr22_z;
      reg eq_ln593_unr3_z;
      reg eq_ln593_unr4_z;
      reg eq_ln593_unr5_z;
      reg eq_ln593_unr6_z;
      reg eq_ln593_unr7_z;
      reg eq_ln593_unr8_z;
      reg eq_ln593_unr9_z;
      reg if_ln563_z;
      reg [23:0] add_ln571_z;
      reg or_case_mux_res_sign_ln509_Z_1_z;
      reg or_case_mux_res_sign_ln509_Z_2_z;
      reg and_1_ln558_z;
      reg and_0_ln558_z;
      reg mux_res_sign_ln509_z;
      reg [25:0] mux_man_ln570_z;
      reg and_1_ln563_z;
      reg and_0_ln563_z;
      reg if_ln573_z;
      reg and_1_ln585_z;
      reg and_0_ln585_z;
      reg [22:0] rsh_ln577_z;
      reg [7:0] add_ln578_z;
      reg or_and_0_ln558_Z_0_z;
      reg or_and_0_ln558_Z_0_0_z;
      reg and_1_ln591_unr0_z;
      reg and_0_ln593_unr0_z;
      reg and_1_ln591_unr1_z;
      reg and_0_ln593_unr1_z;
      reg and_1_ln591_unr2_z;
      reg and_0_ln593_unr2_z;
      reg and_1_ln591_unr3_z;
      reg and_0_ln593_unr3_z;
      reg and_1_ln591_unr4_z;
      reg and_0_ln593_unr4_z;
      reg and_1_ln591_unr5_z;
      reg and_0_ln593_unr5_z;
      reg and_1_ln591_unr6_z;
      reg and_0_ln593_unr6_z;
      reg and_1_ln591_unr7_z;
      reg and_0_ln593_unr7_z;
      reg and_1_ln591_unr8_z;
      reg and_0_ln593_unr8_z;
      reg and_1_ln591_unr9_z;
      reg and_0_ln593_unr9_z;
      reg and_1_ln591_unr10_z;
      reg and_0_ln593_unr10_z;
      reg and_1_ln591_unr11_z;
      reg and_0_ln593_unr11_z;
      reg and_1_ln591_unr12_z;
      reg and_0_ln593_unr12_z;
      reg and_1_ln591_unr13_z;
      reg and_0_ln593_unr13_z;
      reg and_1_ln591_unr14_z;
      reg and_0_ln593_unr14_z;
      reg and_1_ln591_unr15_z;
      reg and_0_ln593_unr15_z;
      reg and_1_ln591_unr16_z;
      reg and_0_ln593_unr16_z;
      reg and_1_ln591_unr17_z;
      reg and_0_ln593_unr17_z;
      reg and_1_ln591_unr18_z;
      reg and_0_ln593_unr18_z;
      reg and_1_ln591_unr19_z;
      reg and_0_ln593_unr19_z;
      reg and_1_ln591_unr20_z;
      reg and_0_ln593_unr20_z;
      reg and_1_ln591_unr21_z;
      reg and_0_ln593_unr21_z;
      reg and_1_ln591_unr22_z;
      reg and_0_ln593_unr22_z;
      reg or_and_0_ln593_unr22_Z_0_z;
      reg [4:0] mux_exit_mux_man_shift_ln591_z;
      reg or_and_0_ln558_Z_0_Z_0_z;
      reg lt_ln610_z;
      reg [7:0] sub_ln613_z;
      reg signed [22:0] lsh_ln612_z;
      reg [2:0] case_mux_exp_ln558_z;
      reg and_case_mux_exp_ln558_0_z;
      reg and_case_mux_exp_ln558_1_z;
      reg and_case_mux_exp_ln558_z;
      reg and_0_ln563_0_z;
      reg and_1_ln585_0_z;
      reg and_or_and_0_ln558_Z_0_0_z;
      reg and_0_ln558_0_z;
      reg or_if_ln509_Z_0_z;
      reg [22:0] mux_res_man_ln509_z;
      reg or_and_case_mux_exp_ln558_1_Z_0_z;
      reg [7:0] mux_res_exp_ln509_z;

      eq_ln545_z = ~(num2_sign_in ^ num1_sign_in);
      gt_ln499_z = {1'b0, num2_exp_in} > {1'b0, num1_exp_in};
      if (gt_ln499_z) begin
        mux_sub_ln501_ln501_0_z = num1_exp_in;
        ternaryMux_ln500_z = num2_exp_in;
      end
      else begin
        mux_sub_ln501_ln501_0_z = num2_exp_in;
        ternaryMux_ln500_z = num1_exp_in;
      end
      sub_ln501_z = {1'b0, ternaryMux_ln500_z} - mux_sub_ln501_ln501_0_z;
      rsh_ln516_z = {1'b1, num1_man_in} >> {{23{sub_ln501_z[8]}}, sub_ln501_z};
      rsh_ln523_z = {1'b1, num2_man_in} >> {{23{sub_ln501_z[8]}}, sub_ln501_z};
      gt_ln509_z = sub_ln501_z[8:3] > 6'h2;
      if (gt_ln499_z) 
        mux_man1_ln514_z = rsh_ln516_z;
      else 
        mux_man1_ln514_z = {1'b1, num1_man_in};
      if (gt_ln499_z) 
        mux_man2_ln514_z = {1'b1, num2_man_in};
      else 
        mux_man2_ln514_z = rsh_ln523_z;
      and_if_ln500_0_z = gt_ln509_z & !gt_ln499_z;
      if_ln509_z = ~gt_ln509_z;
      and_if_ln500_z = gt_ln509_z & gt_ln499_z;
      gt_ln535_z = {1'b0, mux_man1_ln514_z} > {1'b0, mux_man2_ln514_z};
      if (gt_ln535_z) begin
        ternaryMux_ln536_z = mux_man1_ln514_z;
        ternaryMux_ln537_z = mux_man2_ln514_z;
      end
      else begin
        ternaryMux_ln536_z = mux_man2_ln514_z;
        ternaryMux_ln537_z = mux_man1_ln514_z;
      end
      case (1'b1)
        eq_ln545_z: case_ternaryMux_ln659_0_z = 2'h1;
        gt_ln535_z: case_ternaryMux_ln659_0_z = 2'h1;
        default: case_ternaryMux_ln659_0_z = 2'h2;
      endcase
      add_ln546_z = {1'b0, ternaryMux_ln536_z} + ternaryMux_ln537_z;
      sub_ln548_z = {1'b0, ternaryMux_ln536_z} - ternaryMux_ln537_z;
      case (1'b1)
        gt_ln509_z: case_mux_res_sign_ln509_z = 3'h1;
        case_ternaryMux_ln659_0_z[0]: case_mux_res_sign_ln509_z = 3'h2;
        default: case_mux_res_sign_ln509_z = 3'h4;
      endcase
      if (eq_ln545_z) 
        mux_man_ln545_z = {1'b0, add_ln546_z};
      else 
        mux_man_ln545_z = {sub_ln548_z[24], sub_ln548_z};
      and_if_ln500_2_z = case_mux_res_sign_ln509_z[0] & !gt_ln499_z;
      and_if_ln500_1_z = case_mux_res_sign_ln509_z[0] & gt_ln499_z;
      and_ln570_z = &mux_man_ln545_z[1:0];
      eq_ln558_z = mux_man_ln545_z == 26'h0;
      eq_ln585_z = ~mux_man_ln545_z[23];
      eq_ln593_unr1_z = ~mux_man_ln545_z[22];
      eq_ln593_unr10_z = ~mux_man_ln545_z[13];
      eq_ln593_unr11_z = ~mux_man_ln545_z[12];
      eq_ln593_unr12_z = ~mux_man_ln545_z[11];
      eq_ln593_unr13_z = ~mux_man_ln545_z[10];
      eq_ln593_unr14_z = ~mux_man_ln545_z[9];
      eq_ln593_unr15_z = ~mux_man_ln545_z[8];
      eq_ln593_unr16_z = ~mux_man_ln545_z[7];
      eq_ln593_unr17_z = ~mux_man_ln545_z[6];
      eq_ln593_unr18_z = ~mux_man_ln545_z[5];
      eq_ln593_unr19_z = ~mux_man_ln545_z[4];
      eq_ln593_unr2_z = ~mux_man_ln545_z[21];
      eq_ln593_unr20_z = ~mux_man_ln545_z[3];
      eq_ln593_unr21_z = ~mux_man_ln545_z[2];
      eq_ln593_unr22_z = ~mux_man_ln545_z[1];
      eq_ln593_unr3_z = ~mux_man_ln545_z[20];
      eq_ln593_unr4_z = ~mux_man_ln545_z[19];
      eq_ln593_unr5_z = ~mux_man_ln545_z[18];
      eq_ln593_unr6_z = ~mux_man_ln545_z[17];
      eq_ln593_unr7_z = ~mux_man_ln545_z[16];
      eq_ln593_unr8_z = ~mux_man_ln545_z[15];
      eq_ln593_unr9_z = ~mux_man_ln545_z[14];
      if_ln563_z = ~mux_man_ln545_z[24];
      add_ln571_z = {mux_man_ln545_z[25], 1'b1, mux_man_ln545_z[23:2]} + 24'h1;
      or_case_mux_res_sign_ln509_Z_1_z = and_if_ln500_2_z | 
      case_mux_res_sign_ln509_z[1];
      or_case_mux_res_sign_ln509_Z_2_z = and_if_ln500_1_z | 
      case_mux_res_sign_ln509_z[2];
      and_1_ln558_z = !eq_ln558_z & if_ln509_z;
      and_0_ln558_z = eq_ln558_z & if_ln509_z;
      case (1'b1)// pragma parallel_case
        or_case_mux_res_sign_ln509_Z_1_z: mux_res_sign_ln509_z = num1_sign_in;
        or_case_mux_res_sign_ln509_Z_2_z: mux_res_sign_ln509_z = num2_sign_in;
        default: mux_res_sign_ln509_z = 1'bX;
      endcase
      if (and_ln570_z) 
        mux_man_ln570_z = {add_ln571_z, 2'h0};
      else 
        mux_man_ln570_z = {mux_man_ln545_z[25], 1'b1, mux_man_ln545_z[23:0]};
      and_1_ln563_z = if_ln563_z & and_1_ln558_z;
      and_0_ln563_z = mux_man_ln545_z[24] & and_1_ln558_z;
      add_sub_sign_out = mux_res_sign_ln509_z;
      if_ln573_z = ~mux_man_ln570_z[25];
      and_1_ln585_z = mux_man_ln545_z[23] & and_1_ln563_z;
      and_0_ln585_z = eq_ln585_z & and_1_ln563_z;
      rsh_ln577_z = mux_man_ln570_z[24:0] >> {mux_man_ln570_z[25], if_ln573_z};
      add_ln578_z = ternaryMux_ln500_z + {mux_man_ln570_z[25], if_ln573_z};
      or_and_0_ln558_Z_0_z = and_1_ln585_z | and_0_ln563_z | and_0_ln558_z;
      or_and_0_ln558_Z_0_0_z = and_1_ln585_z | and_0_ln558_z;
      and_1_ln591_unr0_z = mux_man_ln545_z[23] & and_0_ln585_z;
      and_0_ln593_unr0_z = eq_ln585_z & and_0_ln585_z;
      and_1_ln591_unr1_z = mux_man_ln545_z[22] & and_0_ln593_unr0_z;
      and_0_ln593_unr1_z = eq_ln593_unr1_z & and_0_ln593_unr0_z;
      and_1_ln591_unr2_z = mux_man_ln545_z[21] & and_0_ln593_unr1_z;
      and_0_ln593_unr2_z = eq_ln593_unr2_z & and_0_ln593_unr1_z;
      and_1_ln591_unr3_z = mux_man_ln545_z[20] & and_0_ln593_unr2_z;
      and_0_ln593_unr3_z = eq_ln593_unr3_z & and_0_ln593_unr2_z;
      and_1_ln591_unr4_z = mux_man_ln545_z[19] & and_0_ln593_unr3_z;
      and_0_ln593_unr4_z = eq_ln593_unr4_z & and_0_ln593_unr3_z;
      and_1_ln591_unr5_z = mux_man_ln545_z[18] & and_0_ln593_unr4_z;
      and_0_ln593_unr5_z = eq_ln593_unr5_z & and_0_ln593_unr4_z;
      and_1_ln591_unr6_z = mux_man_ln545_z[17] & and_0_ln593_unr5_z;
      and_0_ln593_unr6_z = eq_ln593_unr6_z & and_0_ln593_unr5_z;
      and_1_ln591_unr7_z = mux_man_ln545_z[16] & and_0_ln593_unr6_z;
      and_0_ln593_unr7_z = eq_ln593_unr7_z & and_0_ln593_unr6_z;
      and_1_ln591_unr8_z = mux_man_ln545_z[15] & and_0_ln593_unr7_z;
      and_0_ln593_unr8_z = eq_ln593_unr8_z & and_0_ln593_unr7_z;
      and_1_ln591_unr9_z = mux_man_ln545_z[14] & and_0_ln593_unr8_z;
      and_0_ln593_unr9_z = eq_ln593_unr9_z & and_0_ln593_unr8_z;
      and_1_ln591_unr10_z = mux_man_ln545_z[13] & and_0_ln593_unr9_z;
      and_0_ln593_unr10_z = eq_ln593_unr10_z & and_0_ln593_unr9_z;
      and_1_ln591_unr11_z = mux_man_ln545_z[12] & and_0_ln593_unr10_z;
      and_0_ln593_unr11_z = eq_ln593_unr11_z & and_0_ln593_unr10_z;
      and_1_ln591_unr12_z = mux_man_ln545_z[11] & and_0_ln593_unr11_z;
      and_0_ln593_unr12_z = eq_ln593_unr12_z & and_0_ln593_unr11_z;
      and_1_ln591_unr13_z = mux_man_ln545_z[10] & and_0_ln593_unr12_z;
      and_0_ln593_unr13_z = eq_ln593_unr13_z & and_0_ln593_unr12_z;
      and_1_ln591_unr14_z = mux_man_ln545_z[9] & and_0_ln593_unr13_z;
      and_0_ln593_unr14_z = eq_ln593_unr14_z & and_0_ln593_unr13_z;
      and_1_ln591_unr15_z = mux_man_ln545_z[8] & and_0_ln593_unr14_z;
      and_0_ln593_unr15_z = eq_ln593_unr15_z & and_0_ln593_unr14_z;
      and_1_ln591_unr16_z = mux_man_ln545_z[7] & and_0_ln593_unr15_z;
      and_0_ln593_unr16_z = eq_ln593_unr16_z & and_0_ln593_unr15_z;
      and_1_ln591_unr17_z = mux_man_ln545_z[6] & and_0_ln593_unr16_z;
      and_0_ln593_unr17_z = eq_ln593_unr17_z & and_0_ln593_unr16_z;
      and_1_ln591_unr18_z = mux_man_ln545_z[5] & and_0_ln593_unr17_z;
      and_0_ln593_unr18_z = eq_ln593_unr18_z & and_0_ln593_unr17_z;
      and_1_ln591_unr19_z = mux_man_ln545_z[4] & and_0_ln593_unr18_z;
      and_0_ln593_unr19_z = eq_ln593_unr19_z & and_0_ln593_unr18_z;
      and_1_ln591_unr20_z = mux_man_ln545_z[3] & and_0_ln593_unr19_z;
      and_0_ln593_unr20_z = eq_ln593_unr20_z & and_0_ln593_unr19_z;
      and_1_ln591_unr21_z = mux_man_ln545_z[2] & and_0_ln593_unr20_z;
      and_0_ln593_unr21_z = eq_ln593_unr21_z & and_0_ln593_unr20_z;
      and_1_ln591_unr22_z = mux_man_ln545_z[1] & and_0_ln593_unr21_z;
      and_0_ln593_unr22_z = eq_ln593_unr22_z & and_0_ln593_unr21_z;
      or_and_0_ln593_unr22_Z_0_z = and_1_ln591_unr22_z | and_1_ln591_unr21_z | 
      and_1_ln591_unr20_z | and_1_ln591_unr19_z | and_1_ln591_unr18_z | 
      and_1_ln591_unr17_z | and_1_ln591_unr16_z | and_1_ln591_unr15_z | 
      and_1_ln591_unr14_z | and_1_ln591_unr13_z | and_1_ln591_unr12_z | 
      and_1_ln591_unr11_z | and_1_ln591_unr10_z | and_1_ln591_unr9_z | 
      and_1_ln591_unr8_z | and_1_ln591_unr7_z | and_1_ln591_unr6_z | 
      and_1_ln591_unr5_z | and_1_ln591_unr4_z | and_1_ln591_unr3_z | 
      and_1_ln591_unr2_z | and_1_ln591_unr1_z | and_1_ln591_unr0_z | 
      and_0_ln593_unr22_z;
      case (1'b1)// pragma parallel_case
        and_1_ln591_unr0_z: mux_exit_mux_man_shift_ln591_z = 5'h0;
        and_1_ln591_unr1_z: mux_exit_mux_man_shift_ln591_z = 5'h1;
        and_1_ln591_unr2_z: mux_exit_mux_man_shift_ln591_z = 5'h2;
        and_1_ln591_unr3_z: mux_exit_mux_man_shift_ln591_z = 5'h3;
        and_1_ln591_unr4_z: mux_exit_mux_man_shift_ln591_z = 5'h4;
        and_1_ln591_unr5_z: mux_exit_mux_man_shift_ln591_z = 5'h5;
        and_1_ln591_unr6_z: mux_exit_mux_man_shift_ln591_z = 5'h6;
        and_1_ln591_unr7_z: mux_exit_mux_man_shift_ln591_z = 5'h7;
        and_1_ln591_unr8_z: mux_exit_mux_man_shift_ln591_z = 5'h8;
        and_1_ln591_unr9_z: mux_exit_mux_man_shift_ln591_z = 5'h9;
        and_1_ln591_unr10_z: mux_exit_mux_man_shift_ln591_z = 5'ha;
        and_1_ln591_unr11_z: mux_exit_mux_man_shift_ln591_z = 5'hb;
        and_1_ln591_unr12_z: mux_exit_mux_man_shift_ln591_z = 5'hc;
        and_1_ln591_unr13_z: mux_exit_mux_man_shift_ln591_z = 5'hd;
        and_1_ln591_unr14_z: mux_exit_mux_man_shift_ln591_z = 5'he;
        and_1_ln591_unr15_z: mux_exit_mux_man_shift_ln591_z = 5'hf;
        and_1_ln591_unr16_z: mux_exit_mux_man_shift_ln591_z = 5'h10;
        and_1_ln591_unr17_z: mux_exit_mux_man_shift_ln591_z = 5'h11;
        and_1_ln591_unr18_z: mux_exit_mux_man_shift_ln591_z = 5'h12;
        and_1_ln591_unr19_z: mux_exit_mux_man_shift_ln591_z = 5'h13;
        and_1_ln591_unr20_z: mux_exit_mux_man_shift_ln591_z = 5'h14;
        and_1_ln591_unr21_z: mux_exit_mux_man_shift_ln591_z = 5'h15;
        and_1_ln591_unr22_z: mux_exit_mux_man_shift_ln591_z = 5'h16;
        and_0_ln593_unr22_z: mux_exit_mux_man_shift_ln591_z = 5'h17;
        default: mux_exit_mux_man_shift_ln591_z = 5'hX;
      endcase
      or_and_0_ln558_Z_0_Z_0_z = or_and_0_ln593_unr22_Z_0_z | 
      or_and_0_ln558_Z_0_z;
      lt_ln610_z = {1'b0, ternaryMux_ln500_z} > {1'b0, 
      mux_exit_mux_man_shift_ln591_z};
      sub_ln613_z = ternaryMux_ln500_z - mux_exit_mux_man_shift_ln591_z;
      lsh_ln612_z = $signed(mux_man_ln545_z[22:0]) << 
      mux_exit_mux_man_shift_ln591_z;
      case (1'b1)
        or_and_0_ln558_Z_0_z: case_mux_exp_ln558_z = 3'h1;
        lt_ln610_z: case_mux_exp_ln558_z = 3'h2;
        default: case_mux_exp_ln558_z = 3'h4;
      endcase
      and_case_mux_exp_ln558_0_z = if_ln509_z & case_mux_exp_ln558_z[1];
      and_case_mux_exp_ln558_1_z = if_ln509_z & case_mux_exp_ln558_z[2];
      and_case_mux_exp_ln558_z = if_ln509_z & case_mux_exp_ln558_z[0];
      and_0_ln563_0_z = and_case_mux_exp_ln558_z & and_0_ln563_z;
      and_1_ln585_0_z = and_case_mux_exp_ln558_z & and_1_ln585_z;
      and_or_and_0_ln558_Z_0_0_z = and_case_mux_exp_ln558_z & 
      or_and_0_ln558_Z_0_0_z;
      and_0_ln558_0_z = and_case_mux_exp_ln558_z & and_0_ln558_z;
      or_if_ln509_Z_0_z = and_1_ln585_0_z | gt_ln509_z;
      case (1'b1)// pragma parallel_case
        and_case_mux_exp_ln558_0_z: mux_res_man_ln509_z = lsh_ln612_z;
        and_case_mux_exp_ln558_1_z: mux_res_man_ln509_z = 23'h0;
        and_if_ln500_z: mux_res_man_ln509_z = num2_man_in;
        and_if_ln500_0_z: mux_res_man_ln509_z = num1_man_in;
        and_or_and_0_ln558_Z_0_0_z: mux_res_man_ln509_z = mux_man_ln545_z[22:0];
        and_0_ln563_0_z: mux_res_man_ln509_z = rsh_ln577_z;
        default: mux_res_man_ln509_z = 23'hX;
      endcase
      or_and_case_mux_exp_ln558_1_Z_0_z = and_0_ln558_0_z | 
      and_case_mux_exp_ln558_1_z;
      add_sub_man_out = mux_res_man_ln509_z;
      case (1'b1)// pragma parallel_case
        or_if_ln509_Z_0_z: mux_res_exp_ln509_z = ternaryMux_ln500_z;
        and_case_mux_exp_ln558_0_z: mux_res_exp_ln509_z = sub_ln613_z;
        or_and_case_mux_exp_ln558_1_Z_0_z: mux_res_exp_ln509_z = 8'h0;
        and_0_ln563_0_z: mux_res_exp_ln509_z = add_ln578_z;
        default: mux_res_exp_ln509_z = 8'hX;
      endcase
      add_sub_exp_out = mux_res_exp_ln509_z;
    end
endmodule


