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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:08:18 04/08/2012 
-- Design Name: 
-- Module Name:    CW_mod - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity CW_mod is
    Port ( clk : in  STD_LOGIC;	
           carrier : in  STD_LOGIC_VECTOR (13 downto 0);
           Mod_in : in  STD_LOGIC;
           CW_out : out  STD_LOGIC_VECTOR (13 downto 0));
end CW_mod;

architecture Behavioral of CW_mod is

signal mult_factor: integer range 0 to 16 := 0;
signal result: SIGNED (13 downto 0);
signal data_in: integer range -8200 to 8200 := 0;
signal data_out: integer range -131072 to 131072 := 0;
signal counter: integer range 0 to 16384 := 0;

begin
 
process (clk) begin
	if rising_edge(clk) then
		-- counter is counting up to the end, after overflow modulation input is tested
		if counter < 16380 then counter <= counter + 1; 
		else 
			counter<= 0; 
			-- increment or decrement multiplication factor
			if mult_factor < 16 AND Mod_in = '1' then 	
				mult_factor <= mult_factor + 1; 				
			elsif	mult_factor > 0 AND Mod_in = '0' then 	
				mult_factor <= mult_factor - 1; 			
			end if;
		end if;			
		
		-- multiply carrier by the factor
		data_out <= ((data_in * mult_factor)/16);
		result <=  CONV_SIGNED(data_out,14);
  
	end if;
end process;	

CW_out <= CONV_STD_LOGIC_VECTOR(result,14);    -- convert to STD_LOGIC
data_in <= CONV_INTEGER(carrier);


end Behavioral;

