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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:56:13 04/07/2012 
-- Design Name: 
-- Module Name:    ADC_AD6645 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ADC_AD6645 is
    Port ( clk : in  STD_LOGIC;
           DRY : in  STD_LOGIC;
           ADC_Data : in  STD_LOGIC_VECTOR (13 downto 0);
           Data_Out : out  STD_LOGIC_VECTOR (13 downto 0));
end ADC_AD6645;

architecture Behavioral of ADC_AD6645 is

signal Data_input_reg: STD_LOGIC_VECTOR (13 downto 0) := (OTHERS => '0');

begin
process (clk) begin
	IF rising_edge(clk) THEN
		--  when Data Ready signal is high, read the data input
		IF DRY = '1' THEN Data_input_reg <= ADC_Data; ELSE Data_input_reg <= (OTHERS => '0');  END IF;
	END IF;
end process;
	
Data_out <= Data_input_reg;

end Behavioral;

