----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:39:42 04/07/2012 
-- Design Name: 
-- Module Name:    Output_MUX - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Output_MUX is
    Port ( clk : in  STD_LOGIC;
           Data_in : in  STD_LOGIC_VECTOR (13 downto 0);
           AM_out : out  STD_LOGIC_VECTOR (13 downto 0);
           FM_out : out  STD_LOGIC_VECTOR (13 downto 0);
           CW_out : out  STD_LOGIC_VECTOR (13 downto 0);
           SSB_out : out  STD_LOGIC_VECTOR (13 downto 0);
           En : in  STD_LOGIC;
           Address : in  STD_LOGIC_VECTOR (2 downto 0));
end Output_MUX;

architecture Behavioral of Output_MUX is

signal input_reg: STD_LOGIC_VECTOR (13 downto 0) := (OTHERS => '0');

begin

process (clk) begin
	IF rising_edge(clk) THEN
		IF En = '1' THEN
			CASE Address IS
				WHEN "000" => 	AM_out <= input_reg;  
				               FM_out <= (OTHERS => '0');
				               CW_out <= (OTHERS => '0');
				               SSB_out<= (OTHERS => '0');									
				WHEN "001" => 	AM_out <= (OTHERS => '0');
				               FM_out <= input_reg;
				               CW_out <= (OTHERS => '0');
				               SSB_out<= (OTHERS => '0');			
				WHEN "010" =>  AM_out <= (OTHERS => '0');
                           FM_out <= (OTHERS => '0');
                           CW_out <= input_reg;
				               SSB_out<= (OTHERS => '0');
				WHEN OTHERS => AM_out <= (OTHERS => '0');
				               FM_out <= (OTHERS => '0');
				               CW_out <= (OTHERS => '0');
				               SSB_out<= input_reg;									
			END CASE;
		ELSE
			AM_out <= (OTHERS => '0');
			FM_out <= (OTHERS => '0');
			CW_out <= (OTHERS => '0');
			SSB_out<= (OTHERS => '0');
		END IF;			
	END IF;
end process;

input_reg <= Data_in;
end Behavioral;

