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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:49:19 04/07/2012 
-- Design Name: 
-- Module Name:    Output_DEMUX - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Output_DEMUX is
    Port ( clk : in  STD_LOGIC;
           Address : in  STD_LOGIC_VECTOR (2 downto 0);
           En : in  STD_LOGIC;
           AM_in : in  STD_LOGIC_VECTOR (13 downto 0);
           FM_in : in  STD_LOGIC_VECTOR (13 downto 0);
           CW_in : in  STD_LOGIC_VECTOR (13 downto 0);
           SSB_in : in  STD_LOGIC_VECTOR (13 downto 0);
           Data_out : out  STD_LOGIC_VECTOR (13 downto 0));
end Output_DEMUX;

architecture Behavioral of Output_DEMUX is


signal output_reg: STD_LOGIC_VECTOR (13 downto 0) := (OTHERS => '0');

begin

process (clk) begin
	IF rising_edge(clk) THEN
		IF En = '1' THEN
			CASE Address IS
				WHEN "000" => 	output_reg <= AM_in;								
				WHEN "001" => 	output_reg <= FM_in;			
				WHEN "010" =>  output_reg <= CW_in;
				WHEN OTHERS => output_reg <= SSB_in;
   		END CASE;
		ELSE
			output_reg <= (OTHERS => '0');
		END IF;			
	END IF;
end process;

Data_out <= output_reg;


end Behavioral;

