----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:34:02 03/26/2012 
-- Design Name: 
-- Module Name:    switch_source - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity switch_source is
    Port ( 
			  clk : in  STD_LOGIC;
			  button : in  STD_LOGIC;
           harm : in  STD_LOGIC_VECTOR (17 downto 0);
           audio : in  STD_LOGIC_VECTOR (17 downto 0);
           output_sig : out  STD_LOGIC_VECTOR (17 downto 0));
end switch_source;

architecture Behavioral of switch_source is

signal but_sig: STD_LOGIC:= '0';
signal OUT_sig_reg: STD_LOGIC_VECTOR (17 downto 0):= (OTHERS => '0');

begin
process (clk) begin
	IF rising_edge(clk) THEN		
		if but_sig = '1' then
			OUT_sig_reg <= harm;
		else
			OUT_sig_reg <= audio;
		end if;		
	end if;	
end process;

output_sig <= OUT_sig_reg;
but_sig <= button;

end Behavioral;

