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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:27:36 04/25/2012 
-- Design Name: 
-- Module Name:    DDS_Tune_RX - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DDS_Tune_RX is
    Port ( clk : in  STD_LOGIC;
           Address : in  STD_LOGIC_VECTOR (2 downto 0);
           AM_Tune : in  STD_LOGIC_VECTOR (21 downto 0);
           FM_Tune : in  STD_LOGIC_VECTOR (21 downto 0);
           CW_Tune : in  STD_LOGIC_VECTOR (21 downto 0);
           SSB_Tune : in  STD_LOGIC_VECTOR (21 downto 0);
           Tune_Data : out  STD_LOGIC_VECTOR (21 downto 0));
end DDS_Tune_RX;

architecture Behavioral of DDS_Tune_RX is

signal tune_rx_reg: STD_LOGIC_VECTOR (21 downto 0) := (OTHERS => '0');
signal add_reg: STD_LOGIC_VECTOR (2 downto 0) := (OTHERS => '0');

begin

process (clk) begin
	IF rising_edge(clk) THEN
			CASE add_reg IS
				WHEN "000" => 	tune_rx_reg <= AM_Tune;								
				WHEN "001" => 	tune_rx_reg <= FM_Tune;			
				WHEN "010" =>  tune_rx_reg <= CW_Tune;
				WHEN OTHERS=> 	tune_rx_reg <= SSB_Tune;
			END CASE;
	END IF;
end process;

Tune_Data <= tune_rx_reg;
add_reg <= Address;

end Behavioral;

