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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity ClockEnable_gen is
    PORT ( clk_200      : IN  STD_LOGIC;
           clk_EN_100M  : OUT STD_LOGIC;
           clk_EN_50M   : OUT STD_LOGIC;
           clk_EN_10M   : OUT STD_LOGIC;
           clk_EN_5M    : OUT STD_LOGIC;
           clk_EN_1M    : OUT STD_LOGIC;
           clk_EN_500k  : OUT STD_LOGIC;
           clk_EN_100k  : OUT STD_LOGIC;
           clk_EN_50k   : OUT STD_LOGIC;
           clk_EN_10k   : OUT STD_LOGIC;
           clk_EN_5k    : OUT STD_LOGIC;
           clk_EN_1k    : OUT STD_LOGIC);
end ClockEnable_gen;
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architecture Behavioral of ClockEnable_gen is
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  SIGNAL clk_EN_100M_i    : STD_LOGIC := '0';

  SIGNAL cnt_clk_EN_50M   : STD_LOGIC_VECTOR(18 DOWNTO 0) := (OTHERS => '0');
  SIGNAL cnt_clk_EN_10M   : STD_LOGIC_VECTOR(18 DOWNTO 0) := (OTHERS => '0');
  SIGNAL cnt_clk_EN_5M    : STD_LOGIC_VECTOR(18 DOWNTO 0) := (OTHERS => '0');
  SIGNAL cnt_clk_EN_1M    : STD_LOGIC_VECTOR(18 DOWNTO 0) := (OTHERS => '0');
  SIGNAL cnt_clk_EN_500k  : STD_LOGIC_VECTOR(18 DOWNTO 0) := (OTHERS => '0');
  SIGNAL cnt_clk_EN_100k  : STD_LOGIC_VECTOR(18 DOWNTO 0) := (OTHERS => '0');
  SIGNAL cnt_clk_EN_50k   : STD_LOGIC_VECTOR(18 DOWNTO 0) := (OTHERS => '0');
  SIGNAL cnt_clk_EN_10k   : STD_LOGIC_VECTOR(18 DOWNTO 0) := (OTHERS => '0');
  SIGNAL cnt_clk_EN_5k    : STD_LOGIC_VECTOR(18 DOWNTO 0) := (OTHERS => '0');
  SIGNAL cnt_clk_EN_1k    : STD_LOGIC_VECTOR(18 DOWNTO 0) := (OTHERS => '0');
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BEGIN
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  PROCESS(clk_200) BEGIN
    IF rising_edge(clk_200) THEN

      clk_EN_100M_i <= NOT clk_EN_100M_i;

      IF cnt_clk_EN_50M  = CONV_STD_LOGIC_VECTOR(3,19)      THEN  clk_EN_50M  <= '1';  cnt_clk_EN_50M  <= (OTHERS => '0');
                                                            ELSE  clk_EN_50M  <= '0';  cnt_clk_EN_50M  <= cnt_clk_EN_50M + 1;  END IF;

      IF cnt_clk_EN_10M  = CONV_STD_LOGIC_VECTOR(19,19)     THEN  clk_EN_10M  <= '1';  cnt_clk_EN_10M  <= (OTHERS => '0');
                                                            ELSE  clk_EN_10M  <= '0';  cnt_clk_EN_10M  <= cnt_clk_EN_10M + 1;  END IF;

      IF cnt_clk_EN_5M  = CONV_STD_LOGIC_VECTOR(39,19)     THEN  clk_EN_5M   <= '1';  cnt_clk_EN_5M   <= (OTHERS => '0');
                                                            ELSE  clk_EN_5M   <= '0';  cnt_clk_EN_5M   <= cnt_clk_EN_5M + 1;   END IF;

      IF cnt_clk_EN_1M  = CONV_STD_LOGIC_VECTOR(199,19)    THEN  clk_EN_1M   <= '1';  cnt_clk_EN_1M   <= (OTHERS => '0');
                                                            ELSE  clk_EN_1M   <= '0';  cnt_clk_EN_1M   <= cnt_clk_EN_1M + 1;   END IF;

      IF cnt_clk_EN_500k  = CONV_STD_LOGIC_VECTOR(799,19)    THEN  clk_EN_500k <= '1';  cnt_clk_EN_500k <= (OTHERS => '0');
                                                            ELSE  clk_EN_500k <= '0';  cnt_clk_EN_500k <= cnt_clk_EN_500k + 1; END IF;

      IF cnt_clk_EN_100k  = CONV_STD_LOGIC_VECTOR(1999,19)   THEN  clk_EN_100k <= '1';  cnt_clk_EN_100k <= (OTHERS => '0');
                                                            ELSE  clk_EN_100k <= '0';  cnt_clk_EN_100k <= cnt_clk_EN_100k + 1; END IF;

      IF cnt_clk_EN_50k  = CONV_STD_LOGIC_VECTOR(3999,19)   THEN  clk_EN_50k  <= '1';  cnt_clk_EN_50k  <= (OTHERS => '0');
                                                            ELSE  clk_EN_50k  <= '0';  cnt_clk_EN_50k  <= cnt_clk_EN_50k + 1;  END IF;

      IF cnt_clk_EN_10k  = CONV_STD_LOGIC_VECTOR(19999,19)  THEN  clk_EN_10k  <= '1';  cnt_clk_EN_10k  <= (OTHERS => '0');
                                                            ELSE  clk_EN_10k  <= '0';  cnt_clk_EN_10k  <= cnt_clk_EN_10k + 1;  END IF;

      IF cnt_clk_EN_5k  = CONV_STD_LOGIC_VECTOR(39999,19)  THEN  clk_EN_5k   <= '1';  cnt_clk_EN_5k   <= (OTHERS => '0');
                                                            ELSE  clk_EN_5k   <= '0';  cnt_clk_EN_5k   <= cnt_clk_EN_5k + 1;   END IF;

      IF cnt_clk_EN_1k  = CONV_STD_LOGIC_VECTOR(199999,19) THEN  clk_EN_1k   <= '1';  cnt_clk_EN_1k   <= (OTHERS => '0');
                                                            ELSE  clk_EN_1k   <= '0';  cnt_clk_EN_1k   <= cnt_clk_EN_1k + 1;   END IF;

    END IF;
  END PROCESS;

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END Behavioral;
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