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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:15:31 04/07/2012 
-- Design Name: 
-- Module Name:    Input_MUX - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Input_MUX is
    Port ( clk : in  STD_LOGIC;
           Input_data : in  STD_LOGIC_VECTOR (17 downto 0);
			  CW_input: in STD_LOGIC;
           Address : in  STD_LOGIC_VECTOR (2 downto 0);
           En : in  STD_LOGIC;
           AM_mod_out : out  STD_LOGIC_VECTOR (17 downto 0);
           FM_mod_out : out  STD_LOGIC_VECTOR (17 downto 0);
           CW_mod_out : out  STD_LOGIC;
           SSB_mod_out : out  STD_LOGIC_VECTOR (17 downto 0));
end Input_MUX;

architecture Behavioral of Input_MUX is

signal input_reg: STD_LOGIC_VECTOR (17 downto 0) := (OTHERS => '0');
signal cw_reg: STD_LOGIC :=  '0';
 
begin

process (clk) begin
	IF rising_edge(clk) THEN
		IF En = '1' THEN
			CASE Address IS
				WHEN "000" => 	AM_mod_out <= input_reg;  
				               FM_mod_out <= (OTHERS => '0');
				               CW_mod_out <= '0';
				               SSB_mod_out<= (OTHERS => '0');
				WHEN "001" => 	AM_mod_out <= (OTHERS => '0');
				               FM_mod_out <= input_reg;
				               CW_mod_out <= '0';
				               SSB_mod_out<= (OTHERS => '0');			
				WHEN "010" =>  AM_mod_out <= (OTHERS => '0');
                           FM_mod_out <= (OTHERS => '0');
                           CW_mod_out <= cw_reg;
				               SSB_mod_out<= (OTHERS => '0');
				WHEN OTHERS => AM_mod_out <= (OTHERS => '0');
				               FM_mod_out <= (OTHERS => '0');
				               CW_mod_out <= '0';
				               SSB_mod_out<= input_reg;
			END CASE;
		ELSE
			AM_mod_out <= (OTHERS => '0');
			FM_mod_out <= (OTHERS => '0');
			CW_mod_out <=  '0';
			SSB_mod_out<= (OTHERS => '0');
		END IF;			
	END IF;
end process;

input_reg <= Input_data;
cw_reg <= CW_input;

end Behavioral;

