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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:29:00 05/07/2012 
-- Design Name: 
-- Module Name:    Gain_sel - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Gain_sel is
    Port ( clk : in  STD_LOGIC;
           SW_0 : in  STD_LOGIC;
           SW_1 : in  STD_LOGIC;
           Gain : out  STD_LOGIC_VECTOR (1 downto 0));
end Gain_sel;

architecture Behavioral of Gain_sel is

signal sw_state: STD_LOGIC_VECTOR (1 downto 0) := "00";  

begin
process (clk) begin
	if rising_edge(clk) then
		sw_state <= SW_1 & SW_0;	
	end if;
end process;

Gain <= sw_state;

end Behavioral;

