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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:35:05 04/02/2012 
-- Design Name: 
-- Module Name:    DAC_AD9764 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DAC_AD9764 is
    Port ( 
			  clk : in  STD_LOGIC;										-- clock signal for data processing
			  Data_in : in  STD_LOGIC_VECTOR (13 downto 0);		-- data to send
           Data_out : out  STD_LOGIC_VECTOR (13 downto 0);	-- edited data to send to DAC
           Sleep : out  STD_LOGIC);									-- DAC control signal (not used)
end DAC_AD9764;

architecture Behavioral of DAC_AD9764 is

signal Data_reg: STD_LOGIC_VECTOR (13 downto 0) := (OTHERS => '0');

begin


process (clk)

variable dac_data: STD_LOGIC_VECTOR (13 downto 0) := "00000000000000";

begin
	IF rising_edge(clk) THEN
		dac_data := Data_reg;								-- save input data to variable
	
		IF dac_data(13) = '1' THEN 						-- if the number is negative (MSB set)
			dac_data := NOT dac_data;						-- create two's complement of number
			dac_data := "01111111111111" - dac_data; 	-- substract the number from center value
		ELSE	
			dac_data := dac_data + "10000000000000"; 	-- if positive add center value to the number
		END IF;
		
		Data_out <= dac_data;								-- write data to output
	END IF;	
end process;	

Data_reg <= Data_in;			-- read input data
Sleep <= '0';					-- DAC is always on

end Behavioral;

