----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:19:36 03/24/2012 
-- Design Name: 
-- Module Name:    LCD_data_control - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LCD_data_control is
    Port ( busy_flag : in  STD_LOGIC;										-- busy flag from LCD driver
           clk : in  STD_LOGIC;												-- clock signal			
			  button_up : in  STD_LOGIC;										-- button input from navigation switch
			  button_down : in  STD_LOGIC;									-- button input from navigation switch
			  button_left : in  STD_LOGIC;									-- button input from navigation switch
			  button_right : in  STD_LOGIC;									-- button input from navigation switch
			  MUX_addr: out STD_LOGIC_VECTOR (2 downto 0);				-- output for MUX and DEMUX address
			  AM_out: out STD_LOGIC_VECTOR (7 downto 0);					-- AM parameter output
			  FM_out: out STD_LOGIC_VECTOR (7 downto 0);					-- FM parameter output
			  CW_out: out STD_LOGIC_VECTOR (21 downto 0);				-- CW and test signal parameter output
			  SSB_out: out STD_LOGIC;											-- SSB parameter ottput
           LCD_data_out : out  STD_LOGIC_VECTOR (7 downto 0);		-- data for LCD driver
			  Freq_out: out STD_LOGIC_VECTOR (8 downto 0);				-- main DDS parameter output
           LCD_write_enable : out  STD_LOGIC);							-- control signal for LCD driver		
end LCD_data_control;

architecture Behavioral of LCD_data_control is
  
  type modulation is (AM, FM, CW, SSB);
  type position is (modul, param, frequency);
  signal mod_state : modulation := AM; 
  signal pos_state : position := modul;
  signal param_state:	integer range 0 to 8191 := 30;
  signal step_state:	integer range 0 to 1000 := 2;
  signal param_min:	integer range 0 to 2000 := 0;
  signal param_max:	integer range 0 to 5000 := 95;
  
  signal AM_param : integer range 0 to 100 := 30;
  signal FM_param : integer range 0 to 200 := 10;
  signal CW_param: integer range 0 to 5000 := 1000;
  signal SSB_param:	STD_LOGIC := '0';
  signal freq_set: integer range 0 to 300 := 30;
  signal address: STD_LOGIC_VECTOR (2 downto 0) := "000";  
  constant step : integer range 0 to 1 := 1;
  
  constant FM_min: integer range 0 to 10 := 10;
  constant AM_min: integer range 0 to 1 := 0;
  constant CW_min: integer range 0 to 200 := 200;
  constant SSB_min: integer range 0 to 1 := 0;
  
  constant FM_max: integer range 0 to 200 := 200;
  constant AM_max: integer range 0 to 100 := 95;
  constant CW_max: integer range 0 to 5000 := 3000;
  constant SSB_max: integer range 0 to 1 := 1;
  
  constant FM_step: integer range 0 to 10 := 5;
  constant AM_step: integer range 0 to 5 := 2;
  constant CW_step: integer range 0 to 100 := 100;
  constant SSB_step: integer range 0 to 1 := 1;  
  
  -- character array for LCD display
  signal clear_scr : STD_LOGIC_VECTOR (7 downto 0) := X"00";	
  signal char_1 : STD_LOGIC_VECTOR (7 downto 0) := X"41"; 
  signal char_2 : STD_LOGIC_VECTOR (7 downto 0) := X"4D"; 
  signal char_3 : STD_LOGIC_VECTOR (7 downto 0) := X"20"; 
  signal char_4 : STD_LOGIC_VECTOR (7 downto 0) := X"2A";
  signal char_5 : STD_LOGIC_VECTOR (7 downto 0) := X"20";
  signal char_6 : STD_LOGIC_VECTOR (7 downto 0) := X"20"; 
  signal char_7 : STD_LOGIC_VECTOR (7 downto 0) := X"20"; 
  signal char_8 : STD_LOGIC_VECTOR (7 downto 0) := X"20"; 
  signal char_9 : STD_LOGIC_VECTOR (7 downto 0) := X"20";
  signal char_10: STD_LOGIC_VECTOR (7 downto 0) := X"20";
  signal char_11: STD_LOGIC_VECTOR (7 downto 0) := X"35"; 
  signal char_12: STD_LOGIC_VECTOR (7 downto 0) := X"30"; 
  signal char_13: STD_LOGIC_VECTOR (7 downto 0) := X"20"; 
  signal char_14: STD_LOGIC_VECTOR (7 downto 0) := X"25";
  signal char_15: STD_LOGIC_VECTOR (7 downto 0) := X"20";
  signal char_16: STD_LOGIC_VECTOR (7 downto 0) := X"20"; 
  signal char_17: STD_LOGIC_VECTOR (7 downto 0) := X"46"; 
  signal char_18: STD_LOGIC_VECTOR (7 downto 0) := X"72"; 
  signal char_19: STD_LOGIC_VECTOR (7 downto 0) := X"65";
  signal char_20: STD_LOGIC_VECTOR (7 downto 0) := X"71";
  signal char_21: STD_LOGIC_VECTOR (7 downto 0) := X"3A"; 
  signal char_22: STD_LOGIC_VECTOR (7 downto 0) := X"20";
  signal char_23: STD_LOGIC_VECTOR (7 downto 0) := X"20";
  signal char_24: STD_LOGIC_VECTOR (7 downto 0) := X"20"; 
  signal char_25: STD_LOGIC_VECTOR (7 downto 0) := X"20"; 
  signal char_26: STD_LOGIC_VECTOR (7 downto 0) := X"33"; 
  signal char_27: STD_LOGIC_VECTOR (7 downto 0) := X"2E";
  signal char_28: STD_LOGIC_VECTOR (7 downto 0) := X"30";
  signal char_29: STD_LOGIC_VECTOR (7 downto 0) := X"20"; 
  signal char_30: STD_LOGIC_VECTOR (7 downto 0) := X"4D"; 
  signal char_31: STD_LOGIC_VECTOR (7 downto 0) := X"48"; 
  signal char_32: STD_LOGIC_VECTOR (7 downto 0) := X"7A";  
 
  signal actual_char_out  : STD_LOGIC_VECTOR (7 downto 0) := clear_scr; 
  signal pressed_up: STD_LOGIC := '0';
  signal pressed_down: STD_LOGIC := '0';
  signal pressed_left: STD_LOGIC := '0';
  signal pressed_right: STD_LOGIC := '0';  
  signal refresh_up_down: STD_LOGIC := '0';
  signal refresh_right_left: STD_LOGIC := '1';
  signal refresh_value: STD_LOGIC := '0'; 
  signal index_char: integer range 0 to 33 := 1 ;
  signal refresh: STD_LOGIC := '0';
  signal lcd_refresh: STD_LOGIC := '1'; 
  signal lcd_done: STD_LOGIC := '0';
  signal lcd_sent: STD_LOGIC := '1';
  signal param_vect: STD_LOGIC_VECTOR (15 downto 0) := X"0000";
  signal freq_vect: STD_LOGIC_VECTOR (15 downto 0) := X"0000";
  signal BCD_out: STD_LOGIC_VECTOR (15 downto 0) := X"0000";
  signal BCD_out_f: STD_LOGIC_VECTOR (15 downto 0) := X"0000"; 

-- process for data transmission to LCD driver
begin
process (clk) begin
	IF rising_edge(clk) THEN	
		IF lcd_refresh = '1' THEN
			lcd_done <= '0';
		END IF;
		
		IF busy_flag = '0' AND lcd_done= '0' THEN
			LCD_data_out <= actual_char_out;		
			LCD_write_enable <= '1';
			lcd_sent <= '1';							
		ELSIF busy_flag = '1' AND lcd_sent = '1'  THEN
			LCD_write_enable <= '0';
			lcd_sent <= '0';
			IF index_char<32 THEN
				index_char <= index_char + 1;
			ELSE 
				index_char <= 1;
				lcd_done <= '1';
			END IF;	
		END IF;		
	END IF;
end process;

-- process selects data to transmit (state machine for choosing actual character to transmit)
process (clk) begin
	IF rising_edge(clk) THEN		
		CASE index_char IS
			WHEN 0 => actual_char_out <= clear_scr;
			WHEN 1 => actual_char_out <= char_1;
			WHEN 2 => actual_char_out <= char_2;
			WHEN 3 => actual_char_out <= char_3;
			WHEN 4 => actual_char_out <= char_4;
			WHEN 5 => actual_char_out <= char_5;
			WHEN 6 => actual_char_out <= char_6;
			WHEN 7 => actual_char_out <= char_7;
			WHEN 8 => actual_char_out <= char_8;
			WHEN 9 => actual_char_out <= char_9;
			WHEN 10 => actual_char_out <= char_10;
			WHEN 11 => actual_char_out <= char_11;
			WHEN 12 => actual_char_out <= char_12;
			WHEN 13 => actual_char_out <= char_13;
			WHEN 14 => actual_char_out <= char_14;
			WHEN 15 => actual_char_out <= char_15;
			WHEN 16 => actual_char_out <= char_16;
			WHEN 17 => actual_char_out <= char_17;
			WHEN 18 => actual_char_out <= char_18;
			WHEN 19 => actual_char_out <= char_19;
			WHEN 20 => actual_char_out <= char_20;
			WHEN 21 => actual_char_out <= char_21;
			WHEN 22 => actual_char_out <= char_22;
			WHEN 23 => actual_char_out <= char_23;
			WHEN 24 => actual_char_out <= char_24;
			WHEN 25 => actual_char_out <= char_25;
			WHEN 26 => actual_char_out <= char_26;
			WHEN 27 => actual_char_out <= char_27;
			WHEN 28 => actual_char_out <= char_28;
			WHEN 29 => actual_char_out <= char_29;
			WHEN 30 => actual_char_out <= char_30;
			WHEN 31 => actual_char_out <= char_31;
			WHEN 32 => actual_char_out <= char_32;			
			WHEN OTHERS  => actual_char_out <= char_1;
			END CASE;
	END IF;
end process;	

-- state machine that controls output data (for LCD and tranceiver) according to the input from buttons LEFT and RIGHT
process (clk) begin
	IF rising_edge(clk) THEN
		if refresh_value = '1' then refresh_right_left <= '0'; end if;
	
		IF button_right = '1' THEN
			pressed_right <= '1';
		ELSIF pressed_right = '1' THEN
			pressed_right <= '0';			
			
			CASE pos_state IS
				WHEN modul => 
					CASE mod_state IS
						WHEN AM =>	mod_state <= FM;
										param_state <= FM_param;
										step_state <= FM_step;
										param_min <= FM_min;
										param_max <= FM_max;
										address <= "001";
						WHEN FM =>  mod_state <= CW;
										param_state <= CW_param;
										step_state <= CW_step;
										param_min <= CW_min;
										param_max <= CW_max;
										address <= "010";										
						WHEN CW =>  mod_state <= SSB;
										if SSB_param = '0' then param_state <= 0; else param_state <= 1; end if;
										step_state <= SSB_step;
										param_min <= SSB_min;
										param_max <= SSB_max;
										address <= "011";
						WHEN OTHERS => mod_state <= AM;
										param_state <= AM_param;
										step_state <= AM_step;
										param_min <= AM_min;
										param_max <= AM_max;
										address <= "000";
					END CASE;	
					
					
				WHEN param => IF param_state < param_max THEN param_state <= param_state + step_state; END IF;								  
								 
			   WHEN OTHERS => IF freq_set < 300 THEN freq_set <= freq_set + 1;  END IF;
			END CASE;
			refresh_right_left <= '1';
			
			
		ELSIF button_left = '1' THEN
			pressed_left <= '1';
			
		ELSIF pressed_left = '1' THEN
			pressed_left <= '0';
			
			CASE pos_state IS
				WHEN modul => 
					CASE mod_state IS
						WHEN AM =>	mod_state <= SSB;
										if SSB_param = '0' then param_state <= 0; else param_state <= 1; end if;
										step_state <= SSB_step;
										param_min <= SSB_min;
										param_max <= SSB_max;
										address <= "011";
						WHEN FM =>  mod_state <= AM;
										param_state <= AM_param;
										step_state <= AM_step;
										param_min <= AM_min;
										param_max <= AM_max;	
										address <= "000";										
						WHEN CW =>  mod_state <= FM;
										param_state <= FM_param;
										step_state <= FM_step;
										param_min <= FM_min;
										param_max <= FM_max;
										address <= "001";
						WHEN OTHERS => mod_state <= CW;
										param_state <= CW_param;
										step_state <= CW_step;
										param_min <= CW_min;
										param_max <= CW_max;
										address <= "010";
					END CASE;				
						
						
				WHEN param => IF param_state > param_min THEN param_state <= param_state - step_state;  END IF;		

			   WHEN OTHERS => IF freq_set > 30 THEN freq_set <= freq_set - 1;  END IF;
			END CASE;
			refresh_right_left <= '1';
			
		END IF;	
	END IF;
end process;

-- state machine that controls output data (for LCD and tranceiver) according to the input from buttons UP and DOWN
process (clk) begin
	IF rising_edge(clk) THEN
	
		if lcd_refresh = '1' then refresh_up_down <= '0'; end if;
	
		IF button_up = '1' THEN
			pressed_up <= '1';
		ELSIF pressed_up = '1' THEN
			pressed_up <= '0';
			refresh_up_down <= '1';
			CASE pos_state IS
				WHEN modul => pos_state <= frequency;					
				WHEN param => pos_state <= modul;					
			   WHEN OTHERS => pos_state <= param;
			END CASE;
		END IF;
		
		IF button_down = '1' THEN
			pressed_down <= '1';
		ELSIF pressed_down = '1' THEN
			pressed_down <= '0';
			refresh_up_down <= '1';
			CASE pos_state IS
				WHEN modul => pos_state <= param;					
				WHEN param => pos_state <= frequency;					
			   WHEN OTHERS => pos_state <= modul;
			END CASE;
		END IF;	
	END IF;
end process;


-- process for refreshing of parameters values
process(clk) begin
	IF rising_edge(clk) THEN
		IF lcd_refresh = '1' THEN refresh_value <= '0'; END IF;
	
		IF refresh_right_left = '1' THEN
			refresh_value <= '1';
			CASE mod_state IS
				WHEN AM =>	AM_param <= param_state;
				WHEN FM =>  FM_param <= param_state;										
				WHEN CW =>  CW_param <= param_state;
				WHEN OTHERS  =>   if param_state = 0 then SSB_param <= '0';
										else SSB_param <= '1'; end if; 
			END CASE;
			
			param_vect <= CONV_STD_LOGIC_VECTOR(param_state,16);
			freq_vect <= CONV_STD_LOGIC_VECTOR(freq_set,16);			
		END IF;
	END IF;
end process;	


-- process for binary to BCD coversion, starts LCD display refresh
process (clk)

variable b1: STD_LOGIC_VECTOR (3 downto 0) := X"0";
variable b2: STD_LOGIC_VECTOR (3 downto 0) := X"0";
variable b3: STD_LOGIC_VECTOR (3 downto 0) := X"0";
variable b4: STD_LOGIC_VECTOR (3 downto 0) := X"0";

begin
	IF rising_edge(clk) THEN
		IF lcd_done = '0' THEN lcd_refresh <= '0'; END IF;
		
		IF refresh_value = '1' OR refresh_up_down = '1' THEN
			IF lcd_done = '1' THEN
				lcd_refresh <= '1';

				b4 := X"0";
				b3	:= X"0";
				b2 := X"0";
				b1 := X"0";

				for i in 0 to 15 loop
					if b1> X"4" then b1 := b1 + X"3"; end if;
					if b2> X"4" then b2 := b2 + X"3"; end if;
					if b3> X"4" then b3 := b3 + X"3"; end if;
					if b4> X"4" then b4 := b4 + X"3"; end if;
					
					b4 := b4(2 downto 0) & b3(3);
					b3	:= b3(2 downto 0) & b2(3);
					b2 := b2(2 downto 0) & b1(3);
					b1 := b1(2 downto 0) & param_vect(15-i);
				end loop; 

				BCD_out <= b4 & b3 & b2 & b1;
				
				CASE pos_state IS
					WHEN modul => char_4 <= X"2A"; char_8<= X"20"; char_22 <= X"20";
					WHEN param => char_4 <= X"20"; char_8<= X"2A"; char_22 <= X"20";
					WHEN OTHERS => char_4 <= X"20"; char_8<= X"20"; char_22 <= X"2A";
				END CASE;	
				
				CASE mod_state IS
						WHEN AM =>	char_1 <= X"41";char_2 <= X"4D"; char_3 <= X"20";
										char_14 <= X"25";char_15 <= X"20";char_16 <= X"20";

						WHEN FM =>  char_1 <= X"46";char_2 <= X"4D"; char_3 <= X"20";
										char_14 <= X"6B";char_15 <= X"48";char_16 <= X"7A";
									
						WHEN CW =>  char_1 <= X"43";char_2 <= X"57"; char_3 <= X"20";
										char_14 <= X"48";char_15 <= X"7A";char_16 <= X"20";

						WHEN SSB => char_1 <= X"53";char_2 <= X"53"; char_3 <= X"42";
										char_14 <= X"20";char_15 <= X"20";char_16 <= X"20";
				END CASE;
				
				IF BCD_out(15 downto 12) = X"0" THEN char_9 <= X"20"; 
				ELSE
					CASE BCD_out(15 downto 12) IS
							WHEN X"0" =>	char_9 <= X"30";
							WHEN X"1" =>   char_9 <= X"31";									
							WHEN X"2" =>   char_9 <= X"32";
							WHEN X"3" =>   char_9 <= X"33";
							WHEN X"4" =>   char_9 <= X"34";
							WHEN X"5" =>	char_9 <= X"35";
							WHEN X"6" =>   char_9 <= X"36";									
							WHEN X"7" =>   char_9 <= X"37";
							WHEN X"8" =>   char_9 <= X"38";
							WHEN OTHERS =>   char_9 <= X"39";
					END CASE;
				END IF;
				
				IF BCD_out(15 downto 8) = X"00" THEN char_10 <= X"20"; 
				ELSE
					CASE BCD_out(11 downto 8) IS
							WHEN X"0" =>	char_10 <= X"30";
							WHEN X"1" =>   char_10 <= X"31";									
							WHEN X"2" =>   char_10 <= X"32";
							WHEN X"3" =>   char_10 <= X"33";
							WHEN X"4" =>   char_10 <= X"34";
							WHEN X"5" =>	char_10 <= X"35";
							WHEN X"6" =>   char_10 <= X"36";									
							WHEN X"7" =>   char_10 <= X"37";
							WHEN X"8" =>   char_10 <= X"38";
							WHEN OTHERS =>   char_10 <= X"39";
					END CASE;
				END IF;	

				IF BCD_out(15 downto 4) = X"000" THEN char_11 <= X"20"; 
				ELSE
					CASE BCD_out(7 downto 4) IS
							WHEN X"0" =>	char_11 <= X"30";
							WHEN X"1" =>   char_11 <= X"31";									
							WHEN X"2" =>   char_11 <= X"32";
							WHEN X"3" =>   char_11 <= X"33";
							WHEN X"4" =>   char_11 <= X"34";
							WHEN X"5" =>	char_11 <= X"35";
							WHEN X"6" =>   char_11 <= X"36";									
							WHEN X"7" =>   char_11 <= X"37";
							WHEN X"8" =>   char_11 <= X"38";
							WHEN OTHERS =>   char_11 <= X"39";
					END CASE;				
				END IF;

				CASE BCD_out(3 downto 0) IS
						WHEN X"0" =>	char_12 <= X"30";
						WHEN X"1" =>   char_12 <= X"31";									
						WHEN X"2" =>   char_12 <= X"32";
						WHEN X"3" =>   char_12 <= X"33";
						WHEN X"4" =>   char_12 <= X"34";
						WHEN X"5" =>	char_12 <= X"35";
						WHEN X"6" =>   char_12 <= X"36";									
						WHEN X"7" =>   char_12 <= X"37";
						WHEN X"8" =>   char_12 <= X"38";
						WHEN OTHERS =>   char_12 <= X"39";
				END CASE;
				
				IF mod_state = SSB THEN 
					char_11 <= X"53"; char_12 <= X"42";
					
					IF param_vect = 1 THEN char_10 <= X"55"; 
					ELSE char_10 <= X"4C"; 
					END IF;	
				
				END IF;
				
				BCD_out_f <= X"0000";
				b4 := X"0";
				b3	:= X"0";
				b2 := X"0";
				b1 := X"0";
				
				for i in 0 to 15 loop
					if b1> X"4" then b1 := b1 + X"3"; end if;
					if b2> X"4" then b2 := b2 + X"3"; end if;
					if b3> X"4" then b3 := b3 + X"3"; end if;
					if b4> X"4" then b4 := b4 + X"3"; end if;
					
					b4 := b4(2 downto 0) & b3(3);
					b3	:= b3(2 downto 0) & b2(3);
					b2 := b2(2 downto 0) & b1(3);
					b1 := b1(2 downto 0) & freq_vect(15-i);
				end loop; 

				BCD_out_f <= b4 & b3 & b2 & b1;
				
				IF BCD_out_f(15 downto 12) = X"0" THEN char_24 <= X"20"; 
				ELSE
					CASE BCD_out_f(15 downto 12) IS
							WHEN X"0" =>	char_24 <= X"30";
							WHEN X"1" =>   char_24 <= X"31";									
							WHEN X"2" =>   char_24 <= X"32";
							WHEN X"3" =>   char_24 <= X"33";
							WHEN X"4" =>   char_24 <= X"34";
							WHEN X"5" =>	char_24 <= X"35";
							WHEN X"6" =>   char_24 <= X"36";									
							WHEN X"7" =>   char_24 <= X"37";
							WHEN X"8" =>   char_24 <= X"38";
							WHEN OTHERS =>   char_24 <= X"39";
					END CASE;
				END IF;
				
				IF BCD_out_f(15 downto 8) = X"00" THEN char_25 <= X"20"; 
				ELSE
					CASE BCD_out_f(11 downto 8) IS
							WHEN X"0" =>	char_25 <= X"30";
							WHEN X"1" =>   char_25 <= X"31";									
							WHEN X"2" =>   char_25 <= X"32";
							WHEN X"3" =>   char_25 <= X"33";
							WHEN X"4" =>   char_25 <= X"34";
							WHEN X"5" =>	char_25 <= X"35";
							WHEN X"6" =>   char_25 <= X"36";									
							WHEN X"7" =>   char_25 <= X"37";
							WHEN X"8" =>   char_25 <= X"38";
							WHEN OTHERS =>   char_25 <= X"39";
					END CASE;
				END IF;	

				CASE BCD_out_f(7 downto 4) IS
							WHEN X"0" =>	char_26 <= X"30";
							WHEN X"1" =>   char_26 <= X"31";									
							WHEN X"2" =>   char_26 <= X"32";
							WHEN X"3" =>   char_26 <= X"33";
							WHEN X"4" =>   char_26 <= X"34";
							WHEN X"5" =>	char_26 <= X"35";
							WHEN X"6" =>   char_26 <= X"36";									
							WHEN X"7" =>   char_26 <= X"37";
							WHEN X"8" =>   char_26 <= X"38";
							WHEN OTHERS =>   char_26 <= X"39";
				END CASE;
				
				char_27 <= X"2E";

				CASE BCD_out_f(3 downto 0) IS
						WHEN X"0" =>	char_28 <= X"30";
						WHEN X"1" =>   char_28 <= X"31";									
						WHEN X"2" =>   char_28 <= X"32";
						WHEN X"3" =>   char_28 <= X"33";
						WHEN X"4" =>   char_28 <= X"34";
						WHEN X"5" =>	char_28 <= X"35";
						WHEN X"6" =>   char_28 <= X"36";									
						WHEN X"7" =>   char_28 <= X"37";
						WHEN X"8" =>   char_28 <= X"38";
						WHEN OTHERS =>   char_28 <= X"39";
				END CASE;
				 
				char_30 <= X"4D"; char_31 <= X"48"; char_32 <= X"7A";
				
			END IF;		
		END IF;	
	END IF;
end process;

-- write data to output
AM_out 	<= CONV_STD_LOGIC_VECTOR(AM_param,8);
FM_out 	<= CONV_STD_LOGIC_VECTOR(FM_param,8);
CW_out 	<= CONV_STD_LOGIC_VECTOR(CW_param,22);
SSB_out 	<= SSB_param ;
Freq_out	<= CONV_STD_LOGIC_VECTOR(freq_set,8);
Mux_addr	<= address;

end Behavioral;

