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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:08:38 04/25/2012 
-- Design Name: 
-- Module Name:    DDS_Tune_RX_TX - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DDS_Tune_RX_TX is
    Port ( clk : in  STD_LOGIC;
           RX_TX : in  STD_LOGIC;
           RX_Tune_data : in  STD_LOGIC_VECTOR (21 downto 0);
           TX_Tune_data : in  STD_LOGIC_VECTOR (21 downto 0);
           Tune_data : out  STD_LOGIC_VECTOR (21 downto 0));
end DDS_Tune_RX_TX;

architecture Behavioral of DDS_Tune_RX_TX is

signal RX_TX_reg: STD_LOGIC := '0';
signal tune_out_reg:  STD_LOGIC_VECTOR (21 downto 0) := (OTHERS => '0'); 

begin

process (clk) begin
	IF rising_edge(clk) THEN
		IF RX_TX_reg = '1' THEN	tune_out_reg <= TX_Tune_data;
		ELSE	tune_out_reg <= RX_Tune_data;
		END IF;
	END IF;	
end process;

RX_TX_reg <= RX_TX;
Tune_data <= tune_out_reg;

end Behavioral;

