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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:37:16 04/25/2012 
-- Design Name: 
-- Module Name:    RX_TX_Enable - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RX_TX_Enable is
    Port ( clk : in  STD_LOGIC;
           RX_TX_SW : in  STD_LOGIC;
           RX_EN : out  STD_LOGIC;
           TX_EN : out  STD_LOGIC;
           RX_TX_EN : out  STD_LOGIC);
end RX_TX_Enable;

architecture Behavioral of RX_TX_Enable is

signal en_switch: STD_LOGIC := '0';

begin
process (clk) begin
	IF rising_edge(clk) THEN
		IF	en_switch = '1' THEN	RX_EN <= '0'; TX_EN <= '1'; RX_TX_EN <= '1';
		ELSE	RX_EN <= '1'; TX_EN <= '0'; RX_TX_EN <= '0';
		END IF;		
	END IF;
end process;

en_switch <= RX_TX_SW;

end Behavioral;

