# -----------------------------------------------------------------------------
# Author            : Samuel PETRAS <samuel.petras2@onsemi.com>
# -----------------------------------------------------------------------------
# Description       : MTRD - Makefile
# -----------------------------------------------------------------------------

ROOT            := ../hdl
DIR_RTL         := $(ROOT)/rtl
DIR_MODEL       := $(ROOT)/model
DIR_MODEL_EE    := $(DIR_MODEL)/eeprom
DIR_MODEL_REG   := $(DIR_MODEL)/register
DIR_AGENT       := $(ROOT)/agent
DIR_ENV         := $(ROOT)/env
DIR_TEST        := $(ROOT)/test
DIR_TB          := $(ROOT)/tb
DIR_UVM         := $(QUESTA_ROOT)/verilog_src/uvm-1.1d/src

WORK            ?= work
WORK_VELOCE     ?= work_veloce

TIMESCALE       ?= 1ns/1ns

VLOG_OPT        := -incr -sv -timescale $(TIMESCALE)
VELANALYZE_OPT  := -sv -work $(WORK_VELOCE) -timescale $(TIMESCALE)
VELCOMP_OPT     := -verbose -top hdl_top
VELHVL_OPT      := -verbose -sim veloce -work $(WORK_VELOCE)

TEST            ?= mtrd_example_test
VERBOSITY       ?= UVM_MEDIUM

LOGNAME         := log_$(TEST)
LOGNAME_VELOCE  := log_veloce_$(TEST)
FILE_WLF        := wave_$(TEST).wlf

PLUSARGS        := +UVM_TESTNAME="$(TEST)" \
                   +UVM_VERBOSITY="$(VERBOSITY)"

SRC_RTL = \
	                                 $(DIR_RTL)/mtrd_defs_pkg.sv \
	                                 $(DIR_RTL)/clock_gater.sv \
	                                 $(DIR_RTL)/mtrd_clk_gen.sv \
	                                 $(DIR_RTL)/mtrd_rst_gen.sv \
	                                 $(DIR_RTL)/mtrd_watchdog.sv \
	                                 $(DIR_RTL)/crc_serial.sv \
	                                 $(DIR_RTL)/mtrd_crc_ctrl.sv \
	                                 $(DIR_RTL)/mtrd_ee_ctrl.sv \
	                                 $(DIR_RTL)/debouncer.sv \
	                                 $(DIR_RTL)/mtrd_debouncer_top.sv \
	                                 $(DIR_RTL)/resynch.sv \
	                                 $(DIR_RTL)/mtrd_resynch_top.sv \
	                                 $(DIR_RTL)/status_flag_cbw.sv \
	                                 $(DIR_RTL)/mtrd_spi_top.sv \
	                                 $(DIR_RTL)/mtrd_spi_ctrl.sv \
	                                 $(DIR_RTL)/mtrd_spi_regs.sv \
	                                 $(DIR_RTL)/adc_sar_ctrl.sv \
	                                 $(DIR_RTL)/mtrd_adc_meas_ctrl.sv \
	                                 $(DIR_RTL)/mtrd_hb_dcnt.sv \
	                                 $(DIR_RTL)/mtrd_hb_ctrl.sv \
	                                 $(DIR_RTL)/mtrd_main_fsm.sv \
	                                 $(DIR_RTL)/mtrd_dig_core.sv \
	                                 $(DIR_RTL)/mtrd_tst_mux.sv \
	                                 $(DIR_RTL)/mtrd_tst_clk_mux.sv \
	                                 $(DIR_RTL)/mtrd_tst_rst_mux.sv \
	                                 $(DIR_RTL)/mtrd_tst_ctrl.sv \
	                                 $(DIR_RTL)/mtrd_dig_top.sv

SRC_UVM_HDL = \
	                                 $(DIR_MODEL_EE)/std_mem_acc_bfm.sv \
	                                 $(DIR_AGENT)/int_mon/mtrd_int_mon_bfm.sv \
	                                 $(DIR_AGENT)/osc/mtrd_osc_monitor_bfm.sv \
	                                 $(DIR_AGENT)/osc/mtrd_osc_driver_bfm.sv \
	                                 $(DIR_AGENT)/rst/mtrd_rst_monitor_bfm.sv \
	                                 $(DIR_AGENT)/rst/mtrd_rst_driver_bfm.sv \
	                                 $(DIR_AGENT)/disc_io/mtrd_disc_io_monitor_bfm.sv \
	                                 $(DIR_AGENT)/disc_io/mtrd_disc_io_driver_bfm.sv \
	                                 $(DIR_AGENT)/hb/mtrd_hb_monitor_bfm.sv \
	                                 $(DIR_AGENT)/hb/mtrd_hb_driver_bfm.sv \
	                                 $(DIR_AGENT)/spi/mtrd_spi_monitor_bfm.sv \
	                                 $(DIR_AGENT)/spi/mtrd_spi_driver_bfm.sv \
	                                 $(DIR_AGENT)/sar/mtrd_sar_monitor_bfm.sv \
	                                 $(DIR_AGENT)/sar/mtrd_sar_driver_bfm.sv \
	+incdir+$(DIR_RTL)               $(DIR_TB)/hdl_top.sv

SRC_UVM_HVL = \
	+incdir+$(DIR_MODEL_REG)         $(DIR_MODEL_REG)/mtrd_spi_vreguvm_pkg.sv \
	+incdir+$(DIR_MODEL_REG)         $(DIR_MODEL_REG)/mtrd_regmodel_pkg.sv \
	+incdir+$(DIR_ENV)/hb            $(DIR_ENV)/hb/mtrd_hb_env_pkg.sv \
	+incdir+$(DIR_ENV)/spi           $(DIR_ENV)/spi/mtrd_spi_env_pkg.sv \
	+incdir+$(DIR_ENV)/sar           $(DIR_ENV)/sar/mtrd_sar_env_pkg.sv \
                                   $(DIR_TEST)/mtrd_test_pkg.sv \
	+incdir+$(DIR_ENV)/top           $(DIR_ENV)/top/mtrd_scb_pkg.sv \
	+incdir+$(DIR_ENV)/top           $(DIR_ENV)/top/mtrd_top_env_pkg.sv \
	+incdir+$(DIR_TEST)              $(DIR_TEST)/mtrd_test_lib_pkg.sv


SRC_SHARED_PKG = \
	                                 $(DIR_TB)/mtrd_tb_pkg.sv \
	+incdir+$(DIR_MODEL_EE)          $(DIR_MODEL_EE)/std_mem_acc_pkg.sv \
	+incdir+$(DIR_AGENT)/int_mon     $(DIR_AGENT)/int_mon/mtrd_int_mon_pkg.sv \
	+incdir+$(DIR_AGENT)/osc         $(DIR_AGENT)/osc/mtrd_osc_agent_pkg.sv \
	+incdir+$(DIR_AGENT)/rst         $(DIR_AGENT)/rst/mtrd_rst_agent_pkg.sv \
	+incdir+$(DIR_AGENT)/disc_io     $(DIR_AGENT)/disc_io/mtrd_disc_io_agent_pkg.sv \
	+incdir+$(DIR_AGENT)/hb          $(DIR_AGENT)/hb/mtrd_hb_agent_pkg.sv \
	+incdir+$(DIR_AGENT)/spi         $(DIR_AGENT)/spi/mtrd_spi_agent_pkg.sv \
	+incdir+$(DIR_AGENT)/sar         $(DIR_AGENT)/sar/mtrd_sar_agent_pkg.sv

all: build run
all_veloce: build_veloce run_veloce

build:
	vlib $(WORK)
	vlog $(VLOG_OPT) $(DIR_MODEL_EE)/ee_core.veloce.sv
	vlog $(VLOG_OPT) $(SRC_RTL)
	vlog $(VLOG_OPT) $(SRC_SHARED_PKG)
	vlog $(VLOG_OPT) $(SRC_UVM_HVL)
	vlog $(VLOG_OPT) $(SRC_UVM_HDL)
	vlog $(VLOG_OPT) $(DIR_TB)/hvl_top.sv

run:
	vsim -work $(WORK) -c -l $(LOGNAME) -do "run -all" hvl_top hdl_top $(PLUSARGS)

wave:
	vsim -work $(WORK) -voptargs="+acc" -wlf $(FILE_WLF) -l $(LOGNAME) -do "log -r /*;run -all" hvl_top hdl_top $(PLUSARGS)

build_veloce:
	vellib $(WORK_VELOCE)
	velmap $(WORK_VELOCE) ./$(WORK_VELOCE)
	velanalyze $(VELANALYZE_OPT) $(DIR_MODEL_EE)/ee_core.veloce.sv
	velanalyze $(VELANALYZE_OPT) $(SRC_RTL)
	vlog $(VLOG_OPT) -work $(WORK_VELOCE) -tbxhvllint $(SRC_SHARED_PKG)
	vlog $(VLOG_OPT) -work $(WORK_VELOCE) -tbxhvllint $(SRC_UVM_HVL)
	velanalyze $(VELANALYZE_OPT) -extract_hvl_info +incdir+$(DIR_UVM) $(DIR_UVM)/uvm_pkg.sv -verbose
	velanalyze $(VELANALYZE_OPT) -extract_hvl_info +incdir+$(DIR_UVM) $(SRC_SHARED_PKG) -verbose
	velanalyze $(VELANALYZE_OPT) -extract_hvl_info +incdir+$(DIR_UVM) $(SRC_UVM_HVL) -verbose
	velanalyze $(VELANALYZE_OPT) $(SRC_UVM_HDL)
	vlog $(VLOG_OPT) -work $(WORK_VELOCE) -tbxhvllint $(DIR_TB)/hvl_top.sv
	velcomp $(VELCOMP_OPT)
	velhvl $(VELHVL_OPT)

run_veloce:
	vsim -work $(WORK_VELOCE) -c -l $(LOGNAME_VELOCE) -do "run -all" hvl_top hdl_top $(PLUSARGS)

clean:
	rm -rf $(WORK) $(WORK_VELOCE) transcript log* *.wlf vsim_stacktrace.vstf vish_stacktrace.vstf veloce.map veloce.med veloce.log veloce.wave tbxbindings.h modelsim.ini velrunopts.ini make.out


# =============================================================================
#                                                                   End-Of-File
# =============================================================================
