`timescale 1 ns/1 ps
// testbench - verification top module
import test_pkg::*;

module FFT_top_testbench ();

    t_DATA   DATA_out;       // output from FFT_top - serial data
    t_DATA   DATA_in;        // input to FFT_top - serial data
    logic    clk;            // main clock domain, used for counting FFT
    logic    clk_data_en;    // drives DATA_in sending, active one clk period
    logic    rst;            // system reset
    logic    new_data_ready; // new sending cycle started

 top_fft FFT(.*);
 FFT_top_BFM BFM(.*);
 // testcase tc();
endmodule