-----------------------------------------------------------------------------
------------------------------ Data load driver -----------------------------
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

use work.fft_module_pkg.all;

entity loading_logic is
  Port(
      -- clock and reset signals
       clk           : in  std_logic;
       clk_data_en   : in  std_logic;
       rst           : in  std_logic;
      -- load done
       load_done     : out std_logic;
       load_out_reg  : out std_logic
       );
end loading_logic;

architecture Behavioral of loading_logic is

 -- signal declaration
  signal load_cnt_s  : std_logic_vector (c_STAGE_COUNT - 1 downto 0);
  signal load_cnt_c  : std_logic_vector (c_STAGE_COUNT - 1 downto 0);
 
 begin
 
  load_counter_s: process (clk, clk_data_en, rst)
   begin
    if rst = '1' then
     load_cnt_s <= (others => '1');
    elsif (rising_edge(clk) and clk_data_en = '1') then
     load_cnt_s <= load_cnt_c;
    end if;
   end process;
 
  load_counter_c: process (load_cnt_s)
   begin
     load_done <= '0';
     load_out_reg <= '0';
     load_cnt_c <= load_cnt_s + 1;
    if load_cnt_s = c_FFT_SIZE - 1 then
       load_cnt_c <= (others => '0');
       load_done <= '1';
    end if;
    if load_cnt_s = c_FFT_SIZE - 2 then
      load_out_reg <= '1';
    end if;
   end process;

end Behavioral;