`timescale 1 ns/1 ps
// BFM, testbench
import test_pkg::*;

module FFT_top_testbench ();

    logic  [c_DATA_WIDTH-1 : 0] DATA_out [2*c_FFT_SIZE-1 :0];      // output from FFT_top - serial data
    logic  [c_DATA_WIDTH-1 : 0] DATA_in [2*c_FFT_SIZE-1 :0];       // input to FFT_top - serial data
    logic    clk;           // main clock domain, used for counting FFT
    logic    clk_data_en;   // clock signal, drives DATA_in sending
    logic    rst;           // system reset
    logic    load_en;       // enable loading data into FFT

fft_module FFT(
.DATA_out(DATA_out),
.*);
FFT_top_BFM BFM(.*);
testcase tc();
endmodule