-----------------------------------------------------------------------------
------------------------------ Data load driver -----------------------------
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

use work.fft_module_pkg.all;

entity data_load_driver is
  Port(
      -- clock and reset signals
       clk_data_in   : in  std_logic;
       rst           : in  std_logic;
      -- load enable
       load_en       : in  std_logic;
      -- load done
       load_done     : out std_logic;
       load_out_reg  : out std_logic
       );
end data_load_driver;

architecture Behavioral of data_load_driver is

 -- signal declaration
  signal load_cnt_p  : std_logic_vector (c_DATA_LOAD_DRV_CNT_SIZE - 1 downto 0);
  signal load_cnt_n  : std_logic_vector (c_DATA_LOAD_DRV_CNT_SIZE - 1 downto 0);
 
 begin
 
  load_counter_s: process (clk_data_in, rst)
   begin
    if rst = '1' then
     load_cnt_p <= (others => '1');
    elsif rising_edge (clk_data_in) then
     load_cnt_p <= load_cnt_n;
    end if;
   end process;
 
  load_counter_c: process (load_cnt_p, load_en)
   begin
     load_done <= '0';
     load_out_reg <= '0';
    if load_en = '1' then
      load_cnt_n <= load_cnt_p + 1;
     if (c_COMPLEX_DATA = 0) then
      if load_cnt_p = c_FFT_SIZE - 1 then
        load_cnt_n <= (others => '0');
        load_done <= '1';
      end if;
      if load_cnt_p = c_FFT_SIZE - 2 then
        load_out_reg <= '1';
      end if;
    elsif (c_COMPLEX_DATA = 1) then
      if load_cnt_p = 2 * c_FFT_SIZE - 1 then
        load_cnt_n <= (others => '0');
        load_done <= '1';
      end if;
      if load_cnt_p = 2 * c_FFT_SIZE - 2 then
        load_out_reg <= '1';
      end if;
     end if;
    else 
      load_cnt_n <= load_cnt_p;
    end if;
   end process;

end Behavioral;