<profile>

<ReportVersion>
<Version>2017.4</Version>
</ReportVersion>

<UserAssignments>
<unit>ns</unit>
<ProductFamily>zynq</ProductFamily>
<Part>xc7z020clg400-1</Part>
<TopModelName>matrix_multiply_alt2_3</TopModelName>
<TargetClockPeriod>20.00</TargetClockPeriod>
<ClockUncertainty>2.50</ClockUncertainty>
</UserAssignments>

<PerformanceEstimates>
<PipelineType>none</PipelineType>
<SummaryOfTimingAnalysis>
<unit>ns</unit>
<EstimatedClockPeriod>16.34</EstimatedClockPeriod>
</SummaryOfTimingAnalysis>
<SummaryOfOverallLatency>
<unit>clock cycles</unit>
<Best-caseLatency>75</Best-caseLatency>
<Average-caseLatency>75</Average-caseLatency>
<Worst-caseLatency>75</Worst-caseLatency>
<Interval-min>75</Interval-min>
<Interval-max>75</Interval-max>
</SummaryOfOverallLatency>
<SummaryOfLoopLatency>
<a_col_loop_a_row_loop_b_col_loop>
<TripCount>64</TripCount>
<Latency>73</Latency>
<PipelineII>1</PipelineII>
<PipelineDepth>11</PipelineDepth>
</a_col_loop_a_row_loop_b_col_loop>
</SummaryOfLoopLatency>
</PerformanceEstimates>

<AreaEstimates>
<Resources>
<BRAM_18K>4</BRAM_18K>
<DSP48E>20</DSP48E>
<FF>2322</FF>
<LUT>3530</LUT>
</Resources>
<AvailableResources>
<BRAM_18K>280</BRAM_18K>
<DSP48E>220</DSP48E>
<FF>106400</FF>
<LUT>53200</LUT>
</AvailableResources>
</AreaEstimates>

<InterfaceSummary>
<RtlPorts>
<name>ap_clk</name>
<Object>matrix_multiply_alt2.3</Object>
<Type>return value</Type>
<Scope></Scope>
<IOProtocol>ap_ctrl_hs</IOProtocol>
<IOConfig></IOConfig>
<Dir>in</Dir>
<Bits>1</Bits>
<Attribute>control</Attribute>
</RtlPorts>
<RtlPorts>
<name>ap_rst</name>
<Object>matrix_multiply_alt2.3</Object>
<Type>return value</Type>
<Scope></Scope>
<IOProtocol>ap_ctrl_hs</IOProtocol>
<IOConfig></IOConfig>
<Dir>in</Dir>
<Bits>1</Bits>
<Attribute>control</Attribute>
</RtlPorts>
<RtlPorts>
<name>ap_start</name>
<Object>matrix_multiply_alt2.3</Object>
<Type>return value</Type>
<Scope></Scope>
<IOProtocol>ap_ctrl_hs</IOProtocol>
<IOConfig></IOConfig>
<Dir>in</Dir>
<Bits>1</Bits>
<Attribute>control</Attribute>
</RtlPorts>
<RtlPorts>
<name>ap_done</name>
<Object>matrix_multiply_alt2.3</Object>
<Type>return value</Type>
<Scope></Scope>
<IOProtocol>ap_ctrl_hs</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>1</Bits>
<Attribute>control</Attribute>
</RtlPorts>
<RtlPorts>
<name>ap_idle</name>
<Object>matrix_multiply_alt2.3</Object>
<Type>return value</Type>
<Scope></Scope>
<IOProtocol>ap_ctrl_hs</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>1</Bits>
<Attribute>control</Attribute>
</RtlPorts>
<RtlPorts>
<name>ap_ready</name>
<Object>matrix_multiply_alt2.3</Object>
<Type>return value</Type>
<Scope></Scope>
<IOProtocol>ap_ctrl_hs</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>1</Bits>
<Attribute>control</Attribute>
</RtlPorts>
<RtlPorts>
<name>A_re_address0</name>
<Object>A_re</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>4</Bits>
<Attribute>address</Attribute>
</RtlPorts>
<RtlPorts>
<name>A_re_ce0</name>
<Object>A_re</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>1</Bits>
<Attribute>control</Attribute>
</RtlPorts>
<RtlPorts>
<name>A_re_q0</name>
<Object>A_re</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>in</Dir>
<Bits>32</Bits>
<Attribute>data</Attribute>
</RtlPorts>
<RtlPorts>
<name>A_im_address0</name>
<Object>A_im</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>4</Bits>
<Attribute>address</Attribute>
</RtlPorts>
<RtlPorts>
<name>A_im_ce0</name>
<Object>A_im</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>1</Bits>
<Attribute>control</Attribute>
</RtlPorts>
<RtlPorts>
<name>A_im_q0</name>
<Object>A_im</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>in</Dir>
<Bits>32</Bits>
<Attribute>data</Attribute>
</RtlPorts>
<RtlPorts>
<name>B_re_address0</name>
<Object>B_re</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>4</Bits>
<Attribute>address</Attribute>
</RtlPorts>
<RtlPorts>
<name>B_re_ce0</name>
<Object>B_re</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>1</Bits>
<Attribute>control</Attribute>
</RtlPorts>
<RtlPorts>
<name>B_re_q0</name>
<Object>B_re</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>in</Dir>
<Bits>32</Bits>
<Attribute>data</Attribute>
</RtlPorts>
<RtlPorts>
<name>B_im_address0</name>
<Object>B_im</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>4</Bits>
<Attribute>address</Attribute>
</RtlPorts>
<RtlPorts>
<name>B_im_ce0</name>
<Object>B_im</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>1</Bits>
<Attribute>control</Attribute>
</RtlPorts>
<RtlPorts>
<name>B_im_q0</name>
<Object>B_im</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>in</Dir>
<Bits>32</Bits>
<Attribute>data</Attribute>
</RtlPorts>
<RtlPorts>
<name>C_re_address0</name>
<Object>C_re</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>4</Bits>
<Attribute>address</Attribute>
</RtlPorts>
<RtlPorts>
<name>C_re_ce0</name>
<Object>C_re</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>1</Bits>
<Attribute>control</Attribute>
</RtlPorts>
<RtlPorts>
<name>C_re_we0</name>
<Object>C_re</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>1</Bits>
<Attribute>control</Attribute>
</RtlPorts>
<RtlPorts>
<name>C_re_d0</name>
<Object>C_re</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>32</Bits>
<Attribute>data</Attribute>
</RtlPorts>
<RtlPorts>
<name>C_im_address0</name>
<Object>C_im</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>4</Bits>
<Attribute>address</Attribute>
</RtlPorts>
<RtlPorts>
<name>C_im_ce0</name>
<Object>C_im</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>1</Bits>
<Attribute>control</Attribute>
</RtlPorts>
<RtlPorts>
<name>C_im_we0</name>
<Object>C_im</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>1</Bits>
<Attribute>control</Attribute>
</RtlPorts>
<RtlPorts>
<name>C_im_d0</name>
<Object>C_im</Object>
<Type>array</Type>
<Scope></Scope>
<IOProtocol>ap_memory</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>32</Bits>
<Attribute>data</Attribute>
</RtlPorts>
</InterfaceSummary>

</profile>
