//******************************************************************************************//
// Instruction decoder interface                                                            //
//******************************************************************************************//

BFM signal name  | Path                                                        | port, comb, reg
                 |                                                             | 
opcode           | u_cortexm0.u_top.u_sys.u_core.u_pfu.pfu_opcode_o            |
                 | u_cortexm0plus.u_top.u_sys.u_core.op_q                      | internal reg
                 |                                                             |
address          | assign address = {iaex, 1'b0};                              |
                 |                                                             |
iaex             | u_cortexm0.u_top.u_sys.u_core.u_pfu.pfu_iaex_val_o          | 
                 | u_cortexm0plus.u_top.u_sys.u_core.iaex_o                    |
                 |                                                             |
instr_queue      | u_cortexm0.u_top.u_sys.u_core.u_pfu.ibuf_de_nxt             | internal comb
                 | u_cortexm0plus.u_top.u_sys.u_core.iq_q                      | internal reg
                 |                                                             |
op_special       | u_cortexm0.u_top.u_sys.u_core.u_pfu.pfu_op_special_o        |
                 | u_cortexm0plus.u_top.u_sys.u_core.op_s_q                    | internal reg
                 |                                                             |
preempt          | u_cortexm0.u_top.u_sys.u_core.u_ctl.u_dec.int_preempt       | 
                 | u_cortexm0plus.u_top.u_sys.u_core.preempt                   | internal comb
                 |                                                             |
atomic           | u_cortexm0.u_top.u_sys.u_core.u_ctl.u_dec.atomic            | 
                 | u_cortexm0plus.u_top.u_sys.u_core.atomic_q                  | internal reg
                 |                                                             |
reg_rxx          | u_cortexm0.u_top.u_sys.u_core.u_gpr.reg_rxx                 | internal reg
                 | u_cortexm0plus.u_top.u_sys.u_core.rxx_q                     | internal reg
                 |                                                             |
reg_lr           | u_cortexm0.u_top.u_sys.u_core.u_gpr.reg_r14                 | internal reg
                 | u_cortexm0plus.u_top.u_sys.u_core.r14_q                     | internal reg
                 |                                                             |
reg_aux          | u_cortexm0.u_top.u_sys.u_core.u_gpr.reg_aux                 | internal reg
                 | u_cortexm0plus.u_top.u_sys.u_core.aux_q                     | internal reg
                 |                                                             |
reg_msp          | assign{u_cortexm0.u_top.u_sys.u_core.u_gpr.reg_msp, 2'b00}; | internal reg
                 | assign{u_cortexm0plus.u_top.u_sys.u_core.msp_q, 2'b00};     | internal reg
                 |                                                             |
reg_psp          | assign{u_cortexm0.u_top.u_sys.u_core.u_gpr.reg_psp, 2'b00}; | internal reg
                 | assign{u_cortexm0plus.u_top.u_sys.u_core.psp_q, 2'b00};     | internal reg
                 |                                                             |
apsr             | u_cortexm0.u_top.u_sys.u_core.u_psr.psr_apsr_o              | 
                 | u_cortexm0plus.u_top.u_sys.u_core.apsr_q                    | internal reg

//******************************************************************************************//
// Cortex M0+ specific signals                                                              //
//******************************************************************************************//

BFM signal name  | Path                                                        | port, comb, reg
                 |                                                             |
op_queue_spec    | u_cortexm0plus.u_top.u_sys.u_core.iq_s_q                    | internal reg
                 |                                                             |
state            | u_cortexm0plus.u_top.u_sys.u_core.state_q                   | internal reg
                 |                                                             |
cc_pass          | u_cortexm0plus.u_top.u_sys.u_core.cc_pass                   | internal comb
                 |                                                             |
fault            | u_cortexm0plus.u_top.u_sys.u_core.fault_q                   | internal reg
                 |                                                             |
hard_fault       | u_cortexm0plus.u_top.u_sys.u_core.cpu_hdf_request_o         |
                 |                                                             |
lockup           | u_cortexm0plus.LOCKUP                                       |
                 |                                                             |
halted           | u_cortexm0plus.HALTED                                       |
                 |                                                             |
irq_ack          | u_cortexm0plus.u_top.u_sys.u_core.irq_ack                   | internal comb
                 |                                                             |
rfe_ack          | u_cortexm0plus.u_top.u_sys.u_core.rfe_ack                   | internal comb
                 |                                                             |
int_ready        | u_cortexm0plus.u_top.u_sys.u_core.int_ready_q               | internal reg
                 |                                                             |
int_pend_num     | u_cortexm0plus.u_top.u_sys.u_core.nvm_int_pend_num_i        |

//******************************************************************************************//
// Cortex M0 specific signals                                                               //
//******************************************************************************************//

BFM signal name  | Path                                                        | port, comb, reg
                 |                                                             |
ctl_ex_last      | u_cortexm0.u_top.u_sys.u_core.u_ctl.ctl_ex_last_o           |
                 |                                                             |
data_abort       | u_cortexm0.u_top.u_sys.u_core.u_ctl.u_dec.data_abort        |
                 |                                                             |
tbit             | u_cortexm0.u_top.u_sys.u_core.u_pfu.pfu_tbit_o              |

//******************************************************************************************//
// Interrupt visualizer interface                                                           //
//******************************************************************************************//

BFM signal name  | Path                                                        | port, comb, reg
                 |                                                             |
int_active_bit   | u_cortexm0.u_top.u_sys.u_nvic.u_main.nvm_actv_bit_o         |
                 | u_cortexm0plus.u_top.u_sys.u_nvic.actv_bit                  | internal comb
                 |                                                             |
int_pend         | u_cortexm0.u_top.u_sys.u_nvic.nvm_int_pend_o                |
                 | u_cortexm0plus.u_top.u_sys.u_nvic.nvm_int_pend_o            |
                 |                                                             |
int_irq_lvl      | u_cortexm0.u_top.u_sys.u_nvic.u_reg.nvr_irq_lvl_o           |
                 | u_cortexm0plus.u_top.u_sys.u_nvic.irq_lvl_q                 | internal reg
                 |                                                             |
int_sys_tick_lvl | u_cortexm0.u_top.u_sys.u_nvic.u_reg.nvr_tck_lvl_o           |
                 | u_cortexm0plus.u_top.u_sys.u_nvic.tck_lvl_q                 | internal reg
                 |                                                             | 
int_svc_lvl      | u_cortexm0.u_top.u_sys.u_nvic.u_reg.nvr_svc_lvl_o           |
                 | u_cortexm0plus.u_top.u_sys.u_nvic.svc_lvl_q                 | internal reg
                 |                                                             | 
int_psv_lvl      | u_cortexm0.u_top.u_sys.u_nvic.u_reg.nvr_psv_lvl_o           |
                 | u_cortexm0plus.u_top.u_sys.u_nvic.psv_lvl_q                 | internal reg
                 |                                                             | 
int_taken        | u_cortexm0.u_top.u_sys.u_nvic.dec_int_taken_i               |
                 | u_cortexm0plus.u_top.u_sys.u_nvic.cpu_int_taken_i           |
                 |                                                             | 
int_return       | u_cortexm0.u_top.u_sys.u_nvic.dec_int_return_i              |
                 | u_cortexm0plus.u_top.u_sys.u_nvic.cpu_int_return_i          |

//******************************************************************************************//
// Memory access checker interface                                                          //
//******************************************************************************************//

BFM signal name  | Path                                                        | port, comb, reg
                 |                                                             |
HADDR            | u_cortexm0.HADDR                                            |
                 | u_cortexm0plus.HADDR                                        |
                 
                 
                 
                 