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# cs8900.h

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    00001 /*! \file cs8900.h \brief Crystal CS8900 Ethernet Interface Driver. */
    00002 //*****************************************************************************
    00003 //
    00004 // File Name    : 'cs8900.h'
    00005 // Title        : Crystal CS8900 Ethernet Interface Driver
    00006 // Author       : Pascal Stang
    00007 // Created      : 11/7/2004
    00008 // Revised      : 8/22/2005
    00009 // Version      : 0.1
    00010 // Target MCU   : Atmel AVR series
    00011 // Editor Tabs  : 4
    00012 //
    00013 /// \ingroup network
    00014 /// \defgroup cs8900 Crystal CS8900 Ethernet Interface Driver (cs8900.c)
    00015 /// \code #include "net/cs8900.h" \endcode
    00016 /// \par Overview
    00017 ///     This driver provides initialization and transmit/receive
    00018 /// functions for the Crystal CS8900 10Mb Ethernet Controller and PHY.
    00019 //
    00020 //*****************************************************************************
    00021 //@{
    00022
    00023 #ifndef CS8900_H
    00024 #define CS8900_H
    00025
    00026 #include "global.h"
    00027
    00028 #define nop()   asm volatile ("nop")
    00029
    00030
    00031 // Crystal ESIA product ID
    00032 #define CS8900_ESIA_ID              (0x630e)
    00033
    00034 // CS8900 IO Registers
    00035 #define CS8900_IO_RXTX_DATA_PORT0   (0x0000)
    00036 #define CS8900_IO_RXTX_DATA_PORT1   (0x0002)
    00037 #define CS8900_IO_TXCMD             (0x0004)
    00038 #define CS8900_IO_TXLENGTH          (0x0006)
    00039 #define CS8900_IO_ISQ               (0x0008)
    00040 #define CS8900_IO_PP_PTR            (0x000a)
    00041 #define CS8900_IO_PP_DATA_PORT0     (0x000c)
    00042 #define CS8900_IO_PP_DATA_PORT1     (0x000e)
    00043
    00044 // definitions for Crystal CS8900 ethernet-controller
    00045 // based on linux-header by Russel Nelson
    00046
    00047 #define PP_ChipID            0x0000              // offset 0h -> Corp-ID
    00048                                                  // offset 2h -> Model/Product Number
    00049                                                  // offset 3h -> Chip Revision Number
    00050
    00051 #define PP_ISAIOB            0x0020              // IO base address
    00052 #define PP_CS8900_ISAINT     0x0022              // ISA interrupt select
    00053 #define PP_CS8900_ISADMA     0x0024              // ISA Rec DMA channel
    00054 #define PP_ISASOF            0x0026              // ISA DMA offset
    00055 #define PP_DmaFrameCnt       0x0028              // ISA DMA Frame count
    00056 #define PP_DmaByteCnt        0x002A              // ISA DMA Byte count
    00057 #define PP_CS8900_ISAMemB    0x002C              // Memory base
    00058 #define PP_ISABootBase       0x0030              // Boot Prom base
    00059 #define PP_ISABootMask       0x0034              // Boot Prom Mask
    00060 #define PP_RxFrameByteCnt   0x0050
    00061
    00062 // EEPROM data and command registers
    00063 #define PP_EECMD             0x0040              // NVR Interface Command register
    00064 #define PP_EEData            0x0042              // NVR Interface Data Register
    00065
    00066 // Configuration and control registers
    00067 #define PP_RxCFG             0x0102              // Rx Bus config
    00068 #define PP_RxCTL             0x0104              // Receive Control Register
    00069 #define PP_TxCFG             0x0106              // Transmit Config Register
    00070 #define PP_TxCMD             0x0108              // Transmit Command Register
    00071 #define PP_BufCFG            0x010A              // Bus configuration Register
    00072 #define PP_LineCTL           0x0112              // Line Config Register
    00073 #define PP_SelfCTL           0x0114              // Self Command Register
    00074 #define PP_BusCTL            0x0116              // ISA bus control Register
    00075 #define PP_TestCTL           0x0118              // Test Register
    00076
    00077 // Status and Event Registers
    00078 #define PP_ISQ               0x0120              // Interrupt Status
    00079 #define PP_RxEvent           0x0124              // Rx Event Register
    00080 #define PP_TxEvent           0x0128              // Tx Event Register
    00081 #define PP_BufEvent          0x012C              // Bus Event Register
    00082 #define PP_RxMiss            0x0130              // Receive Miss Count
    00083 #define PP_TxCol             0x0132              // Transmit Collision Count
    00084 #define PP_LineST            0x0134              // Line State Register
    00085 #define PP_SelfST            0x0136              // Self State register
    00086 #define PP_BusST             0x0138              // Bus Status
    00087 #define PP_TDR               0x013C              // Time Domain Reflectometry
    00088
    00089 // Initiate Transmit Registers
    00090 #define PP_TxCommand         0x0144              // Tx Command
    00091 #define PP_TxLength          0x0146              // Tx Length
    00092
    00093 // Address Filter Registers
    00094 #define PP_LAF               0x0150              // Hash Table
    00095 #define PP_IA                0x0158              // Physical Address Register
    00096
    00097 // Frame Location
    00098 #define PP_RxStatus          0x0400              // Receive start of frame
    00099 #define PP_RxLength          0x0402              // Receive Length of frame
    00100 #define PP_RxFrame           0x0404              // Receive frame pointer
    00101 #define PP_TxFrame           0x0A00              // Transmit frame pointer
    00102
    00103 // Primary I/O Base Address. If no I/O base is supplied by the user, then this
    00104 // can be used as the default I/O base to access the PacketPage Area.
    00105 #define DEFAULTIOBASE               0x0300
    00106
    00107 // PP_RxCFG - Receive  Configuration and Interrupt Mask bit definition - Read/write
    00108 #define SKIP_1                      0x0040
    00109 #define RX_STREAM_ENBL              0x0080
    00110 #define RX_OK_ENBL                  0x0100
    00111 #define RX_DMA_ONLY                 0x0200
    00112 #define AUTO_RX_DMA                 0x0400
    00113 #define BUFFER_CRC                  0x0800
    00114 #define RX_CRC_ERROR_ENBL           0x1000
    00115 #define RX_RUNT_ENBL                0x2000
    00116 #define RX_EXTRA_DATA_ENBL          0x4000
    00117
    00118 // PP_RxCTL - Receive Control bit definition - Read/write
    00119 #define RX_IA_HASH_ACCEPT           0x0040
    00120 #define RX_PROM_ACCEPT              0x0080
    00121 #define RX_OK_ACCEPT                0x0100
    00122 #define RX_MULTCAST_ACCEPT          0x0200
    00123 #define RX_IA_ACCEPT                0x0400
    00124 #define RX_BROADCAST_ACCEPT         0x0800
    00125 #define RX_BAD_CRC_ACCEPT           0x1000
    00126 #define RX_RUNT_ACCEPT              0x2000
    00127 #define RX_EXTRA_DATA_ACCEPT        0x4000
    00128
    00129 // PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write
    00130 #define TX_LOST_CRS_ENBL            0x0040
    00131 #define TX_SQE_ERROR_ENBL           0x0080
    00132 #define TX_OK_ENBL                  0x0100
    00133 #define TX_LATE_COL_ENBL            0x0200
    00134 #define TX_JBR_ENBL                 0x0400
    00135 #define TX_ANY_COL_ENBL             0x0800
    00136 #define TX_16_COL_ENBL              0x8000
    00137
    00138 // PP_TxCMD - Transmit Command bit definition - Read-only and
    00139 // PP_TxCommand - Write-only
    00140 #define TX_START_5_BYTES            0x0000
    00141 #define TX_START_381_BYTES          0x0040
    00142 #define TX_START_1021_BYTES         0x0080
    00143 #define TX_START_ALL_BYTES          0x00C0
    00144 #define TX_FORCE                    0x0100
    00145 #define TX_ONE_COL                  0x0200
    00146 #define TX_NO_CRC                   0x1000
    00147 #define TX_RUNT                     0x2000
    00148
    00149 // PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write
    00150 #define GENERATE_SW_INTERRUPT       0x0040
    00151 #define RX_DMA_ENBL                 0x0080
    00152 #define READY_FOR_TX_ENBL           0x0100
    00153 #define TX_UNDERRUN_ENBL            0x0200
    00154 #define RX_MISS_ENBL                0x0400
    00155 #define RX_128_BYTE_ENBL            0x0800
    00156 #define TX_COL_COUNT_OVRFLOW_ENBL   0x1000
    00157 #define RX_MISS_COUNT_OVRFLOW_ENBL  0x2000
    00158 #define RX_DEST_MATCH_ENBL          0x8000
    00159
    00160 // PP_LineCTL - Line Control bit definition - Read/write
    00161 #define SERIAL_RX_ON                0x0040
    00162 #define SERIAL_TX_ON                0x0080
    00163 #define AUI_ONLY                    0x0100
    00164 #define AUTO_AUI_10BASET            0x0200
    00165 #define MODIFIED_BACKOFF            0x0800
    00166 #define NO_AUTO_POLARITY            0x1000
    00167 #define TWO_PART_DEFDIS             0x2000
    00168 #define LOW_RX_SQUELCH              0x4000
    00169
    00170 // PP_SelfCTL - Software Self Control bit definition - Read/write
    00171 #define POWER_ON_RESET              0x0040
    00172 #define SW_STOP                     0x0100
    00173 #define SLEEP_ON                    0x0200
    00174 #define AUTO_WAKEUP                 0x0400
    00175 #define HCB0_ENBL                   0x1000
    00176 #define HCB1_ENBL                   0x2000
    00177 #define HCB0                        0x4000
    00178 #define HCB1                        0x8000
    00179
    00180 // PP_BusCTL - ISA Bus Control bit definition - Read/write
    00181 #define RESET_RX_DMA                0x0040
    00182 #define MEMORY_ON                   0x0400
    00183 #define DMA_BURST_MODE              0x0800
    00184 #define IO_CHANNEL_READY_ON         0x1000
    00185 #define RX_DMA_SIZE_64K             0x2000
    00186 #define ENABLE_IRQ                  0x8000
    00187
    00188 // PP_TestCTL - Test Control bit definition - Read/write
    00189 #define LINK_OFF             0x0080
    00190 #define ENDEC_LOOPBACK       0x0200
    00191 #define AUI_LOOPBACK         0x0400
    00192 #define BACKOFF_OFF          0x0800
    00193 #define FDX_8900             0x4000
    00194
    00195 // PP_RxEvent - Receive Event Bit definition - Read-only
    00196 #define RX_IA_HASHED         0x0040
    00197 #define RX_DRIBBLE           0x0080
    00198 #define RX_OK                0x0100
    00199 #define RX_HASHED            0x0200
    00200 #define RX_IA                0x0400
    00201 #define RX_BROADCAST         0x0800
    00202 #define RX_CRC_ERROR         0x1000
    00203 #define RX_RUNT              0x2000
    00204 #define RX_EXTRA_DATA        0x4000
    00205 #define HASH_INDEX_MASK      0xFC00              // Hash-Table Index Mask (6 Bit)
    00206
    00207 // PP_TxEvent - Transmit Event Bit definition - Read-only
    00208 #define TX_LOST_CRS          0x0040
    00209 #define TX_SQE_ERROR         0x0080
    00210 #define TX_OK                0x0100
    00211 #define TX_LATE_COL          0x0200
    00212 #define TX_JBR               0x0400
    00213 #define TX_16_COL            0x8000
    00214 #define TX_COL_COUNT_MASK    0x7800
    00215
    00216 // PP_BufEvent - Buffer Event Bit definition - Read-only
    00217 #define SW_INTERRUPT         0x0040
    00218 #define RX_DMA               0x0080
    00219 #define READY_FOR_TX         0x0100
    00220 #define TX_UNDERRUN          0x0200
    00221 #define RX_MISS              0x0400
    00222 #define RX_128_BYTE          0x0800
    00223 #define TX_COL_OVRFLW        0x1000
    00224 #define RX_MISS_OVRFLW       0x2000
    00225 #define RX_DEST_MATCH        0x8000
    00226
    00227 // PP_LineST - Ethernet Line Status bit definition - Read-only
    00228 #define LINK_OK              0x0080
    00229 #define AUI_ON               0x0100
    00230 #define TENBASET_ON          0x0200
    00231 #define POLARITY_OK          0x1000
    00232 #define CRS_OK               0x4000
    00233
    00234 // PP_SelfST - Chip Software Status bit definition
    00235 #define ACTIVE_33V           0x0040
    00236 #define INIT_DONE            0x0080
    00237 #define SI_BUSY              0x0100
    00238 #define EEPROM_PRESENT       0x0200
    00239 #define EEPROM_OK            0x0400
    00240 #define EL_PRESENT           0x0800
    00241 #define EE_SIZE_64           0x1000
    00242
    00243 // PP_BusST - ISA Bus Status bit definition
    00244 #define TX_BID_ERROR         0x0080
    00245 #define READY_FOR_TX_NOW     0x0100
    00246
    00247 // The following block defines the ISQ event types
    00248 #define ISQ_RX_EVENT         0x0004
    00249 #define ISQ_TX_EVENT         0x0008
    00250 #define ISQ_BUFFER_EVENT     0x000C
    00251 #define ISQ_RX_MISS_EVENT    0x0010
    00252 #define ISQ_TX_COL_EVENT     0x0012
    00253
    00254 #define ISQ_EVENT_MASK       0x003F              // ISQ mask to find out type of event
    00255
    00256 #define AUTOINCREMENT        0x8000              // Bit mask to set Bit-15 for autoincrement
    00257
    00258 // EEProm Commands
    00259 #define EEPROM_WRITE_EN      0x00F0
    00260 #define EEPROM_WRITE_DIS     0x0000
    00261 #define EEPROM_WRITE_CMD     0x0100
    00262 #define EEPROM_READ_CMD      0x0200
    00263
    00264 // Receive Header of each packet in receive area of memory for DMA-Mode
    00265 #define RBUF_EVENT_LOW       0x0000              // Low byte of RxEvent
    00266 #define RBUF_EVENT_HIGH      0x0001              // High byte of RxEvent
    00267 #define RBUF_LEN_LOW         0x0002              // Length of received data - low byte
    00268 #define RBUF_LEN_HI          0x0003              // Length of received data - high byte
    00269 #define RBUF_HEAD_LEN        0x0004              // Length of this header
    00270
    00271 // typedefs
    00272
    00273 // constants
    00274
    00275 // prototypes
    00276
    00277 #include "nic.h"
    00278
    00279 unsigned int cs8900BeginPacketRetreive(void);
    00280 void cs8900RetreivePacketData(u08* packet, unsigned int packetLength);
    00281 void cs8900EndPacketRetreive(void);
    00282
    00283
    00284 void cs8900Init(void);
    00285 void cs8900Write(unsigned char address, unsigned char data);
    00286 unsigned char cs8900Read(unsigned char address);
    00287
    00288 void cs8900Write16(unsigned char address, unsigned short data);
    00289 unsigned short cs8900Read16(unsigned char address);
    00290
    00291 void cs8900WriteReg(unsigned short address, unsigned short data);
    00292 unsigned short cs8900ReadReg(unsigned short address);
    00293
    00294 void cs8900CopyToFrame(unsigned char *source, unsigned short size);
    00295 void cs8900CopyFromFrame(unsigned char *dest, unsigned short size);
    00296
    00297 u08 cs8900LinkStatus(void);
    00298
    00299 void cs8900IORegDump(void);
    00300 void cs8900RegDump(void);
    00301
    00302 #endif
    00303 //@}
    00304
    00305
    00306 /****************
    00307
    00308 // CS8900 device register definitions
    00309
    00310 // Crystal ESIA product id.
    00311
    00312 #define CS8900_ESIA_ID             (0x630e)
    00313
    00314 //IO Registers.
    00315 #define CS8900_IO_RX_TX_DATA_PORT0 (0x0000)
    00316 #define CS8900_IO_TX_TX_DATA_PORT1 (0x0002)
    00317 #define CS8900_IO_TxCMD            (0x0004)
    00318 #define CS8900_IO_TxLength         (0x0006)
    00319 #define CS8900_IO_ISQ              (0x0008)
    00320 #define CS8900_IO_PACKET_PAGE_PTR  (0x000a)
    00321 #define CS8900_IO_PP_DATA_PORT0    (0x000c)
    00322 #define CS8900_IO_PP_DATA_PORT1    (0x000e)
    00323
    00324  * Packet Page Registers.
    00325
    00326  * Bus Interface Registers.
    00327
    00328 #define CS8900_PP_PROD_ID          (0x0000)
    00329 #define CS8900_PP_IO_BASE          (0x0020)
    00330 #define CS8900_PP_INT              (0x0022)
    00331 #define CS8900_PP_DMA_CHANNEL      (0x0024)
    00332 #define CS8900_PP_DMA_SOF          (0x0026)
    00333 #define CS8900_PP_DMA_FRM_CNT      (0x0028)
    00334 #define CS8900_PP_DMA_RX_BCNT      (0x002a)
    00335 #define CS8900_PP_MEM_BASE         (0x002c)
    00336 #define CS8900_PP_BPROM_BASE       (0x0030)
    00337 #define CS8900_PP_BPROM_AMASK      (0x0034)
    00338 #define CS8900_PP_EEPROM_CMD       (0x0040)
    00339 #define CS8900_PP_EEPROM_DATA      (0x0042)
    00340 #define CS8900_PP_RX_FRAME_BCNT    (0x0050)
    00341
    00342  * Configuration and Control Registers.
    00343
    00344 #define CS8900_PP_RxCFG            (0x0102)
    00345 #define CS8900_PP_RxCTL            (0x0104)
    00346 #define CS8900_PP_TxCFG            (0x0106)
    00347 #define CS8900_PP_TxCMD_READ       (0x0108)
    00348 #define CS8900_PP_BufCFG           (0x010a)
    00349 #define CS8900_PP_LineCFG          (0x0112)
    00350 #define CS8900_PP_SelfCTL          (0x0114)
    00351 #define CS8900_PP_BusCTL           (0x0116)
    00352 #define CS8900_PP_TestCTL          (0x0118)
    00353
    00354  * Status and Event Registers.
    00355
    00356 #define CS8900_PP_ISQ              (0x0120)
    00357 #define CS8900_PP_RxEvent          (0x0124)
    00358 #define CS8900_PP_TxEvent          (0x0128)
    00359 #define CS8900_PP_BufEvent         (0x012c)
    00360 #define CS8900_PP_RxMISS           (0x0130)
    00361 #define CS8900_PP_TxCol            (0x0132)
    00362 #define CS8900_PP_LineST           (0x0134)
    00363 #define CS8900_PP_SelfST           (0x0136)
    00364 #define CS8900_PP_BusST            (0x0138)
    00365 #define CS8900_PP_TDR              (0x013c)
    00366
    00367  * Initiate Transmit Registers.
    00368 #define CS8900_PP_TxCMD            (0x0144)
    00369 #define CS8900_PP_TxLength         (0x0146)
    00370
    00371 * Address Filter Registers.
    00372 #define CS8900_PP_LAF              (0x0150)
    00373 #define CS8900_PP_IA               (0x0158)
    00374
    00375  * Frame Location.
    00376 #define CS8900_PP_RxStatus         (0x0400)
    00377 #define CS8900_PP_RxLength         (0x0402)
    00378 #define CS8900_PP_RxFrameLoc       (0x0404)
    00379 #define CS8900_PP_TxFrameLoc       (0x0a00)
    00380
    00381  * Bit Definitions of Registers.
    00382  * IO Packet Page Pointer.
    00383 #define CS8900_PPP_AUTO_INCREMENT             (0x8000)
    00384
    00385  * Reg 3. Receiver Configuration.
    00386 #define CS8900_RX_CONFIG_SKIP_1               (1 << 6)
    00387 #define CS8900_RX_CONFIG_STREAM_ENABLE        (1 << 7)
    00388 #define CS8900_RX_CONFIG_RX_OK                (1 << 8)
    00389 #define CS8900_RX_CONFIG_RX_DMA               (1 << 9)
    00390 #define CS8900_RX_CONFIG_RX_AUTO_DMA          (1 << 10)
    00391 #define CS8900_RX_CONFIG_BUFFER_CRC           (1 << 11)
    00392 #define CS8900_RX_CONFIG_CRC_ERROR            (1 << 12)
    00393 #define CS8900_RX_CONFIG_RUNT                 (1 << 13)
    00394 #define CS8900_RX_CONFIG_EXTRA_DATA           (1 << 14)
    00395
    00396  * Reg 4. Receiver Event.
    00397 #define CS8900_RX_EVENT_HASH_IA_MATCH         (1 << 6)
    00398 #define CS8900_RX_EVENT_DRIBBLE_BITS          (1 << 7)
    00399 #define CS8900_RX_EVENT_RX_OK                 (1 << 8)
    00400 #define CS8900_RX_EVENT_HASHED                (1 << 9)
    00401 #define CS8900_RX_EVENT_IA                    (1 << 10)
    00402 #define CS8900_RX_EVENT_BROADCAST             (1 << 11)
    00403 #define CS8900_RX_EVENT_CRC_ERROR             (1 << 12)
    00404 #define CS8900_RX_EVENT_RUNT                  (1 << 13)
    00405 #define CS8900_RX_EVENT_EXTRA_DATA            (1 << 14)
    00406
    00407  * Reg 5. Receiver Control.
    00408 #define CS8900_RX_CTRL_HASH_IA_MATCH          (1 << 6)
    00409 #define CS8900_RX_CTRL_PROMISCUOUS            (1 << 7)
    00410 #define CS8900_RX_CTRL_RX_OK                  (1 << 8)
    00411 #define CS8900_RX_CTRL_MULTICAST              (1 << 9)
    00412 #define CS8900_RX_CTRL_INDIVIDUAL             (1 << 10)
    00413 #define CS8900_RX_CTRL_BROADCAST              (1 << 11)
    00414 #define CS8900_RX_CTRL_CRC_ERROR              (1 << 12)
    00415 #define CS8900_RX_CTRL_RUNT                   (1 << 13)
    00416 #define CS8900_RX_CTRL_EXTRA_DATA             (1 << 14)
    00417
    00418  * Reg 7. Transmit Configuration.
    00419 #define CS8900_TX_CONFIG_LOSS_OF_CARRIER      (1 << 6)
    00420 #define CS8900_TX_CONFIG_SQ_ERROR             (1 << 7)
    00421 #define CS8900_TX_CONFIG_TX_OK                (1 << 8)
    00422 #define CS8900_TX_CONFIG_OUT_OF_WINDOW        (1 << 9)
    00423 #define CS8900_TX_CONFIG_JABBER               (1 << 10)
    00424 #define CS8900_TX_CONFIG_ANY_COLLISION        (1 << 11)
    00425 #define CS8900_TX_CONFIG_16_COLLISION         (1 << 15)
    00426
    00427  * Reg 8. Transmit Event.
    00428 #define CS8900_TX_EVENT_LOSS_OF_CARRIER       (1 << 6)
    00429 #define CS8900_TX_EVENT_SQ_ERROR              (1 << 7)
    00430 #define CS8900_TX_EVENT_TX_OK                 (1 << 8)
    00431 #define CS8900_TX_EVENT_OUT_OF_WINDOW         (1 << 9)
    00432 #define CS8900_TX_EVENT_JABBER                (1 << 10)
    00433 #define CS8900_TX_EVENT_16_COLLISIONS         (1 << 15)
    00434
    00435  * Reg 9. Transmit Command Status.
    00436 #define CS8900_TX_CMD_STATUS_TX_START_5       (0 << 6)
    00437 #define CS8900_TX_CMD_STATUS_TX_START_381     (1 << 6)
    00438 #define CS8900_TX_CMD_STATUS_TX_START_1021    (2 << 6)
    00439 #define CS8900_TX_CMD_STATUS_TX_START_ENTIRE  (3 << 6)
    00440 #define CS8900_TX_CMD_STATUS_FORCE            (1 << 8)
    00441 #define CS8900_TX_CMD_STATUS_ONE_COLLISION    (1 << 9)
    00442 #define CS8900_TX_CMD_STATUS_INHIBIT_CRC      (1 << 12)
    00443 #define CS8900_TX_CMD_STATUS_TX_PAD_DISABLED  (1 << 13)
    00444
    00445  * Reg B. Buffer Configuration.
    00446 #define CS8900_BUFFER_CONFIG_SW_INT           (1 << 6)
    00447 #define CS8900_BUFFER_CONFIG_RX_DMA_DONE      (1 << 7)
    00448 #define CS8900_BUFFER_CONFIG_RDY_FOR_TX       (1 << 8)
    00449 #define CS8900_BUFFER_CONFIG_TX_UNDERRUN      (1 << 9)
    00450 #define CS8900_BUFFER_CONFIG_RX_MISSED        (1 << 10)
    00451 #define CS8900_BUFFER_CONFIG_RX_128_BYTES     (1 << 11)
    00452 #define CS8900_BUFFER_CONFIG_TX_COL_OVF       (1 << 12)
    00453 #define CS8900_BUFFER_CONFIG_RX_MISSED_OVF    (1 << 13)
    00454 #define CS8900_BUFFER_CONFIG_RX_DEST_MATCH    (1 << 15)
    00455
    00456  * Reg C. Buffer Event.
    00457 #define CS8900_BUFFER_EVENT_SW_INT            (1 << 6)
    00458 #define CS8900_BUFFER_EVENT_RX_DMA_DONE       (1 << 7)
    00459 #define CS8900_BUFFER_EVENT_RDY_FOR_TX        (1 << 8)
    00460 #define CS8900_BUFFER_EVENT_TX_UNDERRUN       (1 << 9)
    00461 #define CS8900_BUFFER_EVENT_RX_MISSED         (1 << 10)
    00462 #define CS8900_BUFFER_EVENT_RX_128_BYTES      (1 << 11)
    00463 #define CS8900_BUFFER_EVENT_RX_DEST_MATCH     (1 << 15)
    00464
    00465  * Reg 13. Line Control.
    00466 #define CS8900_LINE_CTRL_RX_ON               (1 << 6)
    00467 #define CS8900_LINE_CTRL_TX_ON               (1 << 7)
    00468 #define CS8900_LINE_CTRL_AUI                 (1 << 8)
    00469 #define CS8900_LINE_CTRL_10BASET             (0 << 9)
    00470 #define CS8900_LINE_CTRL_AUTO_AUI_10BASET    (1 << 9)
    00471 #define CS8900_LINE_CTRL_MOD_BACKOFF         (1 << 11)
    00472 #define CS8900_LINE_CTRL_POLARITY_DISABLED   (1 << 12)
    00473 #define CS8900_LINE_CTRL_2_PART_DEF_DISABLED (1 << 13)
    00474 #define CS8900_LINE_CTRL_LO_RX_SQUELCH       (1 << 14)
    00475
    00476  * Reg 14. Line Status.
    00477 #define CS8900_LINE_STATUS_LINK_OK           (1 << 7)
    00478 #define CS8900_LINE_STATUS_AUI               (1 << 8)
    00479 #define CS8900_LINE_STATUS_10_BASE_T         (1 << 9)
    00480 #define CS8900_LINE_STATUS_POLARITY_OK       (1 << 12)
    00481 #define CS8900_LINE_STATUS_CRS               (1 << 14)
    00482
    00483  * Reg 15. Self Control.
    00484 #define CS8900_SELF_CTRL_RESET              (1 << 6)
    00485 #define CS8900_SELF_CTRL_SW_SUSPEND         (1 << 8)
    00486 #define CS8900_SELF_CTRL_HW_SLEEP           (1 << 9)
    00487 #define CS8900_SELF_CTRL_HW_STANDBY         (1 << 10)
    00488 #define CS8900_SELF_CTRL_HC0E               (1 << 12)
    00489 #define CS8900_SELF_CTRL_HC1E               (1 << 13)
    00490 #define CS8900_SELF_CTRL_HCB0               (1 << 14)
    00491 #define CS8900_SELF_CTRL_HCB1               (1 << 15)
    00492
    00493  * Reg 16. Self Status.
    00494 #define CS8900_SELF_STATUS_3_3_V            (1 << 6)
    00495 #define CS8900_SELF_STATUS_INITD            (1 << 7)
    00496 #define CS8900_SELF_STATUS_SIBUST           (1 << 8)
    00497 #define CS8900_SELF_STATUS_EEPROM_PRESENT   (1 << 9)
    00498 #define CS8900_SELF_STATUS_EEPROM_OK        (1 << 10)
    00499 #define CS8900_SELF_STATUS_EL_PRESENT       (1 << 11)
    00500 #define CS8900_SELF_STATUS_EE_SIZE          (1 << 12)
    00501
    00502  * Reg 17. Bus Control.
    00503 #define CS8900_BUS_CTRL_RESET_RX_DMA        (1 << 6)
    00504 #define CS8900_BUS_CTRL_USE_SA              (1 << 9)
    00505 #define CS8900_BUS_CTRL_MEMORY_ENABLE       (1 << 10)
    00506 #define CS8900_BUS_CTRL_DMA_BURST           (1 << 11)
    00507 #define CS8900_BUS_CTRL_IOCHRDYE            (1 << 12)
    00508 #define CS8900_BUS_CTRL_RX_DMA_SIZE         (1 << 13)
    00509 #define CS8900_BUS_CTRL_ENABLE_INT          (1 << 15)
    00510
    00511  * Reg 18. Bus Status.
    00512 #define CS8900_BUS_STATUS_TX_BID_ERROR      (1 << 7)
    00513 #define CS8900_BUS_STATUS_RDY_FOR_TX_NOW    (1 << 8)
    00514
    00515 */