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# prism2conf_airdrop.h

    00001 /*! \file prism2conf.h \brief Prism2 802.11b Wireless-LAN Interface Driver Configuration. */
    00002 //*****************************************************************************
    00003 //
    00004 // File Name    : 'prism2conf.h'
    00005 // Title        : Prism2 802.11b Wireless-LAN Interface Driver Configuration
    00006 // Author       : Pascal Stang
    00007 // Created      : 12/27/2004
    00008 // Revised      : 1/7/2005
    00009 // Version      : 0.1
    00010 // Target MCU   : Atmel AVR series
    00011 // Editor Tabs  : 4
    00012 //
    00013 /// \ingroup network
    00014 //
    00015 // Description  : This is the configuration file for the Prism2 802.11b
    00016 //      Wireless-LAN Controller Driver.
    00017 //
    00018 //*****************************************************************************
    00019
    00020 #ifndef PRISM2CONF_H
    00021 #define PRISM2CONF_H
    00022
    00023 // This driver supports a PRISM2 NIC connected in memory-mapped or direct I/O mode.
    00024 //
    00025 #define GENERAL_IO              0
    00026 // Direct I/O mode assumes the NIC address, data, and control lines are
    00027 // connected directly to processor I/O pins.  The memory-bus accesses are
    00028 // software emulated.
    00029 //
    00030 #define MEMORY_MAPPED           1
    00031 // *** MEMORY-MAPPED NOT YET IMPLEMENTED ***
    00032 // Memory-mapped mode assumes that the NIC is connected the processor via
    00033 // the external memory bus, and that the NIC address space starts at the
    00034 // memory location PRISM2_MEMORY_MAPPED_OFFSET.
    00035 //
    00036 // In either mode, a seperate I/O pins is required for control of the NIC's
    00037 // hardware RESET line.
    00038
    00039 // set the connection type used to communicate with the NIC
    00040 #define NIC_CONNECTION GENERAL_IO
    00041
    00042 #if NIC_CONNECTION != GENERAL_IO
    00043     // NIC is memory-mapped starting at this address
    00044     #define PRISM2_MEMORY_MAPPED_OFFSET 0x8000
    00045 #else // NIC Interface through General I/O
    00046     // PRISM2 address port
    00047     #define PRISM2_ADDRESS_PORT         PORTA
    00048     #define PRISM2_ADDRESS_DDR          DDRA
    00049     #define PRISM2_ADDRESS_MASK         0xFF
    00050     // PRISM2 high address port
    00051     #define PRISM2_HADDRESS_PORT        PORTF
    00052     #define PRISM2_HADDRESS_DDR         DDRF
    00053     #define PRISM2_HADDRESS_MASK        0x07
    00054     // PRISM2 data port
    00055     #define PRISM2_DATA_PORT            PORTC
    00056     #define PRISM2_DATA_DDR             DDRC
    00057     #define PRISM2_DATA_PIN             PINC
    00058     // PRISM2 control port
    00059     #define PRISM2_CONTROL_PORT         PORTG
    00060     #define PRISM2_CONTROL_DDR          DDRG
    00061     #define PRISM2_CONTROL_IORD         1
    00062     #define PRISM2_CONTROL_IOWR         2
    00063     #define PRISM2_CONTROL_MEMRD        0
    00064     #define PRISM2_CONTROL_MEMWR        3
    00065     // Set PRISM2 memory and I/O bus access delay
    00066     // NOTE: PRISM2 cards may not respond correctly if access time is too short or too long
    00067     // Typically good settings: MEM = ~12us,  I/O = ~1us
    00068     #define PRISM2_MEM_ACCESS_DELAY         delay_us(12)
    00069     #define PRISM2_IO_ACCESS_DELAY          { nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop(); }
    00070     //#define PRISM2_IO_ACCESS_DELAY            { nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop(); }
    00071 #endif
    00072
    00073 // PRISM2 RESET pin
    00074 #define PRISM2_RESET_PORT   PORTG
    00075 #define PRISM2_RESET_DDR    DDRG
    00076 #define PRISM2_RESET_PIN    4
    00077
    00078
    00079
    00080 // MAC address for this interface
    00081 #ifdef ETHADDR0
    00082 #define PRISM2_MAC0 ETHADDR0
    00083 #define PRISM2_MAC1 ETHADDR1
    00084 #define PRISM2_MAC2 ETHADDR2
    00085 #define PRISM2_MAC3 ETHADDR3
    00086 #define PRISM2_MAC4 ETHADDR4
    00087 #define PRISM2_MAC5 ETHADDR5
    00088 #else
    00089 #define PRISM2_MAC0 '0'
    00090 #define PRISM2_MAC1 'F'
    00091 #define PRISM2_MAC2 'F'
    00092 #define PRISM2_MAC3 'I'
    00093 #define PRISM2_MAC4 'C'
    00094 #define PRISM2_MAC5 'E'
    00095 #endif
    00096
    00097 #endif